CN114070277A - Pulse width modem circuit based on time register and control method - Google Patents
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Abstract
The invention relates to a pulse width modem circuit based on a time register, which comprises a controller, N pulse width comparators and a decision circuit, wherein the N pulse width comparators are connected with the decision circuit through a first input/output circuit; the controller is respectively connected with the input ends of the N pulse width comparators; and the decision circuit is respectively connected with the output ends of the N pulse width comparators. The invention realizes high pulse width resolution and wide range of the demodulated pulse width.
Description
Technical Field
The invention relates to a pulse width modem circuit based on a time register and a control method.
Background
Pulse width modulation is a common wireless communication modulation technique. In wireless communication, 0 and 1 data signals are often modulated into pulse width modulated signals having different pulse widths for wireless transmission, and in wireless signal reception, it is necessary to sense a change in the pulse width of a carrier and demodulate the pulse width modulated signals into 1 and 0 data signals represented by high and low levels. Most of the traditional pulse width modem circuits are realized by digital circuits, and the performance of the traditional pulse width modem circuits depends on the frequency of a sampling clock, so that the traditional pulse width modem circuits have the defects of low pulse width resolution, narrow range of the demodulated pulse width and the like.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a pulse width modem circuit based on a time register and a control method thereof, which achieve high pulse width resolution and a wide range of demodulated pulse widths.
In order to achieve the purpose, the invention adopts the following technical scheme:
a pulse width modem circuit based on a time register comprises a controller, N pulse width comparators and a decision circuit; the controller is respectively connected with the input ends of the N pulse width comparators; and the decision circuit is respectively connected with the output ends of the N pulse width comparators.
Further, the pulse width comparator comprises a first time register, a second time register, a first delay unit, a second delay unit, a first sample-and-hold unit and a second sample-and-hold unit; the output end of the first time register is respectively connected with the input ends of the first delay unit and the second sampling and holding unit; the output end of the second time register is respectively connected with the input ends of the second delay unit and the first sampling and holding unit; the output end of the first delay unit is respectively connected with the first sampling and holding unit and the second sampling and holding unit; and the output end of the second delay unit is respectively connected with the first sampling and holding unit and the second sampling and holding unit.
A control method of a pulse width modem circuit based on a time register comprises the following steps:
the controller detects pulses on the pulse width modulation input signal IN and generates N groups of control signals IN a circulating mode;
when the effective edge of the i-1 pulse IN the mth cycle on the pulse width modulation input signal IN is detected, a pulse with the pulse width LR is output on RSTi, and the ith pulse IN the mth cycle on IN is distributed to CKAi; when the effective edge of the ith pulse IN the mth cycle on the IN is detected, distributing the (i + 1) th pulse IN the mth cycle on the IN to the CKBi; when the effective edge of the (i + 1) th pulse IN the mth cycle on the IN is detected, a pulse with the pulse width LP is output on the RPCi;
when a pulse occurs on RSTi, the ith pulse width comparator will be reset; after the pulse on RSTi is finished, the pulse width comparator converts the pulse widths on the CKAi signal and the CKBi signal into electric quantity on 2 capacitors in the pulse width comparator respectively according to a proportion; when a pulse appears on the RPCi signal, the pulse width comparator will compare the difference in charge amount on the 2 capacitors and generate a pulse on QAi or QBi; when the pulse width of CKai is wider than the pulse width of CKBi, a pulse is generated on Qai; when the pulse width of CKBi is wider than the pulse width of CKai, a pulse is generated at QBi;
the decision circuit decides on the N input signals QA1, QA2, … …, QAn, and the N input signals QB1, QB2, … …, QBn; when a pulse appears on any one of the N input signals QA1, QA2, … …, QAn, the output DOUT of the decision circuit is set to a low level; when a pulse occurs on any one of the N input signals QB1, QB2, … …, QBn, the output DOUT of the decision circuit is set to a high level.
Further, each of the N sets of control signals includes RSTx, CKAx, CKBx, RPCx for driving a corresponding pulse width comparator.
Further, the pulse width comparator is specifically controlled as follows:
when the input RST1 and RST2 signals are changed to active levels, the first time register and the second time register are reset;
when the input RPC1 signal is at an effective level, the first time register outputs an SOA signal with the turnover time related to the pulse width of the input CKA signal; similarly, when the input RPC2 signal is at an active level, the second time register outputs an SOB signal with the flip time related to the pulse width of the input CKB signal;
the SOA signal is input to the first delay unit to generate an SOA _ D signal; the SOA _ D signal is input to a reference clock end CLK of a first sampling and holding unit, the first sampling and holding unit carries out sampling and holding operation on the SOB signal under the drive of the reference clock input effective clock edge, and an output signal QA is generated; meanwhile, the SOA _ D signal is input to a reset terminal of the second sampling and holding unit, and when the SOA _ D signal becomes an effective level, the second sampling and holding unit is reset;
the SOB signal is input into a second delay unit to generate an SOB _ D signal; the SOB _ D signal is input to a reference clock end CLK of the second sampling and holding unit, the second sampling and holding unit carries out sampling and holding operation on the SOA signal under the drive of the reference clock input effective clock edge, and an output signal QB is generated; meanwhile, the SOB _ D signal is input to the reset terminal of the first sample-and-hold unit, and the first sample-and-hold unit is reset when the SOB _ D signal becomes an active level.
Compared with the prior art, the invention has the following beneficial effects:
the invention can demodulate the pulse width modulation signal through the demodulator based on the time register, and compared with other pulse width modulation and demodulation modes, the invention has the advantages of high resolution of demodulation pulse width, wide range of the demodulation pulse width and the like.
Drawings
FIG. 1 is a schematic diagram of the circuit principle of the present invention;
FIG. 2 is a timing diagram of N sets of control signals in a demodulator circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the operation of a pulse width comparator circuit according to an embodiment of the present invention;
FIG. 4 is a circuit of a pulse width comparator according to an embodiment of the present invention;
FIG. 5 is a timing diagram of the input and output signals of the time register according to an embodiment of the present invention;
FIG. 6 is a timing diagram of key signals in a demodulator circuit according to an embodiment of the invention.
Detailed Description
The invention is further explained below with reference to the drawings and the embodiments.
Referring to fig. 1, the present invention provides a pulse width modem circuit based on a time register, which includes a controller, N pulse width comparators and a decision circuit; the controller is respectively connected with the input ends of the N pulse width comparators; and the decision circuit is respectively connected with the output ends of the N pulse width comparators.
Preferably, in this embodiment, a specific control method of the circuit of the present invention is as follows:
the controller detects pulses on the pulse width modulated input signal IN and cyclically generates N sets of control signals.
Each group of control signals comprises RSTx, CKAx, CKBx and RPCx and is used for driving a corresponding pulse width comparator; for example, the ith group of control signals RSTi, CKAi, CKBi and RPCi are generated and used for driving the ith pulse width comparator. Each cycle will contain N pulses on IN, and for example, the mth cycle will contain from the [ (m-1). times.N +1] th pulse to the [ (m-1). times.N + N ] th pulse on the input signal IN.
Taking the generation manner of the ith group of control signals IN the mth cycle as an example, as shown IN fig. 2, when the valid edge of the i-1 th pulse IN the mth cycle on the pwm input signal IN is detected, a pulse with the pulse width LR is output on RSTi, and the ith pulse IN the mth cycle on IN is distributed to CKAi; when the effective edge of the ith pulse IN the mth cycle on the IN is detected, distributing the (i + 1) th pulse IN the mth cycle on the IN to the CKBi; when the active edge of the i +1 th pulse IN the mth cycle on IN is detected, a pulse with pulse width LP will be output on RPCi.
Each set of control signals acts on the pulse width comparator as follows, taking the ith pulse width comparator as an example, when a pulse appears on RSTi, the ith pulse width comparator will be reset. After the pulse on RSTi is finished, the pulse width comparator converts the pulse widths on the CKAi signal and the CKBi signal into electric quantity on 2 capacitors in the pulse width comparator respectively according to a proportion; when a pulse appears on the RPCi signal, the pulse width comparator will compare the difference in the amount of charge on the 2 capacitors and produce a pulse on QAi or QBi. As shown in FIG. 6, when the pulse width of CKai is wider than the pulse width of CKBi, a pulse is generated on Qai; when the pulse width of CKBi is wider than the pulse width of CKai, a pulse is generated at QBi.
The decision circuit decides on the N input signals QA1, QA2, … …, QAn, and the N input signals QB1, QB2, … …, QBn. When a pulse appears on any one of the N input signals QA1, QA2, … …, QAn, the output DOUT of the decision circuit is set to a low level; when a pulse occurs on any one of the N input signals QB1, QB2, … …, QBn, the output DOUT of the decision circuit is set to a high level.
The high level is taken as the active level, and the falling edge is taken as the active edge. Fig. 2 shows the timing of N sets of control signals in a demodulator circuit.
In this embodiment, taking high level active as an example, the operating method of the pulse width comparator circuit in this patent is as follows: as shown in fig. 3, in the 1 st comparison, the pulse width T1 of the CKA signal is less than the pulse width T2 of the CKB signal, the pulse width comparator output QA is set to an inactive level, and QB is set to an active level; at the 2 nd comparison, the pulse width T3 of the CKA signal is equal to the pulse width T4 of the CKB signal, and both pulse width comparator outputs QA and QB are set to an inactive level; when the 3 rd comparison is performed, the pulse width T5 of the CKA signal is greater than the pulse width T6 of the CKB signal, QA output of the pulse width comparator is set to be an active level, and QB is set to be an inactive level; at the 4 th comparison, the pulse width T7 of the CKA signal is equal to the pulse width T8 of the CKB signal, and both pulse width comparator outputs QA and QB are set to an inactive level.
Preferably, referring to fig. 4, in the present embodiment, the pulse width comparator includes a first time register, a second time register, a first delay unit, a second delay unit, a first sample-and-hold unit, and a second sample-and-hold unit; the output end of the first time register is respectively connected with the input ends of the first delay unit and the second sampling and holding unit; the output end of the second time register is respectively connected with the input ends of the second delay unit and the first sampling and holding unit; the output end of the first delay unit is respectively connected with the first sampling and holding unit and the second sampling and holding unit; and the output end of the second delay unit is respectively connected with the first sampling and holding unit and the second sampling and holding unit. The input terminal of the pulse width comparator circuit includes a reset signal RST, a comparison signal CKA, a comparison signal CKB, and an output control signal RPC, and the output terminal thereof includes comparison result outputs QA and QB.
Preferably, the pulse width comparator is specifically controlled as follows:
when the input RST1 and RST2 signals are changed to active levels, the first time register and the second time register are reset;
when the input RPC1 signal is at an effective level, the first time register outputs an SOA signal with the turnover time related to the pulse width of the input CKA signal; similarly, when the input RPC2 signal is at an active level, the second time register outputs an SOB signal with the flip time related to the pulse width of the input CKB signal;
the SOA signal is input to the first delay unit to generate an SOA _ D signal; the SOA _ D signal is input to a reference clock end CLK of a first sampling and holding unit, the first sampling and holding unit carries out sampling and holding operation on the SOB signal under the drive of the reference clock input effective clock edge, and an output signal QA is generated; meanwhile, the SOA _ D signal is input to a reset terminal of the second sampling and holding unit, and when the SOA _ D signal becomes an effective level, the second sampling and holding unit is reset;
the SOB signal is input into a second delay unit to generate an SOB _ D signal; the SOB _ D signal is input to a reference clock end CLK of the second sampling and holding unit, the second sampling and holding unit carries out sampling and holding operation on the SOA signal under the drive of the reference clock input effective clock edge, and an output signal QB is generated; meanwhile, the SOB _ D signal is input to the reset terminal of the first sample-and-hold unit, and the first sample-and-hold unit is reset when the SOB _ D signal becomes an active level.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
Claims (5)
1. A pulse width modem circuit based on a time register is characterized by comprising a controller, N pulse width comparators and a decision circuit; the controller is respectively connected with the input ends of the N pulse width comparators; and the decision circuit is respectively connected with the output ends of the N pulse width comparators.
2. The time register based pulse width modem circuit according to claim 1, wherein said pulse width comparator comprises a first time register, a second time register, a first delay unit, a second delay unit, a first sample-and-hold unit, and a second sample-and-hold unit; the output end of the first time register is respectively connected with the input ends of the first delay unit and the second sampling and holding unit; the output end of the second time register is respectively connected with the input ends of the second delay unit and the first sampling and holding unit; the output end of the first delay unit is respectively connected with the first sampling and holding unit and the second sampling and holding unit; and the output end of the second delay unit is respectively connected with the first sampling and holding unit and the second sampling and holding unit.
3. The method of controlling a time register based pulse width modem circuit according to any of claims 1 or 2, comprising the steps of:
the controller detects pulses on the pulse width modulation input signal IN and generates N groups of control signals IN a circulating mode;
when the effective edge of the i-1 pulse IN the mth cycle on the pulse width modulation input signal IN is detected, a pulse with the pulse width LR is output on RSTi, and the ith pulse IN the mth cycle on IN is distributed to CKAi; when the effective edge of the ith pulse IN the mth cycle on the IN is detected, distributing the (i + 1) th pulse IN the mth cycle on the IN to the CKBi; when the effective edge of the (i + 1) th pulse IN the mth cycle on the IN is detected, a pulse with the pulse width LP is output on the RPCi;
when a pulse occurs on RSTi, the ith pulse width comparator will be reset; after the pulse on RSTi is finished, the pulse width comparator converts the pulse widths on the CKAi signal and the CKBi signal into electric quantity on 2 capacitors in the pulse width comparator respectively according to a proportion; when a pulse appears on the RPCi signal, the pulse width comparator will compare the difference in charge amount on the 2 capacitors and generate a pulse on QAi or QBi; when the pulse width of CKai is wider than the pulse width of CKBi, a pulse is generated on Qai; when the pulse width of CKBi is wider than the pulse width of CKai, a pulse is generated at QBi;
the decision circuit decides on the N input signals QA1, QA2, … …, QAn, and the N input signals QB1, QB2, … …, QBn; when a pulse appears on any one of the N input signals QA1, QA2, … …, QAn, the output DOUT of the decision circuit is set to a low level; when a pulse occurs on any one of the N input signals QB1, QB2, … …, QBn, the output DOUT of the decision circuit is set to a high level.
4. The method of claim 3, wherein each of the N sets of control signals comprises RSTx, CKAx, CKBx, RPCx for driving a corresponding pulse width comparator.
5. The method of claim 3, wherein the pulse width comparator is specifically controlled as follows:
when the input RST1 and RST2 signals are changed to active levels, the first time register and the second time register are reset;
when the input RPC1 signal is at an effective level, the first time register outputs an SOA signal with the turnover time related to the pulse width of the input CKA signal; similarly, when the input RPC2 signal is at an active level, the second time register outputs an SOB signal with the flip time related to the pulse width of the input CKB signal;
the SOA signal is input to the first delay unit to generate an SOA _ D signal; the SOA _ D signal is input to a reference clock end CLK of a first sampling and holding unit, the first sampling and holding unit carries out sampling and holding operation on the SOB signal under the drive of the reference clock input effective clock edge, and an output signal QA is generated; meanwhile, the SOA _ D signal is input to a reset terminal of the second sampling and holding unit, and when the SOA _ D signal becomes an effective level, the second sampling and holding unit is reset;
the SOB signal is input into a second delay unit to generate an SOB _ D signal; the SOB _ D signal is input to a reference clock end CLK of the second sampling and holding unit, the second sampling and holding unit carries out sampling and holding operation on the SOA signal under the drive of the reference clock input effective clock edge, and an output signal QB is generated; meanwhile, the SOB _ D signal is input to the reset terminal of the first sample-and-hold unit, and the first sample-and-hold unit is reset when the SOB _ D signal becomes an active level.
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| CN202111375140.3A CN114070277B (en) | 2021-11-19 | Pulse width modem circuit based on time register and control method |
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| CN202111375140.3A CN114070277B (en) | 2021-11-19 | Pulse width modem circuit based on time register and control method |
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| CN114070277A true CN114070277A (en) | 2022-02-18 |
| CN114070277B CN114070277B (en) | 2024-06-07 |
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|---|---|---|---|---|
| US20050030206A1 (en) * | 2003-08-08 | 2005-02-10 | Li Qiong M. | High-resolution timers and pulse width modulators |
| CN101661302A (en) * | 2009-09-27 | 2010-03-03 | 上海大学 | PWM pulse wave generation method and system on microcontroller |
| CN103516336A (en) * | 2013-09-18 | 2014-01-15 | 东莞博用电子科技有限公司 | Pulse width modulation device and method with clamping pulse width limiting function and automatic phase-shifting function |
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