CN117134786A

CN117134786A - Burst receiver and control method thereof

Info

Publication number: CN117134786A
Application number: CN202311016115.5A
Authority: CN
Inventors: 薛佳旻
Original assignee: Siruipu Microelectronics Technology Shanghai Co ltd
Current assignee: Siruipu Microelectronics Technology Shanghai Co ltd
Priority date: 2023-08-11
Filing date: 2023-08-11
Publication date: 2023-11-28

Abstract

The invention discloses a burst type receiver and a control method thereof, wherein the burst type receiver comprises: comparator, offset voltage generating circuit and related control circuit. The offset voltage generation circuit is used for generating offset voltage to adjust the turnover threshold value of the receiver; the control circuit is used for controlling the offset voltage generation circuit based on the first control signal so as to convey the offset voltage to the first input end or the second input end of the comparator. According to the burst type receiver and the control method thereof, the anti-electromagnetic interference capability of the burst type receiver in an idle state is enhanced, and the defects of aggravation of output signal jitter, increase of circuit power consumption, increase of transmission delay and the like caused by increasing of hysteresis voltage of a comparator in a traditional scheme are avoided. The offset voltage generating circuit, the control circuit, the digital filter and the training control logic module which are matched with each other are flexible in design, strong in expansibility and convenient to adjust according to application scenes.

Description

Burst receiver and control method thereof

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a burst receiver and a control method thereof.

Background

In the practical application scenario of the burst receiver, electromagnetic interference in the environment can be coupled to the transmission cable, and due to non-ideal cable characteristics, an interference signal is partially converted into a differential signal at the input end of the receiver, so that the normal operation of the receiver is influenced. The working state of the burst receiver can be divided into a useful signal receiving state and an idle state, and in the useful signal receiving state, the influence of the superimposed interference signal on the receiver is small due to the fact that the amplitude of the useful signal is large and the rising and falling edges are steep. However, in the idle state, the interfering signal dominates because there is no useful signal, which may cause irregular transitions in the receiver output. The state of waiting for the next set of input data to be temporary is called an idle state, and in the idle state, the receiver needs to keep a constant output value and no irregular jump occurs along with various electromagnetic interferences in the environment, so that the error data is prevented from being sent to a post-level digital processing circuit.

Existing burst receivers typically employ comparators with hysteresis capability within them to achieve their immunity to electromagnetic interference. However, in this method, it is necessary to increase the hysteresis voltage window of the comparator in order to obtain a relatively strong anti-jamming capability. The disadvantage of this is that the large hysteresis voltage window causes the comparator to consume more current at the same working speed, and at the same time increases the overall transmission delay of the receiver.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a burst receiver and a control method thereof, which can improve the electromagnetic interference resistance of the burst receiver under the condition of not increasing the hysteresis voltage window of a comparator.

To achieve the above object, an embodiment of the present invention provides a burst receiver including: the offset voltage generation circuit comprises a comparator, an offset voltage generation circuit and a control circuit.

The comparator is provided with a first input end, a second input end and an output end; the offset voltage generation circuit is used for generating offset voltages; the control circuit is used for controlling the offset voltage generation circuit based on the first control signal so as to convey the offset voltage to the first input end or the second input end of the comparator.

In one or more embodiments of the present invention, the control circuit includes a selection switching module and a first D flip-flop, a D input terminal of the first D flip-flop is connected to a power supply voltage, a Reset input terminal of the first D flip-flop is configured to receive a first control signal, a Q output terminal of the first D flip-flop is connected to the selection switching module to generate a third control signal, and the selection switching module controls on-off between the offset voltage generating circuit and the first input terminal or the second input terminal of the comparator based on the third control signal.

In one or more embodiments of the present invention, the selection switching module includes a first selector, a second selector, and an inverter, where a first input terminal of the first selector, a first input terminal of the second selector is connected to a Q output terminal of the first D flip-flop, a second input terminal of the first selector, a second input terminal of the second selector is connected to a reference voltage, an input terminal of the inverter is connected to a control terminal of the first selector, an output terminal of the inverter is connected to a control terminal of the second selector, and output terminals of the first selector and the second selector are connected to an offset voltage generating circuit.

In one or more embodiments of the present invention, the burst receiver further includes a digital filter that generates a second control signal that controls the control circuit to turn off the offset voltage generation circuit based on the output signal of the comparator and the first control signal.

In one or more embodiments of the invention, the digital filter includes a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first or gate, a second or gate, a third or gate, and an and gate;

the Q output end of the second D trigger is connected with the D input end of the third D trigger, the Q output end of the third D trigger is connected with the D input end of the fourth D trigger, the Q output end of the fourth D trigger is connected with the D input end of the fifth D trigger, the CK input end of the second D trigger, the CK input end of the third D trigger, the CK input end of the fourth D trigger and the CK input end of the fifth D trigger are connected with the output end of the comparator, the Reset input end of the second D trigger, the Reset input end of the third D trigger, the Reset input end of the fourth D trigger and the Reset input end of the fifth D trigger are used for receiving a first control signal, the first input end of the first OR gate is connected with the Q output end of the fifth D trigger, the first input end of the second OR gate is connected with the Q output end of the fourth D trigger, the first input end of the third OR gate is connected with the output end of the third D trigger, the second output end of the second OR gate is connected with the Q output end of the third OR gate, the second output end of the second OR gate is connected with the first OR gate, the first OR gate is connected with the first OR gate input end of the third OR gate, the second OR gate is connected with the first OR gate input end, the third OR gate is connected with the third OR gate input end, and the third OR gate is connected with the third OR gate input.

In one or more embodiments of the present invention, the burst receiver further includes a training control logic module for adjusting the magnitude of the offset voltage generated by the offset voltage generating circuit based on the output signal of the comparator.

In one or more embodiments of the invention, the offset voltage generation circuit includes a current mode digital-to-analog converter or a variable resistor array circuit.

The invention also discloses a control method of the burst receiver, which comprises the following steps:

judging whether the receiver is in an idle state or not based on the first control signal;

if the receiver is in an idle state, the offset voltage generating circuit is controlled by the control circuit based on the first control signal so as to transmit the offset voltage to the first input end or the second input end of the comparator;

if the output signal of the comparator generates effective jump, the offset voltage generating circuit is turned off by the control circuit.

In one or more embodiments of the present invention, the magnitude of the offset voltage generated by the offset voltage generation circuit is adjusted based on the output signal of the comparator by training the control logic module when the receiver is enabled.

In one or more embodiments of the present invention, the offset voltage is adjusted to a preset value by training the control logic module, and the number of false hops generated by the output signal of the comparator is counted, and the offset voltage is adjusted according to the number of false hops of the output signal of the comparator in the counting interval until the output signal of the comparator does not false hops any more in the counting interval.

In one or more embodiments of the present invention, the control circuit is controlled to turn off the offset voltage generation circuit based on an effective output signal of the comparator by the digital filter.

Compared with the prior art, according to the burst receiver and the control method thereof, the offset voltage generation circuit is controlled by the control circuit based on the first control signal so as to transmit the offset voltage to the first input end or the second input end of the comparator, so that the electromagnetic interference resistance of the burst receiver in an idle state is enhanced, and the defects of aggravation of output signal jitter, increase of circuit power consumption, increase of transmission delay and the like caused by increasing the hysteresis voltage of the comparator in the traditional scheme are avoided. The offset voltage generating circuit, the control circuit, the digital filter and the training control logic module which are matched with each other are flexible in design, strong in expansibility and convenient to adjust according to application scenes.

Drawings

Fig. 1 is a schematic circuit diagram of a burst receiver according to an embodiment of the present invention.

Fig. 2 is a graph showing a comparison of voltage transmission characteristic curves of a comparator according to an embodiment of the present invention.

Fig. 3 is a schematic circuit diagram of an offset voltage generation circuit according to another embodiment of the present invention.

Fig. 4 is a schematic circuit diagram of an offset voltage generation circuit according to another embodiment of the present invention.

Fig. 5 is a circuit schematic of a digital filter according to an embodiment of the invention.

Fig. 6 is a waveform diagram of a burst receiver according to an embodiment of the present invention.

Fig. 7 is a flowchart of a control method of a burst receiver according to an embodiment of the present invention.

Detailed Description

Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.

The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.

As shown in fig. 1, a burst receiver includes: RC network 10, preamplifier 20, comparator 30, offset voltage generation circuit 40, control circuit 50, digital filter 60, and training control logic module 70. The RC network 10, the preamplifier 20 and the comparator 30 are connected in sequence.

The comparator 30 has a first input terminal IP, a second input terminal IN, and an output terminal OUT, and IN one embodiment, the comparator 30 is a hysteresis comparator. The offset voltage generating circuit 40 is used for generating an offset voltage Voff. The control circuit 50 is configured to control the offset voltage generating circuit based on the first control signal RESET to supply the offset voltage Voff to the first input terminal IP or the second input terminal IN of the comparator 30. The digital filter 60 generates a second control signal to control the control circuit 50 to turn off the offset voltage generation circuit 40 based on the output signal RXOUT of the comparator 30 and the first control signal RESET. The training control logic module 70 is configured to adjust the magnitude of the offset voltage Voff generated by the offset voltage generating circuit 40 based on the output signal RXOUT of the comparator 30.

As shown in fig. 1, the control circuit 50 includes a selection switching module and a first D flip-flop D1. The D input terminal of the first D flip-flop D1 is connected to the power supply voltage, the Reset input terminal of the first D flip-flop D1 is configured to receive the first control signal Reset, the Q output terminal of the first D flip-flop D1 is connected to the selection switch module to generate the third control signal, and the CK terminal of the first D flip-flop D1 is connected to the output terminal of the digital filter 60, that is, the second control signal is transmitted as the clock signal of the first D flip-flop D1 to the CK terminal of the first D flip-flop D1. The selection switching module controls on/off between the offset voltage generating circuit 40 and the first input terminal IP or the second input terminal IN of the comparator 30 based on the third control signal.

The selection switching module includes a first selector 501, a second selector 502, and an inverter 503. The first input terminal of the first selector 501 and the first input terminal of the second selector 502 are connected to the Q output terminal of the first D flip-flop D1, the second input terminal of the first selector 501 and the second input terminal of the second selector 502 are connected to the reference voltage, the input terminal of the inverter 503 is connected to the control terminal of the first selector 501, the output terminal of the inverter 503 is connected to the control terminal of the second selector 502, and the output terminals of the first selector 501 and the second selector 502 are connected to the offset voltage generating circuit 40.

Offset voltage generation circuit 40 includes a current-mode digital-to-analog converter coupled to first input terminal IP and second input terminal IN of comparator 30.

As shown IN fig. 1, IN one embodiment, the current-mode digital-to-analog converter includes a first current source I1 and a second current source I2 connected to the training control logic module 70, a first switch K1 connected to the first current source I1, and a second switch K2 connected to the second current source I2, where the first switch K1 is simultaneously connected to the first input terminal IP of the comparator 30, and the second switch K2 is simultaneously connected to the second input terminal IN of the comparator 30.

The output signal of the first selector 501 is used to control the on and off of the first switch K1, and the output signal of the second selector 502 is used to control the on and off of the first switch K1. In an embodiment, the first switch K1 and the second switch K2 may be MOS transistors. When the first switch K1 is turned on, the offset voltage Voff is injected to the first input terminal IP of the comparator 30 through the first current source I1; when the second switch K2 is turned on, the offset voltage Voff is injected to the second input terminal IN of the comparator 30 through the second current source I2.

The operation of the receiver is divided into two states, namely a normal receiving state and an idle state, and the difference is whether an offset voltage Voff is applied to the input terminal of the comparator 30. The switching of the two states is controlled by the first control signal RESET provided by the digital circuit and by the transition edge of the output signal RXOUT of the comparator 30, which can be illustrated by the voltage transfer characteristic of the comparator 30. As shown in fig. 2, the waveform diagram on the left side of fig. 2 is in a normal receiving state, and at this time, the suppression of the interference by the comparator 30 is realized by the self-hysteresis voltage, which is a relatively small value, so that the jitter of the output signal RXOUT is not deteriorated, but at the same time, the anti-interference capability is weak, because it can only suppress the interference signal with the amplitude smaller than the hysteresis voltage.

After a group of data is received, the receiver needs to enter an idle state, the digital circuit controls the first control signal RESET to give high-level pulse, so that the output of the first D flip-flop D1 is RESET, and the control signal output by the first D flip-flop D1 controls the current-mode digital-to-analog converter (the first switch K1 or the second switch K2 is turned on) with the corresponding polarity to be turned on after passing through the selective switching module, so that the offset voltage Voff with the expected magnitude and polarity is generated at the first input end IP or the second input end IN of the comparator 30.

At this time, the voltage transmission characteristic curve of the comparator 30 is switched from left to right (assuming that the polarity of the added offset voltage Voff is negative), and the change is represented by the translation of the whole curve, which makes the receiver output set to a low level, and the output of the receiver jumps from the low level to a high level only when the input signal of the comparator 30 is greater than the sum of the offset voltage Voff and the hysteresis voltage Vhys, which means that the receiver can immunity to an interference signal with an amplitude smaller than the value, which is about several times the magnitude of the hysteresis voltage Vhys, so that the large anti-interference amplitude is difficult to be realized by directly increasing the hysteresis voltage Vhys of the comparator 30 in the conventional method, although the amplitude of the useful signal is still a small value compared with that of the useful signal, so that the reception error of the useful signal is not caused, but since the signal distortion is introduced into the input end of the comparator 30, the output jitter performance is affected to some extent, and the current-type digital-analog converter needs to be turned off in time after entering the normal receiving state.

As shown in fig. 1, the training control logic module 70 changes the magnitude of the offset voltage Voff by controlling the turn-on magnitudes of the first current source I1 and the second current source I2. In an embodiment, the first current source I1 and the second current source I2 may be implemented by a current mirror structure.

IN an embodiment, after the receiver is enabled, the training control logic module 70 selects whether to enter the training mode according to the control word, if the training mode is selected, the state opportunity IN the training control logic module 70 adjusts the gear of the current mode digital-to-analog converter to the lowest, that is, the minimum offset voltage Voff is introduced into the first input terminal IP and the second input terminal IN of the comparator 30, then a count is entered for a period of time, if a plurality of hops are detected IN the count interval of the output signal RXOUT of the comparator 30, it is indicated that the receiver has a false hop caused by the interference signal IN the actual environment or the artificially introduced interference signal, at this time, the training control logic module 70 increases the gear of the current mode digital-to-analog converter, that is, increases the introduced offset voltage Voff, counts again until no false hop exists IN the output of the comparator 30 IN the count interval, the value of the introduced offset voltage Voff is considered to be the most reasonable, and the output value of the training control logic module 70 keeps the current result unchanged.

The reason why the value of the offset voltage Voff is selected in this way is that in different application environments, under the influence of factors such as different cable lengths and different anti-interference indexes, the value of the required offset voltage Voff is different, and the offset voltage Voff cannot be increased uniformly, because an excessive offset voltage Voff can cause the receiver to have great input signal distortion in the first few symbol periods which are not switched back to the normal receiving state, which leads to serious jitter in the output signal RXOUT of the comparator 30 in the first few periods, and if the jitter exceeds the tolerance of the subsequent circuit, reception errors can be caused. Therefore, we need to select the value of offset voltage Voff reasonably, and take a small value as much as possible to reduce the influence on the jitter performance of the output signal RXOUT on the premise of meeting the anti-interference requirement.

In other embodiments, offset voltage generation circuit 40 includes a variable resistor array circuit. The variable resistor array circuit includes two resistance variable modules based on the first input terminal IP and the second input terminal IN of the comparator 30, wherein one resistance variable module is composed of a set of first resistors R1 and a set of third switches K3, and the other resistance variable module is composed of a set of second resistors R2 and a set of fourth switches K4.

As shown IN fig. 3, a set of first resistors R1 may be connected IN series with each other and between the power supply voltage and the first input terminal IP of the comparator 30, a set of second resistors R2 may be connected IN series with each other and between the power supply voltage and the second input terminal IN of the comparator 30, and the third switches K3 may be connected IN parallel to both ends of the first resistors R1, the fourth switches K4 may be connected IN parallel to both ends of the second resistors R2, the third switches K3 and the fourth switches K4 may be turned on and off under the control of the training control logic module 70, the number of the first resistors R1, the second resistors R2, the third switches K3 and the fourth switches K4 may be increased or decreased as needed, three first resistors R1, two third switches K3, three second resistors R2 and two fourth switches K4 may be selected, the third switches K3 may be connected IN parallel to two of the first resistors R1, and the fourth switches K4 may be connected IN parallel to two of the second resistors R2.

As shown IN fig. 4, a set of first resistors R1 may be connected IN parallel between the power supply voltage and the first input terminal IP of the comparator 30, a set of second resistors R2 may be connected IN parallel between the power supply voltage and the second input terminal IN of the comparator 30, a third switch K3 may be selectively connected IN series to a branch where the first resistors R1 are located, a fourth switch K4 may be connected IN series to a branch where the second resistors R2 are located, the third switch K3 and the fourth switch K4 are controlled by the training control logic module 70 to be turned on and off, the number of the first resistors R1, the second resistors R2, the third switch K3 and the fourth switch K4 may be increased or decreased as needed, three first resistors R1, two third switches K3, three second resistors R2 and two fourth switches K4 may be selected, a third switch K3 may be connected IN series to a branch where the two first resistors R1 are located, and a fourth switch K4 may be connected IN series to a branch where the two second resistors R2 are located.

IN addition, a first total switch and a second total switch similar to the first switch K1 and the second switch K2 are also provided between the first input terminal IP and the second input terminal IN of the comparator 30 and the two resistance variable modules, respectively, and are controlled to be turned on and off by control signals output from the first selector 501 and the second selector 502, respectively.

In addition, the resistance variable module can also adopt a series-parallel structure of a plurality of resistors which are connected in series and in parallel, and then the quantity of the resistors in the resistance access circuit is controlled through each switch to change the size of the offset voltage Voff.

As shown in fig. 5, the digital filter 60 includes a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a first or gate O1, a second or gate O2, a third or gate O3, AND an AND gate AND.

The Q output of the second D flip-flop D2 is connected to the D input of the third D flip-flop D3, the Q output of the third D flip-flop D3 is connected to the D input of the fourth D flip-flop D4, the Q output of the fourth D flip-flop D4 is connected to the D input of the fifth D flip-flop D5, the CK input of the second D flip-flop D2, the CK input of the third D flip-flop D3, the CK input of the fourth D flip-flop D4, and the CK input of the fifth D flip-flop D5 are connected to the output of the comparator 30. The Reset input end of the second D flip-flop D2, the Reset input end of the third D flip-flop D3, the Reset input end of the fourth D flip-flop D4 and the Reset input end of the fifth D flip-flop D5 are used for receiving the first control signal Reset, the first input end of the first or gate O1 is connected with the Q output end of the fifth D flip-flop D5, the first input end of the second or gate O2 is connected with the Q output end of the fourth D flip-flop D4, the first input end of the third or gate O3 is connected with the Q output end of the third D flip-flop D3, and the second input end of the first or gate O1, the second input end of the second or gate O2 and the second input end of the third or gate O3 are used for receiving corresponding level control signals. The first input of the AND gate AND is connected to the output of the first or gate O1, the second input of the AND gate AND is connected to the output of the second or gate O2, the third input of the AND gate AND is connected to the output of the third or gate O3, the fourth input of the AND gate AND is connected to the Q output of the second D flip-flop D2, AND the output of the AND gate AND is connected to the control circuit 50.

The output signal RXOUT of the comparator 30 is filtered by the digital filter 60, and the filtered result is used as a clock of the first D flip-flop D1 in the circuit, and when the first D flip-flop D1 jumps from low level to high level, the first D flip-flop D1 is set, so that the offset voltage generating circuit 40 is turned off, and the offset voltage Voff disappears.

If the level control signals g2, g3, g4 are all low, the output of the AND gate AND will transition to high only after four valid clock edges, i.e. the receiver will consider the next valid data to have arrived after detecting four valid transitions of the output signal RXOUT of the comparator 30.

The purpose of the digital filter 60 is to enhance the robustness between the offset voltage generation circuit 40 and the control circuit 50, to make it insensitive to the occasional glitches and to avoid erroneous state switching.

By varying the values of the level control signals g2, g3, g4, the bandwidth of the digital filter 60 can be controlled. For example, when the level control signals g4 AND g3 are high AND the level control signal g2 is low, the output of the AND gate AND is enabled after the effective transition edge occurs twice, AND the filtering effect of the digital filter 60 on the glitch is reduced, but the switching of the offset voltage generating circuit 40 can be completed more quickly, so that flexible control can be performed according to the actual situation.

When the reception of one set of data is completed, the high pulse of the new incoming first control signal RESET will cause the receiver to switch to the idle state again, while the digital filter 60 is RESET, and the waiting for the next set of data starts.

In other embodiments, the number of D flip-flops and or gates may be changed according to the number of valid clock edges that need to be passed to switch the offset voltage generating circuit 40, and if the number of valid clock edges needs to be increased to switch the offset voltage generating circuit 40 off, the number of D flip-flops and or gates is increased, and otherwise, the number of D flip-flops and or gates is decreased. The digital filter 60 may be replaced by a digital filter composed of a counter.

The offset voltage generating circuit 40, the control circuit 50, the digital filter 60 and the training control logic module 70 cooperate with each other to enable the designed receiver to have a large useful signal amplitude identification threshold value in an idle state, and for the interference signals with the voltage amplitude smaller than the threshold value, the receiver always outputs a constant low level or high level. When the receiver receives the useful signal, that is, when the voltage jump edge exceeding the threshold value occurs, the receiver considers that the normal receiving state is currently entered, and the signal voltage identification threshold value returns to zero level at the moment, and normal signal receiving is started. The signal voltage identification threshold is set reasonably, so that the maximum electromagnetic interference resistance can be obtained on the premise that useful signals can be received, the offset voltage training function can be started before the receiver works, and the most reasonable turnover threshold is trained by receiving interference signals in an actual working environment or adding expected interference signals to a cable artificially.

As shown in fig. 6, the signal RXIN is the input signal to the receiver, electromagnetic interference in the environment is coupled to the cable and due to cable imperfections, the interference signal partially converts to a differential signal at the input of the receiver, which is superimposed on the useful signal and affects the normal operation of the receiver.

In the useful signal receiving state, the amplitude of the useful signal is larger, the rising and falling edges are steeper, and the influence of the superimposed interference signal on the output of the receiver is smaller. However, in the idle state, there is no useful signal, and the interference signal dominates, which may cause irregular transitions in the output of the receiver, which is undesirable for the post-stage digital processing circuit, such as signal RXOUT (before) in fig. 6, which is the output signal of the receiver before the improvement.

For a receiver employing offset voltage generation circuit 40, control circuit 50, digital filter 60 and training control logic 70 as mentioned above, after receiving a set of useful data, the switching threshold is set using the first control signal RESET pulse provided by the digital circuit so that the receiver has a large signal voltage identification threshold in the subsequent idle state so that the receiver output does not flip with the interfering signal but is constant at a set value (high or low), such as signal RXOUT (after) in fig. 6, which is the modified receiver output signal.

The above manner makes the receiver have strong anti-electromagnetic interference capability in idle state, and avoids the disadvantages caused by the conventional methods of aggravation of the output signal RXOUT jitter, increase of circuit power consumption, increase of transmission delay and the like in the process of receiving the useful signal because no additional delay voltage of the comparator 30 is required to be added.

As shown in fig. 7, the invention also discloses a control method of the burst receiver, which comprises the following steps:

and judging whether the receiver is in an idle state or not based on a first control signal RESET, wherein the first control signal RESET is generated by a digital circuit, and when the first control signal RESET generates a high-level pulse, the receiver is indicated to be in the idle state.

If the receiver is in the idle state, the control circuit 50 controls the offset voltage generating circuit 40 based on the first control signal RESET, and the offset voltage generating circuit 40 is turned on to transmit the offset voltage Voff to the first input terminal or the second input terminal of the comparator 30.

Whether the output signal RXOUT of the comparator 30 generates a valid transition is determined, if the output signal RXOUT of the comparator 30 generates a valid transition, whether the digital filter 60 outputs a valid signal is determined, and if the digital filter 60 outputs a valid signal, the control circuit 50 is controlled by the valid signal to turn off the offset voltage generating circuit 40. The digital filter 60 output valid signal condition may be based on the number of valid transitions produced by the output signal RXOUT, which may be detected by the digital filter 60 and varied by changing the configuration of the digital filter 60.

In addition, in the initial state, firstly confirming whether the receiver is enabled; when the receiver is enabled, it is determined whether to turn on the training control logic module 70 for training, if the training is required, the magnitude of the offset voltage Voff generated by the offset voltage generating circuit 40 is adjusted by the training control logic module 70 based on the output signal RXOUT of the comparator 30, and if the training is not required, the training control logic module 70 is not turned on, the offset voltage generating circuit 40 generates the default offset voltage Voff.

Specifically, the offset voltage Voff is first adjusted to a preset value (generally, the minimum value) by the training control logic module 70, and the number of false transitions generated by the output signal RXOUT of the comparator 30 is counted to confirm whether the output signal RXOUT of the comparator 30 keeps a constant level for a long time, and then the offset voltage Voff is adjusted according to the number of false transitions of the output signal RXOUT of the comparator 30 in the counting interval until the false transitions are not generated in the output signal RXOUT of the comparator 30 in the counting interval, that is, the output signal RXOUT of the comparator 30 cannot keep the constant level for a long time, and then the offset voltage Voff is increased by adjusting the offset voltage generating circuit 40; the offset voltage Voff is maintained at a constant level for a long period of time when the output signal RXOUT of the comparator 30 is outputted.

The invention also discloses a chip comprising the burst type receiver.

The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teachings or may be acquired from other forms, structures, arrangements, proportions, and with other components, materials and parts. The exemplary embodiments were chosen and described in order to explain the principles of the invention and its practical application to thereby enable others skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A burst receiver, comprising:

a comparator having a first input, a second input, and an output;

the offset voltage generation circuit is used for generating offset voltages;

and the control circuit is used for controlling the offset voltage generation circuit based on the first control signal so as to convey the offset voltage to the first input end or the second input end of the comparator.

2. The burst receiver of claim 1, wherein the control circuit comprises a selection switching module and a first D flip-flop, a D input of the first D flip-flop being coupled to a supply voltage, a Reset input of the first D flip-flop being configured to receive the first control signal, a Q output of the first D flip-flop being coupled to the selection switching module to generate the third control signal, the selection switching module controlling an on-off between the offset voltage generating circuit and the first input or the second input of the comparator based on the third control signal.

3. The burst receiver of claim 2, wherein the selection switching module comprises a first selector, a second selector, and an inverter, the first input of the first selector, the first input of the second selector being coupled to the Q output of the first D flip-flop, the second input of the first selector, the second input of the second selector being coupled to a reference voltage, the input of the inverter being coupled to the control of the first selector, the output of the inverter being coupled to the control of the second selector, the output of the first selector and the output of the second selector being coupled to the offset voltage generating circuit.

4. The burst receiver of claim 1, further comprising a digital filter that generates the second control signal that controls the control circuit to turn off the offset voltage generation circuit based on the output signal of the comparator and the first control signal.

5. The burst receiver of claim 4, wherein the digital filter comprises a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first or gate, a second or gate, a third or gate, and an and gate;

6. The burst receiver of claim 1, further comprising a training control logic module to adjust the magnitude of the offset voltage generated by the offset voltage generation circuit based on the output signal of the comparator.

7. The burst receiver of claim 1, wherein the offset voltage generation circuit comprises a current mode digital-to-analog converter or a variable resistor array circuit.

8. A method for controlling a burst receiver, comprising:

9. The control method of burst receiver as claimed in claim 8, wherein the magnitude of the offset voltage generated by the offset voltage generating circuit is adjusted based on the output signal of the comparator by training the control logic module when the receiver is enabled.

10. The control method of burst receiver as claimed in claim 9, wherein the offset voltage is adjusted to a preset value by training the control logic module, and the number of false transitions generated by the output signal of the comparator is counted, and the offset voltage is adjusted according to the number of false transitions of the output signal of the comparator in the counting interval until the output signal of the comparator is not false transitions any more in the counting interval.

11. The control method of the burst receiver according to claim 8, wherein the control circuit is controlled to turn off the offset voltage generation circuit based on an effective output signal of the comparator by the digital filter.