CN114070058A

CN114070058A - Voltage comparator and method

Info

Publication number: CN114070058A
Application number: CN202110863231.5A
Authority: CN
Inventors: S·奥特; D·达维诺
Original assignee: STMicroelectronics Rousset SAS
Current assignee: STMicroelectronics Rousset SAS
Priority date: 2020-07-30
Filing date: 2021-07-29
Publication date: 2022-02-18
Also published as: FR3113139A1; CN216904672U; US20220038003A1; US11736018B2; FR3113139B1; EP3945673B1; EP3945673A1

Abstract

Voltage comparators and methods are disclosed. An embodiment electronic device includes: a first circuit including a first transistor and a second transistor coupled in series between a node to which a power supply voltage is applied and a node to which a reference voltage is applied, the first transistor and the second transistor being coupled to each other through a first node; and a second circuit configured to compare the first voltage on the first node to a first voltage threshold and a second voltage threshold.

Description

Voltage comparator and method

Cross Reference to Related Applications

The present application claims the benefit of french application No. 2008088, filed on 30/7/2020, which is incorporated herein by reference.

Technical Field

The present disclosure relates generally to electronic devices, and more particularly to devices including circuitry configured to determine whether a voltage is within a determined range, e.g., a DC/DC voltage converter of a switched mode power supply type including such circuitry, converting a DC supply voltage to a DC output voltage, e.g., a buck-type DC/DC voltage converter, where the value of the DC output voltage is lower than the value of the DC supply voltage.

Background

In a switched mode power converter, a Direct Current (DC) voltage used to power the converter is chopped by the switching of switches to achieve a power storage phase in an assembly comprising an inductive element and a capacitive element and a phase of transferring the power stored in the assembly to a load connected to the output of the converter.

In a Pulse Frequency Modulation (PFM) type of switched mode converter, each operating cycle of the converter comprises a phase of storing power in the components, followed by a phase of delivering power to a load connected to the converter. During the power storage phase, the current flowing through the inductive element increases. During the power transfer phase, the current flowing through the inductive element is reduced. For each operating cycle, it is desirable that the current flowing through the inductive element be zero at the beginning of the power storage phase and at the end of the power transfer phase.

Known switched mode converters, in particular of the PFM type, have various drawbacks.

Disclosure of Invention

One embodiment overcomes all or part of the disadvantages of known devices that include circuitry configured to determine a sign of a current.

An embodiment electronic device includes: a first circuit including a first transistor and a second transistor coupled in series between a node to which a power supply voltage is applied and a node to which a reference voltage is applied, the first transistor and the second transistor being coupled to each other through a first node; and a second circuit configured to compare the first voltage on the first node to a first voltage threshold and a second voltage threshold.

An embodiment method of controlling an electronic device comprises: a first circuit including a first transistor and a second transistor coupled in series between a node to which a power supply voltage is applied and a node to which a reference voltage is applied, the first transistor and the second transistor being coupled to each other through a first node; and a second circuit to compare the first voltage on the first node to a first voltage threshold and a second voltage threshold.

According to one embodiment, the second circuit comprises a third transistor and a fourth transistor coupled in series between the second node and a third node, the third transistor and the fourth transistor being coupled to each other via the fourth node, the fourth node being coupled to the first node.

According to one embodiment, the second node is coupled to a node to which the power supply voltage is applied through the first resistive element, and the third node is coupled to a node to which the reference voltage is applied through the second resistive element.

According to one embodiment, a control terminal of the third transistor is coupled to a node to which the second voltage threshold is applied, and a control terminal of the fourth transistor is coupled to a node to which the first voltage threshold is applied.

According to one embodiment, the first voltage threshold is a supply voltage and the second voltage threshold is a reference voltage.

According to one embodiment, the second circuit comprises: a first output node having a signal provided thereon, the first output node taking a first value when the first voltage is greater than a first voltage threshold and taking a second value when the first voltage is less than the first voltage threshold; and a second output node having a signal provided thereon, the first value being taken when the first voltage is less than the second voltage threshold and the second value being taken when the first voltage is greater than the second voltage threshold.

According to one embodiment, the first output node is coupled to the second node, and the second output node is coupled to the third node.

According to one embodiment, the first output node is coupled to the second node through two inverter circuits, and the second output node is coupled to the third node through an inverting circuit.

According to one embodiment, the first transistor is connected in parallel with a first diode, the second transistor is connected in parallel with a second diode, and an anode of the first diode and a cathode of the second diode are connected to the first node.

According to one embodiment, the device is a switched mode power supply.

According to one embodiment, the apparatus includes a third circuit configured to compare the first voltage to a second voltage, the second voltage being variable and dependent on signals on the first output node and the second output node.

According to one embodiment, the device comprises a fourth circuit configured to control the first transistor and the second transistor in such a way that each operating cycle comprises successively: a first stage during which the first transistor is turned on and the second transistor is turned off; a second stage during which the first transistor and the second transistor are off; a third stage during which the first transistor is off and the second transistor is on; and a fourth stage during which the first transistor and the second transistor are turned off.

According to one embodiment, the variation of the second voltage is dependent on the signals on the first output node and the second output node during the fourth phase.

Drawings

The above features and advantages, and others, will be described in detail in the following description of particular embodiments, which is given by way of illustration and not of limitation, with reference to the accompanying drawings, in which:

FIG. 1 illustrates an embodiment of an electronic device including circuitry configured to determine whether a voltage is within a voltage range;

FIG. 2 shows a timing diagram illustrating the operation of the embodiment of FIG. 1;

FIG. 3 shows a timing diagram illustrating the operation of the embodiment of FIG. 1;

fig. 4 schematically shows an embodiment of a DC/DC voltage converter;

FIG. 5 shows a timing diagram illustrating an example of the operation of the converter of FIG. 4;

FIG. 6 shows other timing diagrams illustrating the expected or theoretical operation and the real or actual operation of the converter of FIG. 4;

FIG. 7 shows an embodiment of a DC/DC voltage converter including the embodiment of FIG. 1; and

fig. 8 shows a timing diagram illustrating an example of the operation of the embodiment of fig. 7.

Detailed Description

In the different figures, the same features have been designated by the same reference. In particular, structural and/or functional features that are common among the various embodiments may have the same references and may be provided with the same structural, dimensional, and material characteristics.

For the sake of clarity, only steps and elements useful for understanding the embodiments described herein are illustrated and described in detail.

Unless otherwise stated, when two elements are referred to as being connected together, this means that there is no direct connection of any intervening elements other than conductors, and when two elements are referred to as being coupled together, this means that the two elements may be connected, or they may be coupled, by one or more other elements.

In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers, such as the terms "front", "back", "upper", "lower", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "higher", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., the orientations shown in the figures are referred to.

Unless otherwise indicated, "about", "substantially" and "approximately" mean within 10%, preferably within 5%.

Fig. 1 illustrates an electronic device including an embodiment of a circuit 10, the circuit 10 configured to determine whether an input voltage is within a voltage range. In other words, the circuit 10 is configured to compare the input voltage with a first voltage threshold and a second voltage threshold that are different from each other.

The device comprises a circuit 20, for example a power stage. Circuit 20 is an example of a circuit configured to generate an input voltage for circuit 10. Circuit 20 includes two

transistors

202 and 204.

Transistors

202 and 204 are coupled (preferably in series) between rail 3, to which a supply voltage Vbat is applied, and rail 5, to which a reference voltage (e.g., ground GND) is applied. In other words, one conductive terminal (source or drain) of transistor 202 is coupled (preferably connected) to rail 3, while the other conductive terminal (drain or source) is coupled (preferably connected) to center node 206. One conducting terminal (source or drain) of transistor 204 is coupled (preferably connected) to node 206 and its other conducting terminal (drain or source) is coupled (preferably connected) to rail 5.

Preferably, transistor 202 is a P-type field effect or PMOS transistor and transistor 204 is an N-type field effect or NMOS transistor.

The circuit 20 includes two

inputs

208 and 210. Input 208 receives a signal GP for controlling transistor 202. Thus, the input 208 is coupled (preferably connected) to a control terminal or gate of the transistor 202. Input 210 receives a control signal GN for transistor 204. Thus, input 210 is coupled (preferably connected) to a control terminal or gate of transistor 204.

Node 206 is coupled (preferably connected) to input node 102 of circuit 10. Current Ic is provided to the input of circuit 10 through

nodes

206 and 102. Similarly, the voltage VLX on node 206 is provided to the input node 102 of the circuit 10. In operation, node 206 is coupled to a load, for example, which is powered by circuitry 20.

The circuit 20 also includes two

diodes

218 and 220.

Diodes

218 and 220 are coupled in series between track 3 and track 5. More specifically, a first terminal (anode or cathode) of diode 220 is coupled (preferably connected) to rail 5, and a second terminal (cathode or anode) of diode 220 is coupled (preferably connected) to node 206. A first terminal (anode or cathode) of diode 218 is coupled (preferably connected) to node 206 and a second terminal (cathode or anode) of diode 218 is coupled (preferably connected) to rail 3. In the example of fig. 1, the first terminals of

diodes

218 and 220 are anodes and the second terminals of

diodes

218 and 220 are cathodes. Node 206 is thus coupled to the anode of one diode and the cathode of the other diode.

In other words, each diode is coupled in parallel (preferably connected) with one of the

transistors

202 and 204. For example, the anode of diode 218 is coupled (preferably connected) to the source of transistor 202, and the cathode of diode 218 is coupled (preferably connected) to the drain of transistor 202. Similarly, the anode of diode 220 is coupled (preferably connected) to the source of transistor 204, and the cathode of diode 220 is coupled (preferably connected) to the drain of transistor 204. For example, the cathode of diode 218 is also coupled (preferably connected) to the substrate of transistor 202. The anode of diode 220 is also coupled (preferably connected) to the substrate of transistor 204, for example. Preferably,

diodes

218 and 220 are intrinsic diodes of

transistors

202 and 204, respectively.

The circuit 10 includes an input 102 and two

outputs

104 and 106. The input 102 receives a voltage VLX that is desired to be compared to a voltage range, and more specifically, to a first voltage threshold and a second voltage threshold. In the example of fig. 1, the first and second thresholds are the positive supply voltage Vbat and the reference voltage GND (preferably ground) of the device, respectively. The output 104 provides a signal POS (preferably binary) and the output 106 provides a signal NEG (preferably binary). When circuit 10 determines that the input voltage is greater than the first threshold value Vbat of the range, signal NEG takes a first value, e.g. a high value. If the input voltage is less than the first threshold value Vbat, the voltage NEG takes a second value, e.g. a low value. When circuit 10 determines that the input voltage is less than the second threshold of the range, signal POS takes a first value, e.g., a high value. If the input voltage is greater than the second threshold value, the voltage POS takes a second value, e.g., a low value.

Thus, if both signals POS and NEG have a low value, this means that the input voltage is between the first threshold and the second threshold. If the signal NEG has a high value and the signal POS has a low value, the input voltage has a value greater than a first threshold value. If the signal NEG has a low value and the signal POS has a high value, the input voltage has a value smaller than the second threshold value.

Circuit 10 includes two

transistors

108 and 110 coupled in series between rail 3 and rail 5. More specifically, one of the conductive terminals (source or drain) of transistor 108 is coupled (preferably connected) to node 112. The other conducting terminal (drain or source) of transistor 108 is coupled (preferably connected) to input node 102. One of the conductive terminals (source or drain) of transistor 110 is coupled (preferably connected) to node 102. The other conducting terminal (drain or source) of transistor 110 is coupled (preferably connected) to node 114.

Preferably, transistor 110 is a P-type field effect or PMOS transistor and transistor 108 is an N-type field effect or NMOS transistor. Preferably,

transistors

108 and 110 are coupled (preferably connected) to node 102 by their respective sources.

The transistor 108 is controlled by a voltage having a value substantially equal to (preferably equal to) the second voltage threshold, here the reference voltage GND. In other words, the control terminal or gate of transistor 108 is coupled to rail 5 to which voltage GND is applied. The transistor 110 is controlled by a voltage having a value substantially equal to (preferably equal to) the first voltage threshold, here the supply voltage Vbat. In other words, the control terminal or gate of transistor 110 is coupled to rail 3, which applies the voltage Vbat.

Node 112 is preferably coupled to rail 3 through a resistive element or resistor 116. Node 112 is also preferably coupled to output node 104 through a circuit or inverter 117 configured to invert the binary signal. Thus, when circuit 117 receives a low input value, it provides a high output voltage, and vice versa.

Node 114 is preferably coupled to rail 5 through a resistive element or resistor 118. Node 114 is also coupled to output node 106, preferably through two circuits or series connected

inverters

120 and 122 configured to invert the binary signal.

Thus, resistive element 116, transistor 108, transistor 110, and resistive element 118 are coupled in series in this order between track 3 and track 5.

The

circuits

117, 120 and 122 are able to ensure that the signals POS and NEG are binary signals with identifiable high and low values.

Fig. 2 shows a timing diagram illustrating the operation of the embodiment of fig. 1. More specifically, fig. 2 shows the behavior of the control signals GN, GP of the current Ic, the voltage VX, and the signals POS and NEG on the node 206 during the operating cycle of the circuit 20 of fig. 1 and during part (E) of the next cycle. The operation cycle includes, for example, four phases: a power storage phase (a), an intermediate phase (B), a power transfer phase (C), and a compensation phase (D) in an inductive element (not shown in fig. 1, having terminals coupled to node 102).

During power storage phase (a), transistor 202 is on and transistor 204 is off. In the embodiment of fig. 1, this corresponds to the control signal GN having a low value and the control signal GP having a low value. Thus, voltage VLX has a positive value of V1, less than the value of Vbat. Thus, during phase (a), the current Ic (not shown in fig. 1) through the inductive element increases.

The voltage VLX is smaller than the control voltage of the transistor 110, i.e., the supply voltage Vbat, and the gate-source voltage of the transistor 110 is positive. Thus, transistor 110 remains off during phase (a). Thus, the voltage on node 114 has a low value, e.g., substantially equal to the reference voltage GND. Thus, the signal NEG at the output of the

inverters

120 and 122 has a low value.

Similarly, the voltage VLX is greater than the control voltage of the transistor 108, i.e., the reference voltage GND, and the gate-source voltage of the transistor 108 is negative. Thus, transistor 108 remains off during phase (a). Thus, the voltage on node 112 has a high value, e.g., substantially equal to the voltage Vbat. The signal POS at the output of the inverter 117 therefore has a low value.

During phase (B),

transistors

204 and 202 are off. In the embodiment of fig. 1, this corresponds to the control signal GN having a low value and the control signal GP having a high value. Stage (B) is an intermediate stage that can ensure that

transistors

208 and 210 are not on at the same time. During phase (B), node 206 is no longer powered by track 3. And thus the current Ic decreases. Current Ic is positive and

transistors

202 and 204 are off. The current Ic thus passes through the diode 220. The voltage VLX takes a negative value of V3.

The voltage VLX is smaller than the control voltage of the transistor 110, i.e., the power supply voltage Vbat, and the gate-source voltage of the transistor 110 is positive. Thus, transistor 110 remains off during phase (B). Thus, the voltage on node 114 is low, e.g., substantially equal to the reference voltage GND. Thus, the signal NEG at the output of the

inverters

120 and 122 has a low value.

The voltage VLX is negative. In other words, the voltage VLX is smaller than the control voltage of the transistor 108, i.e., the reference voltage GND. The gate-source voltage of transistor 108 is therefore positive. Thus, transistor 108 is turned on during stage (B). Thus, the voltage on node 112 has a low value, e.g., substantially equal to voltage V3. The signal POS at the output of the inverter 117 therefore has a high value.

The signals POS and NEG thus indicate that the voltage VLX is less than the two thresholds Vbat and GND. More specifically, a low value of signal NEG indicates that voltage VLX is less than threshold Vbat or within a range of values GND and Vbat, or outside the range and less than threshold GND. A high value of signal POS indicates that voltage VLX is less than threshold GND and therefore outside the range between values GND and Vbat.

During phase (C), the power transfer phase, transistor 204 is on and transistor 202 is off. In the embodiment of fig. 1, this corresponds to the control signal GN having a high value and the control signal GP having a high value. The voltage VLX increases but remains negative. During phase (C), current Ic decreases and node 206 is no longer powered by rail 3.

The voltage VLX is smaller than the control voltage of the transistor 110, i.e., the supply voltage Vbat, and the gate-source voltage of the transistor 110 is positive. Thus, transistor 110 remains off during stage (C). Thus, the voltage on node 114 has a low value, e.g., substantially equal to the reference voltage GND. Thus, the signal NEG at the output of the

inverters

120 and 122 has a low value.

During stage (D), transistor 204 is off and transistor 202 is off. In the embodiment of fig. 1, this corresponds to the control signal GN having a low value and the control signal GP having a high value.

As in phase (B), current Ic is positive and

transistors

As in phase (B), the voltage VLX is less than the control voltage of the transistor 110, i.e., the supply voltage Vbat, and the gate-source voltage of the transistor 110 is positive. Thus, transistor 110 remains off during phase (B). Thus, the voltage on node 114 has a low value, e.g., substantially equal to the reference voltage GND. Thus, the signal NEG at the output of the

inverters

120 and 122 has a low value.

As in phase (B), the voltage VLX is negative. In other words, the voltage VLX is smaller than the control voltage of the transistor 108, i.e., the reference voltage GND. The gate-source voltage of transistor 108 is therefore positive. Thus, transistor 108 is turned on during stage (B). Thus, the voltage on node 112 has a low value, e.g., substantially equal to voltage V3. The signal POS at the output of the inverter 117 therefore has a high value.

During phase (D), the current Ic is continuously decreasing. Phase (D) ends when current Ic reaches a zero value.

For example, phase (D) is followed by phase (E), which for example corresponds to phase (a) of the next operating cycle or to a phase in the off state.

Fig. 3 shows a timing diagram illustrating the operation of the embodiment of fig. 1. More specifically, fig. 3 illustrates the operation of the control signals GN, GP of the current Ic, the voltage VLX, and the signals POS and NEG on the node 206 during an operating cycle of the circuit 20 of fig. 1. As shown in fig. 2, the operation cycle includes four phases: a power storage phase (a), an intermediate phase (B), a power transfer phase (C) and a compensation phase (D) in the inductive element.

Stages (a) and (B) are the same as stages (a) and (B) of fig. 2. They will not be described again.

During the power transfer phase (C), transistor 204 is on and transistor 202 is off. In the embodiment of fig. 1, this corresponds to the control signal GN having a high value and the control signal GP having a high value.

The voltage VLX increases during phase (C). At time tz of phase (C), voltage VLX reaches a zero value and then continues to increase. The current Ic decreases during phase (C). At time tz, current Ic reaches a value of zero. During phase (C), current Ic is positive before time tz and negative after time tz, and voltage VLX is positive before time tz and negative after time tz.

During phase (C), the voltage VLX is less than the first voltage threshold Vbat. Therefore, the signal NEG remains low. Further, the voltage VLX is less than the second voltage threshold GND before time tz and greater than the second threshold after time tz. Thus, during phase (C), the signal POS takes a high value before time tz and a low value after time tz.

Transistors

202 and 204 are off and current Ic is negative and diode 218 is active. Thus, voltage VLX becomes greater than voltage Vbat, e.g., substantially equal to voltage Vbat plus the threshold voltage of diode 218. Thus, the current Ic increases to zero. When the current reaches zero, phase (D) ends.

The voltage VLX is greater than the control voltage of the transistor 110, i.e., the supply voltage Vbat, and the signal NEG has a high value. In addition, the voltage VLX is greater than the control voltage of the transistor 108, i.e., the reference voltage GND, and the signal POS has a low value.

Stage (D) is followed by stage (E) in which the behavior of the device is similar to its behavior in stage (a). As a variant, stage (E) corresponds to the stage in the off state.

Fig. 4 schematically shows an embodiment of the DC/DC voltage converter. In the present example, the converter 1 is a DC/DC converter which converts a DC supply voltage into a DC output voltage.

The converter 1 is configured to deliver a DC output voltage Vout. The converter comprises an output node 2 on which a voltage Vout is available.

The converter 1 is powered by a DC supply voltage Vbat. The converter 1 is then connected between a first conducting rail or node 3 set to the voltage Vbat and a second conducting rail or node 5 set to the reference potential GND.

The converter 1 is configured to deliver the voltage Vout at a value equal to the set-point value. For this purpose, the converter 1 receives on the input node 7 a DC setpoint voltage Vref referenced to the potential GND, whose value represents the setpoint value of the voltage Vout, preferably equal to the setpoint value of the voltage Vout.

In this example, voltages Vout, Vbat, and Vref are positive.

In the present example, the converter 1 is of the buck type, i.e. the set-point value of the voltage Vout is smaller than the value of the voltage Vbat. In other words, the value of the voltage Vout is smaller than the value of the voltage Vbat.

The converter 1 comprises a first MOS ("metal oxide semiconductor") transistor 9, preferably a PMOS transistor (P-channel MOS transistor). As a variant, the transistor 9 may also be an NMOS transistor associated with the bootstrap system. The MOS transistor 9 is connected between the rail 3 and an internal node 11. In other words, a first conductive terminal of transistor 9 (e.g., its source) is connected to rail 3 and a second conductive terminal of transistor 9 (e.g., its drain) is connected to node 11.

The converter 1 further comprises a second MOS transistor 13, preferably an NMOS transistor (N-channel MOS transistor). Transistor 13 is connected between node 11 and rail 5. In other words, a first conductive terminal of transistor 13 (e.g., its source) is connected to rail 5, and a second conductive terminal of transistor 13 (e.g., its drain) is connected to node 11. As a variant, the NMOS transistor 13 may be replaced by a diode or a schottky diode.

Thus,

transistors

9 and 13 are connected in series between

rails

3 and 5 and to each other at the level of internal node 11.

The converter 1 comprises an inductive element or inductance 15. Inductor 15 is connected between node 11 and node 2.

The converter 1 comprises a control circuit 17. The circuit 17 is configured to implement or control the operating cycle of the converter 1 to regulate the voltage Vout to a value equal to the set-point value Vref.

For this purpose, the circuit 17 comprises:

a terminal 171 coupled (preferably connected) to node 7;

a terminal 172 coupled (preferably connected) to node 2;

a terminal 173 coupled (preferably connected) to the track 3;

a terminal 174 coupled (preferably connected) to the rail 5;

a terminal 175 coupled (preferably connected) to a control terminal or gate of the transistor 9; and

a terminal 176 coupled (preferably connected) to a control terminal or gate of the transistor 13.

The converter 1 comprises an output capacitor 16 connected between the node 2 and the rail 5. For example, the capacitance is in the range of 2.2 μ F to 20 μ F, or even greater. Such an output capacitor functions as a filter. In other words, the converter output capacitor is able to smooth the current present on node 2 and store the power supplied by the converter to node 2.

In operation, a load is connected between node 2 and rail 5 to be powered by voltage Vout. The load comprises for example an input capacitor between node 2 and rail 5.

In this example, the converter 1 is configured to operate with pulse frequency modulation (discontinuous conduction mode). Then, the circuit 17 is configured to start an operating cycle of the converter 1 when the value of the voltage Vout is smaller than the set-point value Vref and the two

transistors

9 and 13 are in the off-state. More specifically, at the beginning of each operating cycle, the circuit 17 is configured to control the setting of the transistor 9 to the on state, the transistor 13 remaining in the off state. Then, during a first time period TPon, which is constant for each operating cycle, when for example transistor 9 is kept in the conductive state by circuit 17, power is then stored in inductor 15 and capacitor 16, and current IL then flows through inductor 15. At the end of the time period TPon, the circuit 17 is configured to control setting the transistor 9 to the off-state and the transistor 13 to the on-state. The power is then fed back to the load connected at the output of the converter through the inductor 15 and the capacitor 16 for a second time period TNon, which is constant for each operating cycle, for example, when the circuit 17 keeps the transistor 13 in a conducting state, the current IL in the inductor decreasing. At the end of the time period TNon, the circuit 17 is configured to control the setting of the transistor 13 to the off state.

The time period TNon is determined such that the time for which the circuit 17 controls the transistor 13 to be set to the off-state corresponds to the time for which the current IL flowing through the inductance 15 becomes zero. However, in practice, as will be described in further detail in the remainder of the disclosure, this is not always true, which raises a problem.

Fig. 5 shows a timing diagram illustrating a desired operation example of the converter 1 in fig. 4.

Timing diagram a (at the top of fig. 5) shows the variation of the voltage Vout with time t, in volts V, and timing diagram B (at the bottom of fig. 5) shows the corresponding variation of the current IL through the inductor 15 with time t.

At time t0,

transistors

9 and 13 are in the off state, current IL is zero, and the value of voltage Vout is greater than its set point value, in this example the value of voltage Vref.

Between time t0 and a subsequent time t2, the voltage Vout decreases, for example due to the fact that the load connected to the converter 1 consumes current and discharges the output capacitor.

At time t1 between times t0 and t2, the voltage Vout becomes smaller than its setpoint value Vref. This is detected by the circuit 17 of the converter 1, which circuit 17 then controls the setting of the transistor 9 to the conducting state. Transistor 9 is turned on at time t 2.

Thus, from time t2, inductor 15 has a terminal connected to node 2 through transistor 9 and a terminal coupled to rail 3. The current IL flowing through the inductance 15 increases.

Thus, from time t2, current IL is provided to node 2 and capacitor 16 between node 2 and rail 5 charges. The voltage Vout increases and becomes greater than its setpoint value Vref.

At the next time t3, equal to t2+ TPon, circuit 17 controls setting transistor 13 to the on state and transistor 9 to the off state. At time t3, the current in the inductor has a maximum value ILP.

Thus, from time t3, inductor 15 has a terminal connected to node 2 via transistor 13 and a terminal coupled to rail 5. The current IL flowing through the inductance 15 decreases.

Although current IL decreases from time t3, if the current drawn by the load is less than current IL supplied to node 2, the capacitor between node 2 and rail 5 remains charged and voltage Vout remains increased.

At the next time t4, equal to t3+ TNon, circuit 17 controls setting transistor 13 to the off state. It is assumed here that the converter 1 is operating in the manner it should be, and then the current IL is zero at time t 4. However, in practice, this is not always true.

From time t4, current IL is zero and voltage Vout decreases, similar to what occurs at time t 0.

Although not shown herein, when the value of the potential Vout falls below its setpoint value Vref at a time after time t4, the circuit 17 implements a new operating cycle, as described with respect to successive times t2, t3 and t 4.

Fig. 6 shows a further timing diagram illustrating the operation of the converter 1 in fig. 4. More specifically, a timing chart a1 shows an ideal or theoretical example of the change in the current IL, a timing chart a2 shows the voltage Vout corresponding to the change in the current IL of the timing chart a1, a timing chart B1 shows an example of the actual change in the current IL, and a timing chart B2 shows the voltage Vout corresponding to the change in the current IL of the timing chart B1. These timing charts show an operation example in which the voltage Vout is smaller than the voltage Vref at the end of each operation period of the converter 1 in a plurality of consecutive operation periods. The current taken at the output node is considered to be a constant current Iout.

At time t30 (timing diagrams a1 and a2), the voltage Vout is less than the voltage Vref. The operating cycle starts with the transistor 9 switching to a conducting state. Therefore, the current IL increases until the next time t31 equals t30+ TPon.

At time t31, current IL reaches its maximum value ILP. Further, the

transistors

9 and 13 are switched to an off state and an on state, respectively. Therefore, the current decreases until the next time t32 equals t31+ TNon.

In this example of ideal operation, transistor 13 switches to the off state at time t32, and current IL becomes zero at time t 32.

At time t32, when voltage Vout is less than voltage Vref, transistor 9 switches to a conducting state, which marks the beginning of a new operating cycle. The current IL then increases until the next time t33 equals t32+ TPon.

At time t33, current IL reaches a value ILP. Further, the

transistors

9 and 13 are switched to an off state and an on state, respectively. Therefore, the current decreases until the next time t34 equals t33+ TNon.

In this example of ideal operation, transistor 13 switches to the off state at time t34, and current IL becomes zero at time t 34.

At time t34, when voltage Vout is less than voltage Vref, transistor 13 switches to a conducting state, which marks the beginning of a new operating cycle. The current IL increases until the next time t35 equals t34+ TPon.

At time t35, current IL reaches a value ILP. Further, the

transistors

9 and 13 are switched to an off state and an on state, respectively. Therefore, the current decreases until the next time t36 equals t35+ TNon.

In this example of ideal operation, transistor 13 switches to the off state at time t36, and current IL becomes zero at time t 36.

At time t36, voltage Vout is less than voltage Vref, and a new cycle of operation begins.

In the example of theoretical operation shown in the timing charts a1 and a2, at the end of each operation period, switching of the transistor 13 in the off state occurs at the time when the current IL becomes zero. Thus, when an operating cycle is followed by a new operating cycle, the current IL increases from a zero value during this new operating cycle.

Timing diagrams B1 and B2 show corresponding examples of the true operation of the converter 1. In this example of actual operation, consider the actual case where transistor 13 does not immediately switch to the off state at the end of the time period TNon that has elapsed since its last switch to the on state.

At time t40 (B1 of fig. 6 and B2 of fig. 6) when the voltage Vout is smaller than the voltage Vref, the operation period starts from switching to the on state of the transistor 9. Therefore, the current IL increases until the next time t41 equals t40+ TPon.

At time t41, current IL reaches its maximum value ILP. Further, the

transistors

9 and 13 are switched to an off state and an on state, respectively. Therefore, the current decreases until the next time t42 equals t41+ TNon. The current becomes zero at time t 42. However, the switching of the transistor 13 to the off state is effective only at time t43 after time t 42. Thus, between times t42 and t43, current IL is negative and decreases. In other words, before time t42, current flows in inductor 15 from node 11 to node 2, becomes zero at time t42, and flows through inductor 15 after time t42 from node 2 to node 11.

At time t43, the voltage Vout is less than the voltage Vref, and transistor 9 switches to a conducting state at time t43, which marks the beginning of a new operating cycle. The current IL then increases until the next time t44 equals t43+ TPon.

At time t44, since the time period TPon is constant in each cycle, the current IL reaches a value ILp' smaller than the maximum value ILp. Further, the

transistors

9 and 13 are switched to an off state and an on state, respectively. Therefore, the current IL decreases until the next time t46 equals t44+ TNon, the current IL becoming zero at a time t45 between times t44 and t 46. Further, the switching to the off state of the transistor 13 is effective only at time t47 after time t 46. Therefore, between times t45 and t47, current IL is negative and decreases to a value lower (or higher in absolute value) than the value reached at time t 43.

At time t47, the voltage Vout is less than the voltage Vref, and transistor 9 switches to the conducting state at time t47, which marks the beginning of a new operating cycle. The current IL then increases until the next time t48 equals t47+ TPon.

At time t48, current IL reaches a value ILp ", which is less than a value ILp'. Further, the

transistors

9 and 13 are switched to an off state and an on state, respectively. Therefore, the current IL decreases until the next time t50 equals t48+ TNon, the current IL becoming zero at a time t49 between times t48 and t 50. Further, the switching to the off state of the transistor 13 is effective only at time t51 after time t 50. Therefore, between times t49 and t51, current IL is negative and decreases to a value lower (or higher in absolute value) than the value reached at time t 47.

Since in each operating cycle shown in the timing diagrams B1 and B2 the maximum value reached by the current IL (times t41, t44 and t48) is lower and lower, the converter 1 does not supply enough power to the node 2 to regulate the voltage Vout at its value Vref, which causes problems, for example, lower and lower. Furthermore, in each operating cycle shown in the timing diagrams B1 and B2, the current IL (times t43, t47 and t51) reaches increasingly lower negative values (or increasingly higher in absolute value), whereby the converter 1 samples more and more power from the node 2, which is undesirable. In fact, the value of the current supplied to the load, in particular the value of the current peak, decreases from cycle to cycle, which has a negative effect on the load power supply. Furthermore, although theoretically the maximum value of current IL may decrease indefinitely, in practice, in some cases transistor 13 may be damaged or destroyed by the negative value of current IL before transistor 13 is unable to conduct between its conducting terminals.

A practical example of an operation in which switching to the off state of the transistor 13 occurs after the current IL becomes zero has been described in conjunction with the timing charts B1 and B2 of fig. 6.

In another practical example of operation, not shown, in each operating period of a number of successive periods effected immediately after the other periods, transistor 13 is switched to the off state, while current IL is not zero and is still positive. In this case, in each operating cycle, the current IL increases from an increasingly higher value, whereby the current IL reaches an increasingly higher maximum value, and the operating cycle ends with an increasingly higher positive non-zero value of the current IL. This operation is less disturbing than the operation described in relation to the timing diagrams B1 and B2, because after a number of operating cycles, the voltage Vout will resume its setpoint value Vref. Therefore, the next operating cycle will not be realized immediately, which will leave time for the current IL to become zero.

Both of these cases, the cases described with respect to the timing diagrams B1 and B2 of fig. 3 and the other practical cases described above, are generally caused, at least in part, by component-level defects, particularly of the comparator, particularly by the comparator's on-time (response or propagation time) and offset in comparator level. In other words, the comparator does not compare the input signals S1 and S2, but compares the signals S1 and S2+ a, a being the offset of the comparator.

Fig. 7 shows an example of the application of the embodiment of the circuit 10 of fig. 1 in a DC/DC voltage converter. The converter of fig. 7 comprises the elements described in relation to fig. 4, the circuit 17 being in more detail.

The converter comprises

transistors

9 and 13, an inductance 15 and a capacitor 16 as described in relation to fig. 4.

Transistors

9 and 13 are coupled (preferably connected in series), similar to

transistors

202 and 204 of fig. 1, between rail 3, to which a supply voltage Vbat is applied, and rail 5, to which a reference voltage (e.g., ground GND) is applied. In other words, one conducting terminal (source or drain) of the transistor 9 is coupled (preferably connected) to the rail 3, while the other conducting terminal (drain or source) is coupled (preferably connected) to the central node 11. One conducting terminal (source or drain) of transistor 13 is coupled (preferably connected) to node 11 and the other conducting terminal (drain or source) is coupled (preferably connected) to rail 5.

Preferably, transistor 9 is a P-type field effect or PMOS transistor and transistor 13 is an N-type field effect or NMOS transistor.

Each of the

transistors

9 and 13 includes an intrinsic diode not shown.

Intrinsic diodes (not shown), similar to

diodes

218 and 220 of fig. 1, are coupled in series between track 3 and track 5. More specifically, a first terminal (anode or cathode) of the intrinsic diode of transistor 13 is coupled (preferably connected) to rail 5, and a second terminal (cathode or anode) of the diode is coupled (preferably connected) to node 11. A first terminal (anode or cathode) of the intrinsic diode of transistor 9 is coupled (preferably connected) to node 11 and a second terminal (cathode or anode) of the diode is coupled (preferably connected) to rail 3. In the example of fig. 1, the first terminal of the intrinsic diode is the anode and the second terminal of the intrinsic diode is the cathode. The node 11 is thus coupled to the anode of one of the diodes and the cathode of the other diode.

The converter comprises a circuit 180 for generating control signals GP, GN, a circuit 182 for transmitting a signal PWN determining the duration TPon and TNon, a circuit 184 configured to determine the start time of each operating cycle and a circuit 186 generating a variable voltage.

Circuit 180 includes a first output 180a and a second output 180b that are coupled (preferably connected) to

outputs

175 and 176, respectively, of circuit 17. The circuit 180 generates a signal GP for controlling the transistor 9 at a first output 180a and a signal GN for controlling the transistor 13 at a second output 180 b.

The circuit 180 includes an input 180c coupled (preferably connected) to an output of the circuit 182. Circuit 182 provides on this output a signal PWN that determines the duration TPon and TNon and thus determines the duration of the power storage phase and the power delivery phase.

The circuit 182 includes two inputs 182a and 182b that are coupled (preferably connected) to the

inputs

171 and 172 of the circuit 17, respectively. Thus, circuit 182 generates signal PWN as a function of the values of voltage Vout received on input 172 and set point voltage Vref received on input 171, and more specifically as a function of the difference between these values. Thus, if the voltage Vout is less than the voltage Vref, the duration TPon increases and the duration TNon decreases. If the voltage Vout is greater than the voltage Vref, the duration TNon increases and the duration TPon decreases.

The converter includes circuitry 184 configured to determine a start time of each operating cycle. More specifically, circuit 184 is configured to determine when current Ic reaches a zero value, i.e., the end of the operating cycle. In practice, this corresponds to the detection of a zero crossing of the voltage VLX. Circuit 184 includes an output coupled (preferably connected) to circuit 180 to convey this information by signal S taking a high value when current Ic reaches a zero value.

The circuit 184 is, for example, a zero-crossing detection circuit (ZCD). The circuit 184 includes a comparator.

The comparator of circuit 184 suffers from the drawbacks discussed in relation to fig. 6B. More specifically, propagation delays and offsets of the comparator input voltages cause comparison defects, as described with respect to fig. 6B.

Circuit 184 is coupled at its input to rail 5, passing a reference voltage GND, and to node 11, passing a voltage VLX.

Circuit 184 is coupled to track 5 through circuit 186, circuit 186 being configured to modify the value compared to voltage VLX to compensate for propagation delays and offsets of the comparators of circuit 184. For example, circuit 186 is a variable voltage source. Thus, the output voltage of circuit 186, i.e., the input voltage of circuit 184 compared to voltage VLX, may be different than zero. The circuit 184 does not compare the voltage VLX with a value of zero, but rather compares the voltage VLX with the output value of the circuit 186. For example, the output value of circuit 186 is modified at each operating cycle.

To determine whether the circuit 186 should modify its output value, the circuit 186 receives the signal d. Signal d is generated by a circuit combination comprising circuit 10 and circuit 190. Thus, circuit 10 is coupled (preferably connected) at its input to node 11. The circuit 10 includes two outputs with signals POS and NEG generated thereon.

Circuit 190 is coupled (preferably connected) at its input to the output of circuit 10 and thus receives POS and NEG as input signals. Circuit 190 determines the sign of current IC during stage (D) and generates a modified signal D that controls the value of the output of circuit 186. Therefore, the voltage modification of circuit 186 is dependent on the sign of current Ic during phase (D), and preferably independent of the sign of the current during the other phases.

Fig. 8 shows a timing diagram illustrating an example of the operation of the embodiment of fig. 7. Fig. 8 shows two operating cycles of the converter, separated by a stop phase.

During the first stop phase (E), the

transistors

9 and 13 are switched off. This corresponds to signals GN and GP having low and high values, respectively. During this phase, current Ic is zero and voltage VLX has a value substantially equal to V2, and is positive and less than voltage Vbat. Furthermore, the signal S, preferably binary, has for example a low value.

At time t60, phase (A) of the operating cycle begins. Thus, time t60 corresponds to the end of phase (E) and the beginning of phase (a).

At time t60, transistor 9 is turned on. In other words, the value of the control signal GP takes another binary value, here a low value. The node 11 is thus powered by the track 3. Thus, the voltage at node V1, slightly less than Vbat, but greater than V2, increases the current Ic.

At time t62, phase (A) ends and phase (B) begins. The duration of phase (a) corresponds to the duration TPon.

As in the case of stage (B) of fig. 2 and 3, the transistor 9 is turned off and the transistor 13 is turned off. In the embodiment of fig. 7, this corresponds to the control signal GN having a low value and the control signal GP having a high value. Stage (B) is an intermediate stage that can ensure that

transistors

9 and 13 are not on at the same time. During phase (B), the node 11 is no longer powered by the track 3. And thus the current Ic decreases.

Current Ic is positive and

transistors

During phase (B), the signal POS takes a high value, as described in fig. 2 and 3. However, during phase (B), circuitry 190 does not consider signals POS and NEG.

At time t62, phase (B) ends and phase (C) begins. Transistor 13 is on and transistor 9 is off. In the embodiment of fig. 7, this corresponds to the control signal GN having a high value and the control signal GP having a high value. Voltage VLX increases and current Ic decreases through inductor 15 and node 11 is no longer powered by rail 3.

At time tz1 of phase (C), i.e., after duration TNon, current Ic and voltage VLX reach a value of zero. However, the circuit 184 has a propagation delay of value D. Thus, the output S of circuit 184 only takes a high value at time t66 spaced from tz1 by a time period D, indicating a zero crossing of current Ic. Between time tz1 and time t66, current Ic becomes negative.

At time t66, circuit 180 is informed by the rising edge of signal S that current Ic has reached the value zero. Thus, stage (C) ends and stage (D) begins.

During phase (D),

transistors

9 and 13 are off. In the embodiment of fig. 7, this corresponds to the control signal GN having a low value and the control signal GP having a high value.

Transistors

9 and 13 are off and current Ic is negative and the intrinsic diode of transistor 9 becomes active. Thus, the voltage VLX becomes greater than the voltage Vbat, e.g., substantially equal to the voltage Vbat plus the threshold voltage of the diode. Therefore, current Ic increases to zero at time t 68. When the current reaches zero, the diode is no longer conducting and stage (D) ends.

At time t68, a phase (E) such as previously described begins. The voltage VLX recovers the value V2.

Phase (E) is followed by a second operating cycle that includes phase (a) between time t70 and time t72, phase (B) between time t72 and time t74, phase (C) between time t74 and time t76, and phase (D) between time t76 and time t 78.

The second operating cycle differs from the first operating cycle in that prior to phase (C), e.g., during phase (a), circuit 190 provides signal d to circuit 186 to modify the value of the output signal of circuit 186. In the case of the second operation period, the value of the output of the circuit 186 is modified to be equal to the value V4 that is smaller than the value of the reference voltage (here, ground).

Thus, the circuit 184 compares the voltage VLX with the value V4. At time tz2, value V4 is reached here earlier than zero. Stage (C) ends time period D after time tz 2. The negative value reached by current Ic at the end of phase (C) is closer to zero than the value reached by current Ic at the end of the preceding phase (C).

An advantage of the described embodiment is that the voltage can be compared with two thresholds by a simple circuit.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

Finally, the actual implementation of the described embodiments and variants is within the abilities of a person skilled in the art based on the functional indications given above.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.

Claims

1. An electronic device, comprising:

a first circuit including a first transistor and a second transistor coupled in series between a node to which a power supply voltage is applied and a node to which a reference voltage is applied, the first transistor and the second transistor being coupled to each other through a first node; and

a second circuit configured to compare a first voltage on the first node to a first voltage threshold and a second voltage threshold.

2. The apparatus of claim 1, wherein the second circuit comprises a third transistor and a fourth transistor coupled in series between a second node and a third node, the third transistor and the fourth transistor coupled to each other through a fourth node, the fourth node coupled to the first node.

3. The apparatus of claim 2, wherein the second node is coupled to a node to which the supply voltage is applied through a first resistive element, and the third node is coupled to the node to which the reference voltage is applied through a second resistive element.

4. The apparatus of claim 2, wherein a control terminal of the third transistor is coupled to a node to which the second voltage threshold is applied and a control terminal of the fourth transistor is coupled to a node to which the first voltage threshold is applied.

5. The apparatus of claim 1, wherein the first voltage threshold is the supply voltage and the second voltage threshold is the reference voltage.

6. The apparatus of claim 3, wherein the second circuit comprises:

a first output node on which a first signal is provided, the first signal taking a first value when the first voltage is greater than the first voltage threshold and taking a second value when the first voltage is less than the first voltage threshold; and

a second output node on which a second signal is provided, the second signal taking a third value when the first voltage is less than the second voltage threshold and taking a fourth value when the first voltage is greater than the second voltage threshold.

7. The apparatus of claim 6, wherein the first output node is coupled to the second node and the second output node is coupled to the third node.

8. The apparatus of claim 6, wherein the first output node is coupled to the second node through two inverting circuits and the second output node is coupled to the third node through an inverting circuit.

9. The apparatus of claim 1, wherein the first transistor is connected in parallel with a first diode, the second transistor is connected in parallel with a second diode, an anode of the first diode and a cathode of the second diode are connected to the first node.

10. The apparatus of claim 6, wherein the apparatus is a switched mode power supply.

11. The apparatus of claim 10, wherein the apparatus comprises a third circuit configured to compare the first voltage to a second voltage, the second voltage being variable and dependent on signals on the first and second output nodes.

12. The apparatus of claim 10, wherein the apparatus comprises a fourth circuit configured to control the first transistor and the second transistor in such a way that each operating cycle comprises successively:

a first phase during which the first transistor is turned on and the second transistor is turned off;

a second phase during which the first and second transistors are off;

a third phase during which the first transistor is off and the second transistor is on; and

a fourth stage during which the first transistor and the second transistor are turned off.

13. The apparatus of claim 12, wherein:

the apparatus further comprises a third circuit configured to compare the first voltage to a second voltage, the second voltage being variable and dependent on signals on the first and second output nodes; and

during the fourth phase, the second voltage varies in dependence on the signals on the first and second output nodes.

14. A method of controlling an electronic device, the electronic device comprising a first circuit comprising a first transistor and a second transistor, the first and second transistors coupled in series between a node to which a supply voltage is applied and a node to which a reference voltage is applied, the first and second transistors coupled to each other through a first node, the method comprising:

in each operation period, turning on and off each of the first transistor and the second transistor according to a predetermined pattern; and

comparing, by a second circuit, a first voltage on the first node to a first voltage threshold and a second voltage threshold.

15. The method of claim 14, wherein the comparing is performed by third and fourth transistors coupled to the first node and coupled in series between second and third nodes.

16. The method of claim 15, further comprising:

applying the second voltage threshold to a control terminal of the third transistor; and

applying the first voltage threshold to a control terminal of the fourth transistor.

17. The method of claim 14, wherein the first voltage threshold is the supply voltage and the second voltage threshold is the reference voltage.

18. The method of claim 15, further comprising:

a first signal of a first output node of the second circuit takes a first value when the first voltage is greater than the first voltage threshold and a second value when the first voltage is less than the first voltage threshold; and

a second signal of a second output node of the second circuit takes a third value when the first voltage is less than the second voltage threshold and a fourth value when the first voltage is greater than the second voltage threshold.

19. The method of claim 18, further comprising: comparing, by a third circuit, the first voltage to a second voltage, the second voltage being variable and dependent on signals on the first output node and the second output node.

20. The method of claim 18, further comprising: controlling the first transistor and the second transistor by a fourth circuit in such a manner that each operation cycle successively includes:

a second phase during which the first and second transistors are off;

21. The method of claim 20, further comprising: comparing, by a third circuit, the first voltage with a second voltage, the second voltage being variable and dependent on signals on the first and second output nodes, the second voltage varying during the fourth phase dependent on signals on the first and second output nodes.