CN114070035B

CN114070035B - Power supply device and medical equipment

Info

Publication number: CN114070035B
Application number: CN202111339821.4A
Authority: CN
Inventors: 王海科; 王洪涛; 秦晓华; 杨延嗣
Original assignee: Shanghai United Imaging Healthcare Co Ltd
Current assignee: Shanghai United Imaging Healthcare Co Ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2023-12-26
Anticipated expiration: 2041-11-12
Also published as: CN114070035A

Abstract

The embodiment of the application discloses a power supply device. The power supply device includes: the power supply circuit is connected with the processed electric energy input end and provides a first power supply for the processing unit; the positive voltage output end of the processing unit provides a positive load power supply, and the negative voltage output end of the processing unit provides a negative load power supply; wherein the switching frequency of the processing unit is outside the effective frequency range of the load. According to the power supply device, the first power supply is converted into positive and negative high-voltage power supplies through the processing unit, and then the switching frequency of the processing unit is controlled, so that the EMI of the power supply device to a load is reduced.

Description

Power supply device and medical equipment

Technical Field

The present disclosure relates to the field of power supply, and in particular, to a high-voltage power supply device and a medical apparatus.

Background

In the medical imaging field, the work of some electronic devices requires a power supply device to provide positive and negative high voltage power. For example, ultrasound devices typically require positive and negative high voltage power supplies to generate pulses for subsequent detection with the pulses.

However, in the prior art, the signal processed when the power supply device provides the high-voltage power supply and the output electric energy often cause electromagnetic interference (electromagnetic interference, EMI) to the load, which affects the working quality of the load. For example, the detector easily collects signals output by the power supply device in the detection process, and the detection accuracy is affected.

Therefore, it is necessary to provide a power supply device that outputs positive and negative high-voltage power sources and has a small EMI.

Disclosure of Invention

The purpose of this specification is to provide a power supply unit and medical equipment to solve following technical problem: (1) The positive and negative power supplies (such as voltage and current of the power supply) are unstable. (2) The signals (such as fundamental wave and second harmonic wave) related to the power supply device cause electromagnetic interference to the load, and the working quality of the load is affected.

To achieve the above object, one of the embodiments of the present specification provides a power supply device. The power supply device includes: the power supply circuit is connected with the electric energy input end of the processing unit and provides a first power supply for the processing unit. The positive voltage output end of the processing unit provides a positive load power supply, and the negative voltage output end of the processing unit provides a negative load power supply. Wherein the switching frequency of the processing unit is outside the effective frequency range of the load.

In some embodiments, the processing unit includes a resonant circuit, and the switching frequency of the processing unit includes a resonant frequency of the resonant circuit that is outside an effective frequency range of the load and an n-harmonic range of the effective frequency range, the n-harmonic of the resonant frequency being outside the effective frequency range and the n-harmonic range of the effective frequency range.

In some embodiments, the resonant circuit includes a resonant capacitor bank including one or more resonant capacitors and a resonant inductor, the resonant capacitor bank being in series with the resonant inductor.

In some embodiments, the resonant capacitor group includes a first resonant capacitor subset and a second resonant capacitor subset, one end of the first resonant capacitor subset is connected to one end of the second resonant capacitor subset, the other end of the first resonant capacitor subset is used for receiving the bias voltage, and the other end of the second resonant capacitor subset is grounded.

In some embodiments, the processing unit further includes a rectifying and filtering circuit, an input end of the rectifying and filtering circuit is connected with an output end of the resonant circuit, the rectifying and filtering circuit is symmetrically arranged with the resonant circuit as a center, a first output end of the rectifying and filtering circuit provides a positive load power supply, and a second output end of the rectifying and filtering circuit provides a negative load power supply.

In some embodiments, the resonant circuit further comprises a switching element and a driver, the power input of the driver being connected to the power supply circuit, the driver being arranged to receive the drive signal and to control the switching element, the switching element being connected to the power supply circuit, the switching element being arranged to receive the first power supply. The difference between the frequency of the driving signal and the resonant frequency is within a preset range.

In some embodiments, the power supply device further comprises a first feedback circuit. The first feedback circuit is used for receiving the positive load power supply, the negative load power supply and the reference voltage and outputting the positive load power supply, the negative load power supply and the reference voltage to the processor so that the processor can send a first enabling signal to the processing unit.

In some embodiments, the power supply device further comprises a second feedback circuit comprising a first comparator and a second comparator, wherein the first comparator outputs a first comparison result according to the positive load power supply and the reference voltage, and the second comparator outputs a second comparison result according to the negative load power supply and the reference voltage; the second feedback circuit sends a second enabling signal and a third enabling signal to the processing unit according to the first comparison result and the second comparison result.

In some embodiments, the power supply device further comprises a hysteretic resistor disposed between the positive input of the second comparator and the output of the second comparator.

One of the embodiments of the present specification provides a medical device including: the detector and the power supply device provide positive load power supply and negative load power supply for the detector.

In summary, the possible beneficial effects of the embodiments of the present application include, but are not limited to: (1) The first power supply is converted into a positive load power supply and a negative load power supply through the processing unit, so that positive and negative power supplies can be simultaneously provided; (2) By setting the resonance frequency of the resonance circuit in the processing unit outside the effective frequency range of the load, the signal processed by the power supply device during working and the output electric energy are difficult to influence the normal working of the load in the effective frequency range, so that the EMI of the power supply device to the load is reduced; (3) The resonant circuit is adopted for electric energy conversion, so that the current of the positive load power supply and the current of the negative load power supply can be stable; (4) The electric energy output by the resonant circuit is respectively processed by adopting the same rectifying and filtering mode through the symmetrical structure of the rectifying and filtering circuit, so that the symmetry of a positive load power supply and a negative load power supply is improved, and the generation of second harmonic wave to cause EMI to the load is avoided; (5) The stability of the load power supply is effectively improved through the multi-feedback control method of the first feedback circuit and the second feedback circuit.

Drawings

The present specification will be further elucidated by way of example embodiments, which will be described in detail by means of the accompanying drawings. The embodiments are not limiting, in which like numerals represent like structures, wherein:

fig. 1 is a schematic view of a power supply device according to some embodiments of the present disclosure;

FIG. 2 is a power supply topology shown in accordance with some embodiments of the present description;

fig. 3A and 3B are schematic circuit configurations of a power supply circuit according to some embodiments of the present specification;

FIG. 4 is a schematic circuit diagram of a processing unit according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of frequency versus current according to some embodiments of the present description;

FIG. 6 is a simplified schematic diagram of a resonant circuit shown in accordance with some embodiments of the present description;

FIG. 7 is a schematic diagram of a processing unit according to some embodiments of the present disclosure;

fig. 8 is a schematic diagram of a driving circuit according to some embodiments of the present specification;

fig. 9 is a schematic circuit configuration diagram of a driving circuit shown according to some embodiments of the present specification;

FIG. 10 is a schematic diagram of a switching circuit shown in accordance with some embodiments of the present disclosure;

FIG. 11 is a schematic diagram of a feedback circuit shown in accordance with some embodiments of the present description;

fig. 12A and 12B are schematic diagrams of structures of voltage sampling circuits according to some embodiments of the present disclosure;

FIG. 13 is a schematic diagram of a power monitoring module according to some embodiments of the present disclosure;

FIGS. 14A and 14B are schematic circuit diagrams of comparison circuits according to some embodiments of the present disclosure;

FIG. 15 is a schematic diagram of a reference voltage generation scheme according to some embodiments of the present disclosure;

FIG. 16 is a schematic circuit diagram of a reference voltage circuit according to some embodiments of the present disclosure;

fig. 17 is a schematic diagram of a medical device according to some embodiments of the present disclosure.

100, a power supply device; 110. a power supply circuit; 120. a processing unit; u1, a driver; an MCU and a processor; u5, a first comparator; u6, a second comparator; r10, hysteresis resistance; 10. a medical device; 200. a detector.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is apparent that the drawings in the following description are only some examples or embodiments of the present specification, and it is possible for those of ordinary skill in the art to apply the present specification to other similar situations according to the drawings without inventive effort. Unless otherwise apparent from the context of the language or otherwise specified, like reference numerals in the figures refer to like structures or operations.

It will be appreciated that "system," "apparatus," "unit" and/or "module" as used herein is one method for distinguishing between different components, elements, parts, portions or assemblies at different levels. However, if other words can achieve the same purpose, the words can be replaced by other expressions.

As used in this specification and the claims, the terms "a," "an," "the," and/or "the" are not specific to a singular, but may include a plurality, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus.

A flowchart is used in this specification to describe the operations performed by the system according to embodiments of the present specification. It should be appreciated that the preceding or following operations are not necessarily performed in order precisely. Rather, the steps may be processed in reverse order or simultaneously. Also, other operations may be added to or removed from these processes.

The power supply device of one or more embodiments of the present disclosure may output positive and negative high voltages, so as to be applied to various service scenarios requiring positive and negative high voltage power, for example, production scenarios where signals such as pulses and lasers are generated by using positive and negative high voltage power, and for example, detection scenarios where signals, particles and the like are collected by using positive and negative high voltage power. In some embodiments, the power circuit may provide direct current to the power supply device or alternating current to the power supply device, and the input to the power supply device may be selected based on the type of processing unit in the power supply device.

In some embodiments, the power supply device may include a power circuit and a processing unit that may boost power provided by the power circuit to provide high voltage power to the load. However, the signal processed by the power supply device during operation and the output electric energy easily affect the signal related to the load during operation, thereby causing electromagnetic interference and reducing the working quality of the load. For example, the signal driving the power supply device and the harmonic wave in the power supply provided by the power supply device easily cause electromagnetic interference to the ultrasonic equipment by power supply, and influence the quality of the signal generated by the ultrasonic equipment.

Some embodiments of the present disclosure provide a power supply device including a power circuit and a processing unit. The power supply circuit provides a first power supply for the processing unit, and the processing unit converts the first power supply into a positive load power supply and a negative load power supply. Wherein the switching frequency of the processing unit is outside the effective frequency range [ a, b ] of the load, which is the frequency range in which most of the signals involved in operation of the load are located. Therefore, the processing unit of the power supply device can provide positive and negative high-voltage power supplies, and the switching frequency of the processing unit is controlled, so that signals processed by the power supply device during working and the provided positive and negative load power supplies are difficult to influence the normal working of the load in an effective frequency range, the EMI of the power supply device to the load is reduced, and the working quality of the load is improved.

Fig. 1 is a schematic structural view of a power supply device according to some embodiments of the present specification. As shown in fig. 1, the power supply apparatus 100 may include a power supply circuit 110 and a processing unit 120.

The power circuit 110 is connected to the power input terminal of the processing unit 120, and is configured to provide a first power supply to the processing unit 120. Specifically, the first power supply is configured to provide the processing unit 120 and finally output the converted power to supply power to the load. In some embodiments, the first power supply is a dc power supply, and may also be an ac power supply. In some embodiments, the power circuit 110 may also include a filtering circuit for filtering interference on the power supply bus.

In some embodiments, the power circuit 110 may also need to power active electronic devices in the processing unit 120, and since these active electronic devices operate most efficiently at a particular voltage, the power circuit 110 may also include a voltage converter to convert the power supply voltage provided to the active electronic devices to a desired voltage, thereby improving the operating efficiency. As shown in the power supply topology of fig. 2, the bus voltage of the power supply circuit 110 is supplied to the resonance circuit of the processing unit 120 through the filter circuit on the one hand, and to the IC device in the processing unit 120 through the voltage converter on the other hand. The specific implementation of the power circuit 110 can be referred to in the related description of fig. 3A and 3B, and will not be described herein.

The processing unit 120 is configured to convert the first power supply provided by the power supply circuit 110 into a positive load power supply and the negative load power supply. In some embodiments, the processing unit 120 includes a positive voltage output for providing a positive load power supply to a load and a negative voltage output for providing a negative load power supply to the load.

In some embodiments, the processing unit 120 may include a resonant circuit and a rectifying-filtering circuit, and the switching frequency of the processing unit 120 may include a resonant frequency f of the resonant circuit. The resonant circuit is used for adjusting the resonant frequency f and outputting a resonant signal, and the rectifying and filtering circuit is used for rectifying and filtering the resonant signal so as to output a positive load power supply and the negative load power supply. In some embodiments, an input of the resonant circuit is connected to the power circuit 110 for receiving a first power supply, and an output of the resonant circuit is connected to an input of the rectifying and filtering circuit for outputting a resonant signal. In some embodiments, the rectifying and filtering circuit is symmetrically arranged with the resonant circuit as a center, so that the symmetry degree of the positive load power supply and the negative load power supply output by the rectifying and filtering circuit is within a preset symmetry range. The specific implementation of the resonant circuit and the rectifying and filtering circuit can be referred to in the relevant description of fig. 4-6, and will not be repeated here.

In some embodiments, the processing unit 120 may further include a boost circuit, where an input terminal of the boost circuit is connected to an output terminal of the power circuit 110. The voltage output by the boost circuit is higher than the voltage of the first power supply.

The boost circuit may be a circuit that boosts a voltage. In some embodiments, the boost circuit may boost the voltage of the first power supply to output high voltage power. In some embodiments, the boost circuit may be a Sepic, LC resonant, flyback, etc. circuit, and the type of boost circuit is not specifically limited in this application.

In some embodiments, the switching frequency of the processing unit 120 may further include a resonant frequency f of the boost circuit, the resonant frequency f of the boost circuit being outside an effective frequency range of the load, and the resonant frequency f being outside an n-th harmonic range of the effective frequency range. In some embodiments, the n-th harmonic of the resonant frequency f is outside the effective frequency range of the load, and the n-th harmonic of the resonant frequency f is outside the n-th harmonic range of the effective frequency range.

In some embodiments, the switching frequency may include the frequency at which components in the processing unit 120 turn on and off as well as the frequency at which resonance occurs. In some embodiments, the resonant frequency may be the frequency at which the boost circuit resonates, an inherent characteristic of the circuit. When the resonance frequency f of the booster circuit is controlled to be out of the effective frequency range [ a, b ] of the load, the signal processed by the power supply device 100 in operation and the output electric energy hardly affect the normal operation of the load in the effective frequency range, thereby reducing the EMI of the power supply device 100 to the load. For specific implementation of the resonant frequency and the effective frequency range, reference may be made to the following description of the resonant circuit, which is not repeated here.

In some embodiments, the power supply apparatus 100 may further include a driving circuit. The driving circuit is connected to the processor and the processing unit 120, and is configured to output a driving signal to the processing unit 120 according to an instruction transmitted by the processor, so as to control the output of the processing unit 120. In some embodiments, the driving circuit may be a PWM (Pulse Width Modulation) driving circuit for outputting a pulse width modulated signal.

In some embodiments, the power supply apparatus 100 may further include a processor. The processor may be an integrated circuit that performs the processing services. By way of example, the processor may be a combination of one or more of a single-chip microcomputer, an advanced reduced instruction set processor (Advanced RISC Machines, ARM), a programmable logic device (Complex Programmable logic device, CPLD), a field programmable gate array (Field Programmable Gate Array, FPGA), and the like. In some embodiments, the processor may be an internal processor of the power supply apparatus 100, or may be an external processor of the power supply apparatus 100, for remotely controlling the power supply apparatus 100. It should be noted that the processor is a different circuit device from the processing unit 120, the processing unit 120 is configured to convert the first power supply into a positive load power supply and the negative load power supply, and the processor is configured to issue an instruction to the processing unit 120, so as to control the output of the processing unit 120.

In some embodiments, the load is an electronic device that consumes electrical power, and in particular, requires a stable positive and negative high voltage electrical power supply. In some embodiments, the load may be an output device that generates a pulse, laser, etc. signal using positive and negative high voltage electrical energy. For example, the load may be an ultrasonic system element, such as an ultrasonic probe, an ultrasonic diagnostic device, etc., and because the ultrasonic signal is small and is easily interfered by other signals, the quality requirement on the high-voltage power supply is high, and a good EMI environment is more needed. In some embodiments, the load may be a detection device that utilizes positive and negative high voltage electrical energy to acquire signals, particles, e.g., a spectrum detector, a radiation detector, a sound acquisition system, etc.

Fig. 3A and 3B are schematic circuit configurations of a power supply circuit according to some embodiments of the present specification.

In some embodiments, the power supply circuit may include a first power supply circuit and a second power supply circuit. The first power supply circuit is configured to provide the first power supply to pass through the processing unit 120 and finally output the converted positive load power supply and negative load power supply to supply power to the load. The second power supply circuit is configured to provide a power supply voltage to active electronic devices in the processing unit 120, and in particular, to provide a power supply voltage to the driver U1 of the processing unit 120.

As shown in fig. 3A, the first power supply circuit is configured to provide a first power supply to the processing unit 120. In some embodiments, the first power supply circuit includes a first energy source for providing a first power source, one end of the first energy source is connected in series to a first end of the inductor L2, the other end of the first energy source is grounded, and a second end of the inductor L2 is an output end of the first power supply circuit, and is used for outputting the first power supply to the processing unit 120, for example, a switching element of the processing unit 120. In some embodiments, the first energy source may be a direct current power source, such as a 12V direct current source. In some embodiments, the inductor L2 may be replaced with a magnetic bead or other noise suppressing component.

In some embodiments, as shown in fig. 3A, the filter capacitors C4 and C28 are connected in parallel to both ends of the first dc source, one ends of the filter capacitors C5 and C29 are connected in parallel to the second end of the inductor L2, and the other ends of the filter capacitors C5 and C29 are connected in parallel to the ground. The inductor L2, the capacitor C4, the capacitor C5, the capacitor C28 and the capacitor C29 form a pi-type filter circuit for filtering the interference of the direct current bus. In some embodiments, the capacitance of the capacitor C4 is different from the capacitance of the capacitor C28, and the capacitance of the capacitor C5 is the same as the capacitance of the capacitor C29, so as to filter noise interference in different frequency bands.

As shown in fig. 3B, the second power supply circuit is configured to provide a second power supply to the driver U1 of the processing unit 120. In some embodiments, the second power supply circuit includes a second energy source for providing a second power source, one end of the second energy source is grounded through a capacitor C30, the other end of the second energy source is connected to an input terminal of a voltage converter U2, and an output terminal of the voltage converter U2 is connected to an electrical energy input terminal of the driver U1 to be a rated operation voltage required by the driver U1. In some embodiments, the second energy source may be a direct current power source, such as a 12V direct current source. If the efficiency of the driver U1 is highest when the power supply voltage is 7-8V, the voltage converter U2 may convert the 12V dc power supply into a dc power supply in the range of 7-8V to supply power to the driver U1. In some embodiments, it is desirable to adjust the output voltage of the voltage converter U2 according to the supply voltage required by different models of drivers U1.

In some embodiments, the output terminal of the voltage converter U2 is connected to the regulation terminal of the voltage converter U2 through a resistor R2, the regulation terminal of the voltage converter U2 is grounded through a resistor R1, and the resistor R1 and the resistor R2 are used to regulate the output voltage of the voltage converter U2. In some embodiments, the voltage converter U2 may be a module with a voltage conversion function, such as a linear regulator (LDO, low dropout regulator), DCDC, or some power supply module.

In some embodiments, the power supply circuit 110 may further include a third power supply circuit, a fourth power supply circuit, a fifth power supply circuit … …, and the like, which are similar in structure to the second power supply circuit, for providing a power supply voltage (e.g., a bias voltage, a third power supply, a fourth power supply … …) to other active electronic devices in the power supply apparatus 100, such as an operational amplifier in a voltage sampling circuit, a comparator in a comparison circuit, and a level shifter U3 in a driving circuit, and the like.

The specific implementation of the boosting process and controlling the resonant frequency will be described in detail below using a boost circuit as an example of a resonant circuit.

Fig. 4 is a schematic circuit configuration diagram of the processing unit 120 according to some embodiments of the present specification.

In some embodiments, the processing unit 120 may include a resonant circuit, where the resonant circuit includes a resonant capacitor set and a resonant inductor, where the resonant capacitor set includes one or more resonant capacitors, and the resonant capacitor set is connected in series with the resonant inductor, and the resonant capacitor set and the resonant inductor are used to adjust the resonant frequency f.

A resonant circuit is a network of ports exhibiting capacitive, inductive and resistive properties, which can produce ac power. In some embodiments, the resonant circuit is purely resistive when the frequency of the input drive signal (i.e., the control signal described below) is equal to the resonant frequency of the resonant circuit; when the frequency of the input driving signal is smaller than the resonance frequency of the resonance circuit, the resonance circuit is capacitive; when the frequency of the input drive signal is greater than the resonant frequency of the resonant circuit, the resonant circuit exhibits an inductance. In some embodiments, the resonant circuit may convert the dc power to ac power through the energy storage and conversion functions of the resonant capacitor and the resonant inductor, thereby replacing the direction of current in the resonant circuit while boosting the voltage. As shown in fig. 4, the resonant circuit includes a resonant capacitor bank (capacitors C1, C15-C27 shown in fig. 4) and a resonant inductor (inductor L1 shown in fig. 4), from which current flows to the resonant capacitor when the resonant capacitor bank is charged, and from which current flows to the resonant inductor when the resonant capacitor bank is discharged.

The resonance frequency is the frequency at which the resonant circuit resonates, and is an inherent characteristic of the resonant circuit. When the signal frequency at the resonant circuit (i.e. the frequency of the current commutation) is at the resonant frequency, the resonant circuit resonates and the current of the resonant circuit approaches a peak. In some embodiments, the switching frequency of the processing unit 120 may include a resonant frequency f of the resonant circuit.

In some embodiments, the resonant frequency f is controlled by the resonant capacitance and resonant inductance of the resonant circuit. In some embodiments, the resonant frequency f of the resonant circuit may be adjusted by adjusting parameters of the resonant capacitance C and the resonant inductance L based on the resonant frequency formula of the resonant circuit. In some embodiments, the resonant frequency formula may be the following formula (1):

wherein f is the resonant frequency of the resonant circuit, L is the inductance value of the resonant inductor, and C is the capacitance value of the resonant capacitor group.

In some embodiments, the resonant capacitor bank may include one or more capacitors and the resonant inductance may be one or more inductors. In some embodiments, the inductance value L of the resonant inductor may be adjusted by adjusting a parameter of the inductor L1. In some embodiments, the capacitance value C of the resonant capacitor bank may be adjusted by adjusting one or more of the number, parameters, and connection of the capacitors C1 and C15-C27. An exemplary combination of the resonant inductor L1 and the resonant capacitor group C is described below by taking fig. 4 as an example.

As shown in fig. 4, the resonant inductor may include an inductor L1, and the resonant capacitor group may include a capacitor C1 and capacitors C15-C27. The capacitor C1 and the capacitor C22 are connected in parallel with the capacitor C23, one end of the capacitor C1 is connected with the inductor L1, and the other end of the capacitor C1 is grounded. The capacitor C15 is connected with the capacitor C16 in series, the capacitor C15 is connected with the capacitor C24 in parallel, and one end of the capacitor C16 is grounded. One end of the capacitor C15 away from the capacitor C16 is connected to the inductor L1. The capacitor C17 is connected with the capacitor C18 in series, the capacitor C19 is connected with the capacitor C18 in parallel, one end of the capacitor C18 is connected with the bias voltage, and one end of the capacitor C17 away from the capacitor C18 is connected with the resonant inductor L1. Capacitor C20 and capacitor C21 are connected in parallel with capacitor C27, one end of capacitor C20 is connected to inductor L1, and the other end of capacitor C20 is connected to the bias voltage. The capacitor C25 is connected in series with the capacitor C26, one end of the capacitor C25 is connected to the resonant inductor L1, and one end of the capacitor C26 is connected to the bias voltage.

It should be noted that, since the volume of the inductor is generally larger than that of the capacitor, in some embodiments, the resonant inductor may be an inductor with a smaller inductance value, so as to maintain the volume of the resonant inductor. In some embodiments, to ensure that the ripple of the power supply device is small, the inductance value of the resonant inductor may also be selected according to the rate of change of the current and the stored energy of the inductor. In some embodiments, the resonant inductor may have an inductance ranging from 10nH to 10uH.

In some embodiments, the output of the resonant circuit may include a connection point of the resonant capacitor bank and the resonant inductor for outputting a resonant signal, the resonant signal having a voltage higher than a voltage of the first power supply. To provide positive and negative power, in some embodiments, the resonant signal may be an ac signal for subsequent processing with a rectifying and filtering circuit, outputting positive and negative power. In some embodiments, the resonant signal may be a single frequency sinusoidal signal.

Fig. 5 is a schematic diagram of frequency versus current as shown in accordance with some embodiments of the present description.

In some embodiments, the signal frequency of the input drive signal of the resonant circuit versus the current of the resonant circuit may be curve 1 in fig. 5. Since the resonant circuit corresponds to a purely resistive port circuit when the input drive signal is equal to the resonant frequency, the current of the resonant circuit is maximum and the output power is also maximum. As shown in curve 1, when the input driving signal of the resonant circuit is at the resonant frequency f ₀ When the current of the resonant circuit approaches a peak value, the signal strength is larger, so that interference of other signals is reduced. In some embodiments, the frequency of the load signal versus the load current may be curve 2 in fig. 5. In some embodiments, the effective frequency range of the load may be [ a, b ]Wherein a is a first effective frequency, b is a second effective frequency, and a is required to be smaller than or equal to b when preset so as to enable [ a, b ]]The range interval or specific value may be set, in some embodiments, to any value from 2Hz to 20Hz, and b is any value from 6MHz to 20KHz, and in specific implementations, different first effective frequency a and second effective frequency b may be selected according to different loads, which is not specifically limited in this application. When the frequency of the load signal is [ a, b]And when the load is in the internal state, the load current is larger, so that the maximum signal-to-noise ratio of the signal acquisition system where the load is positioned is ensured.

The load signal is a signal related to the load in operation, and comprises a signal acquired by the load in operation and a processed signal, and the effective frequency range of the load is a frequency range where most of the signals related to the load in operation are located. For example, when the load is a sound collection system, the effective frequency range of the sound collection system may be 20Hz-20KHz; when the load is an ultrasonic diagnostic apparatus, the frequency range of the ultrasonic diagnostic apparatus is usually 2-20MHz; when the load is an ultrasonic probe, the effective frequency range that the ultrasonic probe can receive can be 2-6MHz. The effective frequency range of the load is not particularly limited in this application.

In some embodiments, the resonant frequency f of the resonant circuit is within the effective frequency range of the load [ a, b]Outside of that. As shown in fig. 5, the resonance frequency f of the resonance circuit is within the effective frequency range [ a, b]To the left of (i.e. resonant frequency f) ₀ In the effective frequency range [ a, b]Outside the frequency ranges [ a, b]The load current corresponding to curve 2 is greater than the current of the resonant circuit corresponding to curve 1, which can be explained in the frequency range [ a, b]In comparison with the load current, the current of the resonant circuit is smaller and the signal strength of the resonant circuit is also smaller.

That is, when the resonant frequency f of the resonant circuit is adjusted to be out of the effective frequency range of the load, in the frequency range [ a, b ], the signal strength of the resonant circuit is smaller for the signal of the load, so that the normal operation of the load is difficult to be affected, thereby reducing the EMI of the power supply device 100 to the load and improving the working quality of the load.

In some embodiments, the n-th harmonic of the resonant frequency f may be in the effective frequency range of the load [ a, b]Outside of that. In some embodiments, the resonant frequency f may be in the nth harmonic range of the effective frequency rangeOutside of that. In some embodiments, the n-th harmonic of the resonant frequency f may be in the n-th harmonic range of the effective frequency range Outside of that.

The n-th harmonic is a wavelet with a frequency higher than the fundamental wave of the signal, where n is an integer greater than 1. In some embodiments, the nth harmonic of the resonant frequency f is the fundamental wave of the resonant circuit outputDistorted wavelets, which also cause electromagnetic interference to the load. In some embodiments, the n-th harmonic of the effective frequency range is a wavelet of the fundamental wave of the load signal, which is also referred to during operation. In some embodiments, the frequency of the n-th harmonic is n times the fundamental frequency. In some embodiments, the frequency of the n-th harmonic is n times the resonant frequency f. For example, when the resonance frequency is f, the frequency of the third harmonic is 5f, and the frequency of the fifth harmonic is 5f. In some embodiments, the frequency of the n-th harmonic of the effective frequency range is n times the load frequency, corresponding to the frequency of [ a, b ] in the effective frequency range]In the case of (a), the frequency range of the n-th harmonic of the effective frequency range may be

In order to avoid electromagnetic interference of signals and harmonics to the load, the influence on the load can be reduced by limiting the frequency of the signals. In some embodiments, the resonant frequency f and the n-th harmonic of the resonant frequency f can be adjusted to be within the effective frequency range [ a, b ] of the load ]N-harmonic range of effective frequency rangeOutside of that. Thus, for the signals of the load, the signals of the resonant circuit and the signals of the harmonic waves are not in the useful bandwidth of the load signals, the load can filter out the modulation interference by digital or analog filtering and signal processing means, and the load is difficult to influence in the frequency range [ a, b]And the frequency range of the n-order harmonic +.>Thereby further reducing the EMI of the power supply device 100 to the load and improving the working quality of the load.

In some embodiments, the electromagnetic environment within the housing may also be isolated from the environment outside the housing by providing a shielded enclosure within the power supply 100 that fits over the exterior, thereby further reducing the effects of EMI interference on the load.

In some embodiments, the resonant circuit may further include a switching element (Q1 and Q2 as shown in fig. 4) and a driver (U1 as shown in fig. 4), the power input of the driver being connected to the power circuit 110, the driver being configured to receive the driving signal and control the switching element, the switching element being connected to the power circuit 110, the switching element being configured to receive the first power supply.

The driver U1 may be an integrated circuit that drives the switching elements to switch states (e.g., on and off states). In some embodiments, the driving end PWM of the driver U1 may receive a driving signal, and the driver U1 may control the switching element according to the driving signal. For example, the driving terminal PWM of the driver U1 may receive a pulse width modulation signal, and the driver U1 outputs a high-low level according to a duty ratio of the pulse width modulation signal to control on and off of the switching element. For a specific implementation of the driving signal, reference may be made to the following description of the driving circuit, which is not repeated here.

It should be noted that in some embodiments, the adjustment of the resonant frequency of the resonant circuit also needs to take into account the damage of the switch and the interference of the switch to the user. Taking the switching loss as an example, the lower the resonance frequency, the lower the switching frequency, the smaller the switching loss, so that the efficiency of the resonance circuit can be increased. Taking the switching interference as an example, if the resonance frequency is out of the hearing frequency range of the user, the sound signal generated when the switching element is switched on and off is difficult to capture by the user's human ear, so that the interference to the user can be reduced.

In some embodiments, the power input of the driver U1 is connected to the power circuit 110, and may be used to receive the second power supply provided by the power circuit 110. The specific implementation of the second power supply may refer to the specific description in the power supply circuit 110, which is not repeated here. In some embodiments, the driving output pin UGATE and the driving output pin LGATE of the driver U1 are respectively connected to the control terminals of the corresponding switch devices for outputting the control signals. In some embodiments, the enable end EN/PG of the driver U1 is configured to receive an enable signal, and the driver U1 may control itself to be turned on or off according to the enable signal. In some embodiments, the mode select terminal BOOT of the driver U1 is connected to the PHASE terminal PHASE through the bootstrap capacitor C41 to avoid damaging the device due to excessive voltage. In some embodiments, the PHASE terminal PHASE of driver U1 may be connected to the source of fet Q1 and the drain of fet Q2 to provide a return path for fet Q1. In some embodiments, the ground GND of the driver U1 is connected to ground.

The switch element is a component for controlling the on or off of the circuit. In some embodiments, the control terminal of the switch element may receive a control signal (such as the input driving signal described above), and switch itself to an on state or an off state according to the control signal. Taking fig. 4 as an example, the switching element may include a fet Q1 and a fet Q2. The grid electrode of the field effect transistor Q1 is connected with a driving output pin UGATE of the driver U1, the grid electrode of the field effect transistor Q2 is connected with a driving output pin LGATE of the driver U1, the drain electrode of the field effect transistor Q1 is connected with the power circuit 110, the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q2, and the source electrode of the field effect transistor Q2 is grounded. The connection point of the source electrode of the field effect transistor Q1 and the drain electrode of the field effect transistor Q2 is also respectively connected with a PHASE end PHASE of the driver U1 and a resonance inductor. In some embodiments, the field effect transistor Q1 and the field effect transistor Q2 may be alternately turned on according to the driving signal to supply power to the resonant inductor and the resonant capacitor. The specific control process of the switch element can be referred to the following description of the operation process of the resonant circuit, which is not repeated here.

To more clearly illustrate the operation of the resonant circuit, the resonant circuit of fig. 4 may be simplified to the resonant circuit of fig. 6.

Fig. 6 is a simplified schematic diagram of a resonant circuit according to some embodiments of the present description.

In some embodiments, the resonant capacitor group may include a first resonant capacitor subset (equivalent resonant capacitor C100 shown in fig. 6) and a second resonant capacitor subset (equivalent resonant capacitor C200 shown in fig. 6), where one end of the first resonant capacitor subset is connected to one end of the second resonant capacitor subset, the other end of the first resonant capacitor subset is used to receive the bias voltage, and the other end of the second resonant capacitor subset is grounded.

The first and second subsets of resonant capacitors are each equivalent capacitance sets of the resonant circuit, such as equivalent resonant capacitors C100 and C200 depicted in fig. 6. In some embodiments, the first subset of resonant capacitors may include capacitors C17-C21 and C25-C27 of FIG. 4, and the second subset of resonant capacitors may include capacitors C1, C15-C16 and C22-C24 of FIG. 4. In some embodiments, the parameters of the first and second resonant capacitor subsets may be adjusted by adjusting one or more of the number, parameters, and manner of connection of the capacitors C1, C15-C27, such that the resonant frequency of the resonant circuit may be quickly adjusted.

In some embodiments, the field-effect transistor Q1, the field-effect transistor Q2, and the resonance inductance L1 in fig. 6 are respectively in one-to-one correspondence with the field-effect transistor Q1, the field-effect transistor Q2, and the resonance inductance L1 in fig. 4. The specific connection manner of the above components in fig. 6 can be referred to the specific description of the connection manner in fig. 4.

It should be noted that, when the bias voltage is not set, the resonant circuit controls the direction of the current in the resonant circuit to be switched by the state switching (such as on and off) of the switching element, so that a part of the ac component can be transmitted and diffused through the circuit board, so that the output of the power supply device 100 has ripple waves, and EMI is generated to the load.

To reduce ripple generated in the resonant circuit, in some embodiments, one end of the first subset of resonant capacitors is set with a bias voltage. In this way, the bias voltage may be matched with the first power supply, and when the state of the switch element is switched, the bias voltage may be matched with the first power supply, so that currents of the first resonant capacitor subset and the second resonant capacitor subset in the resonant circuit are symmetrical, thereby reducing ripple waves in the output of the power supply device 100 and avoiding interference with loads.

For example, as shown in fig. 6, assuming that the first power supply and the bias voltage can both provide a dc voltage of 12V, the field effect transistors Q1 and Q2 can form two current loops, one including the field effect transistor Q1, the resonant inductor L1, and the equivalent resonant capacitor C200 (i.e., the second resonant capacitor subset), and the other including the field effect transistor Q2, the resonant inductor L1, and the equivalent resonant capacitor C100 (i.e., the first resonant capacitor subset). When the field effect transistor Q1 is turned on and the field effect transistor Q2 is turned off, the voltage at the two ends of the equivalent resonant capacitor C200 is +6V, the voltage at the two ends of the resonant inductor L1 is +6V, and current flows from the field effect transistor Q1 to the resonant inductor L1. When the field effect transistor Q1 is cut off and the field effect transistor Q2 is turned on, the voltage at two ends of the equivalent resonant capacitor C100 is +6V, the voltage at two ends of the resonant inductor L1 is-6V, and current flows from the resonant inductor L1 to the field effect transistor Q2. That is, the voltages across the equivalent resonant capacitors C100 and C200 are the superposition of the +6v dc bias voltage and the resonant signal, and the voltage across the resonant inductor L1 is the square wave drive voltage of ±6v.

Therefore, at a duty ratio of 50% of the driving signal PWM, 50% of the current flows to 12V and 50% of the current flows to 0V, so that the currents in the equivalent resonant capacitors C100 and C200 are symmetrical, thereby reducing the ripple of the resonant circuit output.

In some embodiments, the processing unit 120 may further include a processing circuit, an input of the processing circuit being connected to an output of the boost circuit, a positive voltage output of the processing circuit may provide a positive load power supply, and a negative voltage output of the processing circuit may provide a negative load power supply.

The processing circuit may be a circuit for deforming the electrical energy. In some embodiments, the processing circuitry may include: one or more of the functional circuits such as a rectifying circuit, a filtering circuit, a voltage stabilizing circuit and the like. In some embodiments, the processing circuit may include a filter voltage regulator circuit, e.g., the processing circuit may include an LDO circuit. In some embodiments, the processing circuit may include a rectifying and filtering circuit, such as the processing circuit may include a direct current half-wave rectifying and voltage doubling circuit. It should be noted that, the processing circuit and the processing unit 120 are different circuit devices, the processing unit 120 may convert the first power supply into a positive load power supply and the negative load power supply, and the processing circuit may perform electric energy processing such as rectification, filtering, voltage stabilizing, and the like on the high-voltage electric energy output by the boost circuit.

In some embodiments, the processing circuit may process the output of the boost circuit to obtain a positive load power supply and a negative load power supply, the positive load power supply and the negative load power supply being of opposite polarity. The specific implementation of the processing circuit will be described below by taking a rectifying and filtering circuit and a filtering and voltage stabilizing circuit as examples.

In some embodiments, as shown in fig. 4, when the boost circuit is a resonant circuit, the processing circuit may include a rectifying filter circuit.

In some embodiments, the difference between the voltage of the bias voltage and the voltage of the first power supply may be within a preset voltage range. In some embodiments, the capacitance value of the first subset of resonant capacitors is similar or identical to the parameter of the first subset of resonant capacitors, and the fet Q1 is similar or identical to the fet Q2. Therefore, the voltage of the bias voltage is similar to or the same as that of the first power supply, so that the voltage of the resonant capacitor and the voltage at two ends are similar to or the same as that of the first power supply, and the ripple wave output by the resonant circuit is further reduced.

In some embodiments, the processing unit 120 may further include a rectifying and filtering circuit, where an input end of the rectifying and filtering circuit is connected to an output end of the resonant circuit, the rectifying and filtering circuit is symmetrically disposed with the resonant circuit as a center, a first output end of the rectifying and filtering circuit is used for providing a positive load power supply, and a second output end of the rectifying and filtering circuit is used for providing a negative load power supply; the symmetry degree of the positive load power supply and the negative load power supply is within a preset symmetry range.

The rectifying and filtering circuit may be a circuit that converts alternating current power to direct current power. In some embodiments, the rectifying and filtering circuit may include a first rectifying and filtering sub-circuit and a second rectifying and filtering sub-circuit, the first rectifying and filtering sub-circuit and the second rectifying and filtering sub-circuit being symmetrically disposed about the resonant circuit. The input end of the first rectifying and filtering sub-circuit and the input end of the second rectifying and filtering sub-circuit can respectively receive the resonance signals, and the resonance signals are respectively processed in the same rectifying and filtering mode, so that a positive load power supply and a negative load power supply with high symmetry are provided. In some embodiments, the first and second rectifying and filtering sub-circuits may be direct current half-wave rectifying and voltage doubling circuits.

In some embodiments, the preset symmetry range may characterize a degree of symmetry of the positive load power supply and the negative load power supply. For example, the smaller the preset symmetry range, the more symmetrical the positive and negative load power supplies are. The larger the preset symmetry range, the smaller the degree of symmetry of the positive load power supply and the negative load power supply. In some embodiments, the preset symmetry range may be adjusted by adjusting the structure of the rectifying and filtering circuit. In some embodiments, the preset symmetry range may be [0.99,1 ]. Preferably, the predetermined symmetry range may be [0.999,1 ].

The following provides structural description symmetry of an exemplary rectifying and filtering circuit.

In some embodiments, as shown in FIG. 4, the first rectifying and filtering sub-circuit may include capacitors C3, C6-8 and diodes D3-D4. One end of the capacitor C3 is connected with the output end of the resonant circuit, and the other end of the capacitor C3 is connected with a connecting point of the capacitors C6 and C7. The capacitors C6-C8 are connected in parallel, one end of the capacitor C6 is grounded, one end of the capacitor C8 is grounded, and the connection point of the capacitor C7 and the capacitor C8 is used for providing a forward load power supply. The positive electrode of the diode D3 is connected to the negative electrode of the diode D2, and the negative electrode of the diode D3 is connected to the connection point between the capacitors C7 and C8. The negative electrode of the diode D4 is connected to the connection point between the capacitor C6 and the capacitor C7, and the positive electrode is grounded.

In some embodiments, as shown in FIG. 4, the second rectifying and filtering sub-circuit may include capacitors C2, C9-11 and diodes D1-D2. One end of the capacitor C2 is connected with the output end of the resonant circuit, and the other end of the capacitor C2 is connected with a connecting point of the capacitors C9 and C10. The capacitors C9-C11 are connected in parallel, one end of the capacitor C9 is grounded, one end of the capacitor C11 is grounded, and the connection point of the capacitor C10 and the capacitor C11 is used for providing negative load power supply. The positive electrode of the diode D1 is connected to at least the connection point of the capacitors C9 and C10, and the negative electrode is grounded. The negative electrode of the diode D2 is connected to the positive electrode of the diode D1, and the positive electrode of the diode D2 is connected to the connection point between the capacitor C10 and the capacitor C11.

In this way, the structure of the first rectifying and filtering sub-circuit and the structure of the second rectifying and filtering sub-circuit are symmetrical with respect to the resonance circuit, and the resonance signal output from the resonance circuit can be rectified and filtered symmetrically.

The rectifying and filtering process will be exemplarily described below taking the above-described first rectifying and filtering sub-circuit and second rectifying and filtering sub-circuit as an example.

The resonance signal of the resonance circuit is assumed to be single-frequency sine wave, and the amplitude is V _m . For the first rectifying and filtering sub-circuit, in the negative half cycle of the resonant signal, the diode D4 is turned on, the diode D3 is turned off, and the resonant signal charges the capacitor C3 to V through the diode D4 _m -V _D At the positive half cycle of the resonant signal, diode D4 is turned off and diode D3 is turned on, and the resonant power supply charges capacitor C8 through capacitor C3 and diode D3. Due to the voltage V across the capacitor C3 _m -V _D In addition to Vm of the resonant capacitor and the tube voltage drop of diode D3, C8 can be charged to 2 (V _m -V _D ) Because of the direction of the diode, the direction of the voltage across C11 is the same as the direction of the resonant signal, and the forward load supply is positive supply + HV.

For the second rectifying and filtering sub-circuit, the diode D1 is turned on and the diode D2 is turned off in the positive half cycle of the resonant signal, and the resonant signal charges the capacitor C2 to V through the diode D1 _m -V _D (VD is the diode drop) and diode D1 is turned off and diode D2 is turned on during the negative half of the resonant signal, and the resonant signal charges capacitor C11 through capacitor C2 and diode D2. Due to the voltage V across the capacitor C2 _m -V _D (capacitor voltage cannot be changed suddenly), plus V of resonant capacitor C _m And diode D2, can charge capacitor C11 to 2 (V) _m -V _D ) The negative load power supply is negative power supply-HV, since the direction of the voltage across the C11 is opposite to the direction of the resonant signal, and in the direction of the diodes D1-D2.

In some embodiments, a plurality of charging combinations of capacitors and diodes may be provided in the rectifying and filtering subcircuit for voltage doubling charging. Taking the first rectifying-filtering sub-circuit as an example, n charging combinations such as capacitors C6-C7 and diodes D3-D4 can be provided, so that the capacitor C8 can be charged to 2n (V _m -V _D ). Correspondingly, the forward load power supply may be positive power + nHV.

It should be noted that the catalyst may be contained in one or more ofThe load capacitances C11 and C8 are charged to 2 (V _m -V _D ). After the charging is completed, if the load is consumed, the voltages of the capacitors C11 and C8 are reduced, and the charging process is repeated, so that the output voltage is kept at a certain value. In some embodiments, the capacitors C11 and C8 may be composed of a plurality of capacitors, respectively, and the capacitors C11 and C8 may be used for energy storage and smoothing filtering, and together with the diodes D1-D4, perform a shaping filtering function, and change the ac signal output by the resonant circuit into a dc power supply.

Therefore, through the symmetrical structure of the rectifying and filtering circuit, the same rectifying and filtering mode can be adopted to process the resonance signals respectively, so that the symmetry of a positive load power supply and a negative load power supply is improved, and the generation of second harmonic waves to cause EMI to the load is avoided.

In some embodiments, the first rectifying and filtering sub-circuit may further include an inductor L3, where one end of the inductor L3 is connected to a connection point of the capacitor C7 and the capacitor C8, and the other end is used to output the forward target load power source +hv_f. Correspondingly, the second rectifying and filtering sub-circuit can further comprise an inductor L4, one end of the inductor L4 is connected with a connection point of the capacitor C10 and the capacitor C11, and the other end of the inductor L4 is used for outputting a negative target load power supply-HV_F. The inductors L3 and L4 can be used as magnetic beads, and the outputs are filtered again, so that a positive target load power supply +hv_f and a negative target load power supply-hv_f are provided, and the EMI interference of the power supply equipment to the load is reduced.

In some embodiments, the current of the positive load power supply and the current of the negative load power supply are within a preset current range.

In some embodiments, the preset current range may indicate that the current of the positive load power supply and the current of the negative load power supply are stable. It should be noted that, because the resonant circuit is used for electric energy conversion, the current of the positive load power supply and the current of the negative load power supply can be stabilized, and compared with the charging mode using a constant voltage, the charging time can be controlled by the charging mode using a constant current. For example, when the ultrasound device generates a 128 channel full wave signal pulse of 4.0MHz lasting 240ns, the voltage across the load capacitance of 35uF will drop by 1V. According to the capacitance charge-discharge equation (2) below), the time to charge the load capacitance can be calculated. The capacitance charge-discharge formula may be:

Wherein I is the current output by the power supply device 100, C is the capacitance value of the load capacitor, V is the voltage across the capacitor, and t is the charge-discharge time. Thus, if the voltage drop of the load capacitor is 1V, the power supply device 100 is required to output a current of 0.5A for 70us to be charged again. The charging period may be increased by decreasing the current output from the power supply device 100, or may be decreased by increasing the current output from the current supply device 100.

In some embodiments, the current of the positive load power supply and the current of the negative load power supply may be adjusted according to the load's demand for current. In some embodiments, the current of the positive load power supply and the current of the negative load power supply may be controlled by the load current and the load capacitance.

Fig. 7 is a schematic diagram of a processing unit 120 according to some embodiments of the present disclosure.

In some embodiments, as shown in fig. 7, the processing unit 120 may further include a filtering voltage stabilizing circuit, where an input end of the filtering voltage stabilizing circuit is connected to an output end of the boost circuit, the filtering voltage stabilizing circuit is symmetrically disposed around the boost circuit, a first output end of the filtering voltage stabilizing circuit is used for providing a positive load power supply, and a second output end of the filtering voltage stabilizing circuit is used for providing a negative load power supply; the symmetry degree of the positive load power supply and the negative load power supply is within a preset symmetry range.

The filter voltage stabilizing circuit can be a circuit for removing signal impurities. In some embodiments, the filtering voltage stabilizing circuit may include a first filtering voltage stabilizing sub-circuit and a second filtering voltage stabilizing sub-circuit, the first filtering voltage stabilizing sub-circuit and the second filtering voltage stabilizing sub-circuit being symmetrically disposed about the boost circuit. The input end of the first filtering voltage stabilizing sub-circuit and the input end of the second filtering voltage stabilizing sub-circuit can respectively process the output of the voltage boosting circuit in the same filtering voltage stabilizing processing mode, so that a positive load power supply and a negative load power supply with high symmetry are output. In some embodiments, the first and second filtered voltage regulator circuits may be LDO circuits. The following provides structural illustration symmetry of an exemplary filter voltage regulator circuit.

In some embodiments, as shown in fig. 7, the first filtering regulator circuit may include a first power supply filter circuit, an LDO circuit, a power path, and a second power supply filter circuit. The first power supply filter circuit, the LDO circuit and the second power supply filter circuit are sequentially connected, the input end of the first power supply filter circuit is connected with the output end of the boost circuit, the second power supply filter circuit is used for outputting a forward load power supply, and the power path is connected with the LDO circuit in parallel.

In some embodiments, the power supply filter circuit may be a circuit that filters signal noise, e.g., an LC, RC, etc. filter circuit. In some embodiments, the LDO circuit may reduce switching noise. Since LDO circuits generally have a smaller input voltage range and a larger power consumption, in order to expand the input voltage range of the LDO and reduce the power consumption, in some embodiments, the LDO of the first filtering regulator circuit is designed with floating ground. In some embodiments, the power path may be a circuit that functions as a shunt. In some embodiments, the current of the LDO circuit may be reduced by shunting a parallel power path in the load, thereby reducing the power consumption of the LDO circuit. In some embodiments, the power path may be a power device such as a MOSFET.

Taking the filtering voltage stabilizing circuit shown in fig. 7 as an example, a specific implementation manner of the first filtering voltage stabilizing sub-circuit is described in detail. In some embodiments, the first filtering voltage regulator circuit may utilize the first power supply filtering circuit to reduce noise output by the boost circuit and utilize the LDO circuit to reduce switching noise. Most of the current output by the first power supply filter circuit is transmitted through the power path, so that LDO power consumption can be reduced. In some embodiments, the LDO circuit in the first filtering voltage stabilizing sub-circuit may reduce noise in the power output by the LDO circuit through the second power filtering circuit, thereby outputting a forward load power supply. The specific implementation manner of the second filtering voltage stabilizing sub-circuit is the same as that of the first filtering voltage stabilizing sub-circuit, and will not be repeated here.

In some embodiments, the processing unit 120 may further include a digital-to-analog conversion circuit, an input terminal of the digital-to-analog conversion circuit is connected to the processor, and a first output terminal of the digital-to-analog conversion circuit is connected to the driving terminal of the voltage boosting circuit. In some embodiments, the digital-to-analog conversion circuit may convert the output of the processor into a voltage signal and send the voltage signal to the boost circuit through the first output terminal to control the magnitude of the voltage output by the boost circuit.

In some embodiments, processing unit 120 may also include signal modulation circuitry. The input end of the signal modulation circuit is connected with the second output end of the digital-to-analog conversion circuit, and the output end of the signal modulation circuit is connected with the LDO circuit. In some embodiments, the digital-to-analog conversion circuit may convert the output of the processor into a voltage signal, process the voltage signal through the signal modulation circuit, and send the processed voltage signal to the LDO circuit, so as to control the LDO circuit to perform filtering voltage stabilization processing on the electric energy.

Fig. 8 is a schematic diagram of a driving circuit according to some embodiments of the present specification.

In some embodiments, the power supply device 100 may further include a driving circuit, where an input end of the driving circuit is connected to the processor MCU, and an output end of the driving circuit is connected to the driving end of the driver U1, and the driving circuit may output a driving signal to the driver U1 according to an instruction sent by the processor MCU.

Fig. 9 is a schematic circuit configuration diagram of a driving circuit shown according to some embodiments of the present specification.

The driving circuit may be a circuit that transmits an instruction, such as an instruction (initial driving signal) issued by the processor MCU, to the driver U1. In some embodiments, as shown in fig. 8, when the level of the initial driving signal output by the processor MCU is inconsistent with the level requirement input by the driver U1, the driving circuit may include a level shifter U3, an input terminal a of the level shifter U3 is connected to the processor MCU, may receive the initial driving signal from the processor MCU, an output terminal B of the level shifter U3 is connected to the driver U1, and may transmit the driving signal to the driver U1. The level shifter U3 may be an integrated circuit that shifts levels. In some embodiments, the level shifter U3 may adjust the level of the initial driving signal to avoid that the driver U1 cannot process signals with unsuitable levels.

In some embodiments, the output terminal B of the level shifter U3 may be connected to the driver U1 through a resistor R17, the connection point of the resistor R17 and the driver U1 may also be connected to one end of a resistor R18, the other end of the resistor R18 is grounded, and the resistors R17-R18 may be used for over-current protection. In some embodiments, the power input VCCA of the level shifter U3 may receive a third power supply, the power input VCCB of the level shifter U3 may receive a fourth power supply, and the voltages of the third power supply and the fourth power supply may be the same or different. In some embodiments, the driving terminal DIR of the level shifter U3 may receive the third power supply, such that the input terminal a of the level shifter U3 may receive the signal and the output terminal B of the level shifter U3 may transmit the signal. Wherein the driving end DIR of the level shifter U3 may be used to control the flow direction of the signal. In some embodiments, the ground GND of the level shifter U3 is grounded.

The processor may be an integrated circuit that performs the processing services. In some embodiments, the processor may send an initial drive signal to the driver U1 to control the drive frequency of the driver U1. In some embodiments, the processor may also send an enable signal to the driver U1 to control the switching and closing of the driver U1. The specific implementation of the enable signal may refer to the following related description of the switch circuit, which is not repeated here.

The driving signal may be a signal with variable parameters, such as an initial driving signal sent by the processor MCU and a driving signal sent by the level shifter U3. In some embodiments, the drive signal comprises one or more of a carrier signal, a pulse signal, a sinusoidal signal, and the like. For example, the initial drive signal and the drive signal may each be a pulse width modulated signal. In some embodiments, the inherent characteristics of the drive signal may be used to adjust the switching frequency of the switching element. For example, the drive signal may adjust the operating state of the resonant circuit.

In some embodiments, the frequency of the control signal output by the driver may be adjusted by controlling the frequency of the drive signal. In some embodiments, the difference between the frequency of the driving signal and the resonant frequency f is within a preset range. In some embodiments, the difference between the frequency of the driving signal and the resonant frequency f is within a preset range. In some embodiments, the frequency of the drive signal may be adjusted such that the drive signal itself, as well as the control signal output by the driver, approaches the resonant frequency f. Taking the driving signal as a pulse width modulation signal as an example, when the pulse width modulation signal and the control signal approach the resonant frequency of the resonant circuit, the resonant circuit of the resonant circuit can resonate, and the current flowing through the switch when the switch element (Q1 and Q2 shown in fig. 4) is turned on and off is equal to zero, so that the switching loss can be reduced, and the efficiency of the power supply device 100 can be improved.

In practical use, the power supply device 100 for supplying power to the load may be one or more. In order to avoid excessive ripple caused by superposition of the driving signals when the power supply apparatus 100 is plural, in some embodiments, the processor MCU may control the phase difference between the driving signals and the driving signals of other power supply apparatuses 100, so as to cancel EMI interference caused by the ripple.

Fig. 10 is a schematic diagram of a switching circuit according to some embodiments of the present description.

In some embodiments, as shown in fig. 10, the power supply device 100 may further include a switching circuit, an input terminal of which is connected to the processor MCU, which may receive the initial enable signal. The output end of the switching circuit is connected with the enable end EN/PG of the driver U1, and the output end of the switching circuit is used for sending out an enable signal. Correspondingly, the enable end EN/PG of the driver U1 is configured to receive the enable signal, and switch the driver U1 according to the enable signal.

The switching circuit may be a circuit that transmits switching instructions. In some embodiments, the switching circuit may send an initial enable signal to drive the switching element by using the processor MCU, and output the enable signal to the controller U1 by controlling the switching element to be turned on and off. Thus, the processor MCU can realize the function of remotely turning on or remotely turning off the driver U1 through the switching circuit, so that the loss of the power supply apparatus 100 can be effectively reduced and the EMI of the switching circuit to the load can be reduced.

The enable signal may be a signal with a level change, such as an initial enable signal sent by the processor MCU and an enable signal sent by the switching circuit. In some embodiments, the enable signal may include one or more of a square wave signal, a pulse signal, a sinusoidal signal, and the like. In some embodiments, the enable signal may include a level signal, with the high and low level signals controlling the device to switch the corresponding state. For example, the driver U1 is turned on when the enable signal is high, and the driver U1 is turned off when the enable signal is low.

An exemplary switching circuit is provided below to describe a specific implementation of remote switching control.

In some embodiments, as shown in fig. 10, the switching circuit may include a field effect transistor Q3 and a resistor R11, where a gate of the field effect transistor Q3 may be connected to the processor MCU through the resistor R11, a drain of the field effect transistor Q3 may be connected to an enable terminal EN/PG of the controller U1, and may also be connected to a second power supply through the resistor R3, and a source of the field effect transistor Q3 is grounded. When the initial enabling signal smps_en sent by the processor MCU is at a high level, the field effect transistor Q3 is turned on, so that the drain electrode of the field effect transistor Q3 is directly grounded, and the output enabling signal hvnt_ndis is at a low level. When the initial enabling signal smps_en sent by the processor MCU is at a low level, the field effect transistor Q3 is turned off, the voltage at the drain of the field effect transistor Q3 is increased under the action of the resistor R3 and the second power supply, and the output enabling signal hvnt_ndis is at a high level.

Fig. 11 is a schematic diagram of a feedback circuit according to some embodiments of the present description.

In some embodiments, the power supply apparatus 100 may further include a feedback circuit for adjusting the operation state of the processing unit 120 according to the positive load power supply and the negative load power supply. In some embodiments, the feedback circuit may include a voltage sampling circuit for sampling output voltages of the positive load power supply and the negative load power supply to obtain a first sampled voltage and a second sampled voltage. In some embodiments, the feedback circuit may send the first sampled voltage and the second sampled voltage to the processor through the power supply monitoring module, thereby causing the processor to send a first enable signal to the enable terminal of the controller U1. The voltage sampling circuit, the power supply monitoring module and the processor can form a first feedback circuit. In some embodiments, the feedback circuit may obtain the second enable signal and the third enable signal by setting the comparing circuit to compare the magnitudes of the first sampling voltage and the second sampling voltage with the reference voltage, respectively, and transmitting the second enable signal and the third enable signal to the enable terminal of the controller U1. Wherein the voltage sampling circuit and the comparison circuit may constitute a second feedback circuit. In some embodiments, the first enable signal, the second enable signal, and the third enable signal may all be used to adjust the output of the processing unit 120.

When the first feedback circuit and the second feedback circuit coexist, the processing unit 120 may simultaneously receive the first enable signal, the second enable signal, and the third enable signal. Thus, in some embodiments, the processing unit 120 may determine a target enable signal based on the received first enable signal, the second enable signal, and the third enable signal to adjust the output based on the target enable signal.

In some embodiments, the processing unit 120 may process the first enable signal, the second enable signal, and the third enable signal according to and logic. That is, when the first, second, and third enable signals are all high, the target enable signal is high, and when any one of the first, second, and third enable signals is low, the target enable signal is low.

In some embodiments, the use of multiple feedback mechanisms (e.g., when the first feedback circuit and the second feedback circuit are present at the same time) may be effective to avoid inaccuracy of the output power supply caused by a single error.

Fig. 12A and 12B are schematic circuit configurations of voltage sampling circuits according to some embodiments of the present description.

In some embodiments, the voltage sampling circuit may be divided into a positive voltage sampling circuit and a negative voltage sampling circuit for sampling the positive load power supply and the negative load power supply, respectively.

Fig. 12A shows a forward voltage sampling circuit, and the input of the forward voltage sampling circuit is the connection point of the capacitor C7 and the capacitor C8 in the circuit shown in fig. 4, namely, the output end of the forward load power supply. In some embodiments, the connected forward load power +hv is grounded through resistors R4 and R5, and a capacitor C36 is connected in parallel across the resistor R5, where the junction of the resistors R4 and R5 is used to provide the first sampling voltage +hvmeans. The resistors R4 and R5 are used for dividing the voltage of the forward load power supply, so that a first sampling voltage +HVmeans with a lower voltage value is obtained. In some embodiments, the ratio of the resistance values of R4 and R5 may be set to adjust the range of the first sampling voltage.

As shown in fig. 12B, the input of the positive voltage sampling circuit is the connection point of the capacitor C10 and the capacitor C11 in the circuit shown in fig. 4, i.e. the output terminal of the negative load power supply. In some embodiments, the connected negative load power supply-HV is connected to the negative input of the operational amplifier U4 through resistors R6 and R7, and the output of the operational amplifier U4 provides the second sampling voltage-HVmeans through resistor R9. Meanwhile, the output end of the operational amplifier U4 is connected to the negative input end of the operational amplifier U4 through a resistor R8, and a capacitor C37 is connected in parallel to the two ends of the resistor R8. The positive input end of the operational amplifier U4 is grounded, the VDD port is connected to a fifth power supply, and the VSS port is grounded. The operational amplifier U4 and the resistors R6, R7 and R8 form a negative-direction proportional operational amplifier circuit, and negative power supply-HV is converted into positive voltage for sampling, so that a second sampling voltage-HVmeans is obtained. In some embodiments, the fifth power supply may be provided by a fifth power supply circuit similar to the second power supply circuit, and the fifth power supply may be a 5V dc power supply.

In some embodiments, the first and second sampled voltages +hvmeans may generate an enable signal through the first or second feedback circuits for adjusting the output of the processing unit 120. Specific implementations of the first feedback circuit or the second feedback circuit may be referred to in fig. 14A, 14B and fig. 13, and will not be described herein.

Fig. 13 is a schematic diagram of a power monitoring module according to some embodiments of the present disclosure.

In some embodiments, the first feedback circuit is configured to receive the positive load power supply, the negative load power supply, and the reference voltage, and output the positive load power supply, the negative load power supply, and the reference voltage to the processor, so that the processor sends a first enable signal to the processing unit 120, where the first enable signal is used to adjust the output of the processing unit 120.

In some embodiments, the first feedback circuit may include a power supply monitoring module through which the first sampled voltage and the second sampled voltage are sent to the processor, thereby causing the processor to send the first enable signal. In some embodiments, the power supply monitoring module may include an analog-to-digital converter ADC including at least three signal receiving channels for receiving the signal-processed first and second sampled voltages +hvmeans, HVmeans, and a reference voltage hvctrl_ref (V _REF ) And converting the voltage signal into a digital signal and outputting the digital signal to the processor MCU, thereby achieving the purpose of monitoring the voltage of the positive load power supply and the negative load power supply in real time.

In some embodiments, when the processing unit 120 is connected to the power supply, the driver U1 starts to operate, the processor MCU transmits an instruction to the driver U1 through the driving circuit, and after the driver U1 receives a driving signal consistent with the resonant frequency f, the resonant circuit and the rectifying and filtering circuit operate by controlling on and off of the switching elements Q1 and Q2, so that the voltage values of the positive load power +hv and the negative load power-HV of the output are continuously increased. In some embodiments, the voltage sampling circuit samples the positive load power supply +hv and the negative load power supply-HV to obtain a first sampled voltage +hvmeans and a second sampled voltage-HVmeans, and then converts the first sampled voltage +hvmeans, the second sampled voltage-HVmeans, and the reference voltage hvctrl_ref into digital signals (e.g., voltage values) through the analog-to-digital converter ADC for transmission to the processor MCU.

The processor MCU will compare the voltage value transmitted by the analog-to-digital converter ADC with a set threshold value. In some embodiments, when the voltage value transmitted by the analog-to-digital converter ADC exceeds a first threshold value V _TH1 When the processor MCU outputs the first enable signal HVNT_nDIS to the processing unit 120 as a low level ₁ When the enable end EN/PG of the driver U1 is connected, the driver U1 is disabled, the switching elements Q1 and Q2 are cut off, the resonant circuit stops working, and the voltage values of the positive load power supply and the negative load power supply are not increased any more. Exemplary, in connection with the switching circuit shown in FIG. 10, when the voltage value transmitted by the analog-to-digital converter ADC exceeds the first threshold value V _TH1 When the initial enable signal smps_en of the processor MCU is at a high level, the fet Q3 is turned on to directly ground the drain of the fet Q3, and the first enable signal hvnt_ndis is outputted ₁ Is low.

The voltage values of the positive load power supply and the negative load power supply may decrease due to load consumption or the like. In some embodiments, when the voltage value transmitted by the analog-to-digital converter ADC is less than the second threshold value V _TH2 When the first enable signal output from the processor MCU to the processing unit 120 is at a high level, the driver U1 is enabled, the switching elements Q1 and Q2 are turned on, and the resonant circuit is operated again, so that the voltage values of the positive load power supply and the negative load power supply continue to rise. Exemplary, in connection with the switching circuit shown in FIG. 10, when the voltage value transmitted by the analog-to-digital converter ADC exceeds the second threshold value V _TH2 When the initial enable signal smps_en of the processor MCU is low, the fet Q3 is turned off, and the first enable signal hvnt_ndis is output ₁ Is low.

The above operation is repeated when the voltage values of the positive load power supply and the negative load power supply continuously rise to a certain value, so that the positive load power supply and the negative load power supply reach dynamic balance and are kept within a certain range.

In some embodiments, to prevent frequent enablement of driver U1, a first threshold V _TH1 And a second threshold value V _TH2 Is not equal and the second threshold value V _TH2 Less than a first threshold V _TH1 . In one placeIn some embodiments, the first threshold V is set according to the high voltage source voltage value required by the load and the sensitivity to the source voltage _TH1 And a second threshold value V _TH2 。

Fig. 14A and 14B are schematic circuit configurations of a comparison circuit shown according to some embodiments of the present specification.

In some embodiments, the second feedback circuit may include a first comparison circuit and a second comparison circuit, wherein the first comparison circuit includes a first comparator U5, the first comparator U5 outputting a first comparison result according to the forward load power supply and the reference voltage; the second comparison circuit comprises a second comparator U6, and the second comparator U6 outputs a second comparison result according to the negative load power supply and the reference voltage.

In some embodiments, the second feedback circuit is configured to send the second enable signal and the third enable signal to the processing unit 120 according to the comparison result (i.e. the first comparison result and the second comparison result) of the sampling voltage of the positive load power supply and the sampling voltage of the negative load power supply with the reference voltage through the first comparator U5 and the second comparator U6, respectively, where the second enable signal and the third enable signal may be used to adjust the output of the processing unit 120.

In some embodiments, when the processing unit 120 is connected to the power supply, the driver U1 starts to operate, the processor MCU transmits an instruction to the driver U1 through the driving circuit, and after the driver U1 receives a driving signal consistent with the resonant frequency f, the resonant circuit and the rectifying and filtering circuit operate by controlling on and off of the switching elements Q1 and Q2, so that the voltage values of the output positive load power supply and the output negative load power supply are continuously increased. In some embodiments, the voltage sampling circuit samples the positive load power supply +hv and the negative load power supply-HV to obtain a first sampled voltage +hvmeans and a second sampled voltage-HVmeans, and then generates an enable signal to adjust the output of the processing unit 120 through the first comparison circuit and the second comparison circuit.

As shown in fig. 14A, the negative input terminal of the first comparator U5 is the first sampling voltage +hvmeans, and the positive input terminal of the first comparator U5 isThe input end is the reference voltage HVCTRL_REF, the VDD port is connected to the sixth power supply, the VSS port is grounded, and the output end is the second enable signal HVNT_nDIS ₂ Is connected to the enable EN/PG pin of the driver U1.

In some embodiments, when the first sampled voltage +HVmeans exceeds the reference voltage V _REF At this time, the second enable signal HVNT_nDIS outputted from the first comparator U5 ₂ At low level, the drive output pin UGATE of the driver U1 can be controlled to be disconnected from LGATE, and the switching elements Q1 and Q2 are turned off, so that the resonant circuit does not work, and the voltage of the forward load power supply does not increase any more. The voltage of the forward load power supply drops due to load consumption or the like. In some embodiments, the second enable signal HVNT_nDIS output by the first comparator U5 when the first sampling voltage +HVmeans exceeds the reference voltage HVCTRL_REF ₂ For high level, the driver U1 is enabled, the resonant circuit resumes operation, the voltage of the forward load power supply rises until reaching within a certain threshold, and finally a balance value is reached, so as to obtain the required output voltage value.

In some embodiments, the relationship between the forward load supply and the reference voltage may be expressed by the following equation (3):

+HV＝+HVmeans((R4+R5)/R5)＝V _REF ((R4+R5)/R5) (3)

wherein +HV is the voltage of the forward load power supply, +HVmeans is the first sampling voltage value, V _REF As reference voltage values, R4 and R5 are resistance values of resistors R4 and R5, respectively. In some embodiments, let r4=100 kΩ, r5=2.7kΩ, reference voltage V _REF The output is 1.8V, and the output voltage of the forward load power supply is 68.47V.

As shown in fig. 14B, the negative input end of the second comparator U6 is the second sampling voltage-HVmeans, the positive input end of the second comparator U6 is the reference voltage hvctrl_ref, the VDD port is connected to the sixth power supply, the VSS port is grounded, and the output end is the third enable signal hvnt_ndis ₃ Is connected to the enable EN/PG pin of the driver U1. Because the second sampling voltage-HVmeans is a positive voltage value, the working principle of the second comparison circuit and the working principle of the first comparison circuitSimilarly, by a second sampling voltage-HVmeans, and a reference voltage V _REF Is output by the comparison of the third enable signal HVNT_nDIS ₃ Thereby controlling the switch of the resonant circuit to obtain the required output voltage value.

In some embodiments, the output of the first comparison circuit and the output of the second comparison circuit may be connected together and then connected to the enable EN/PG pin of the driver U1. In some embodiments, when the first feedback circuit and the second feedback circuit coexist, the first enable signal HVNT_nDIS can be used for the control of the logic of the combining circuit ₁ Second enable signal HVNT_nDIS ₂ And a third enable signal HVNT_nDIS ₃ The generation target enable signal hvnt_ndis is re-sent to the enable terminal EN/PG of the driver U1 to control whether the resonant circuit operates.

In some embodiments, the second comparison circuit further comprises a hysteresis resistor R10 arranged between the output and the positive input of the second comparator U6 for adjusting the threshold voltage of said comparator. Because the voltage of the load energy storage capacitor can be reduced along with the consumption of the load, the charging current is constant, the capacitor can be charged and discharged intermittently, and the voltage is the integral of the charging current with respect to time, so that the control loop has 90-degree phase delay, and in order to improve the stability of the loop and reduce the recharging frequency, the second comparison circuit is also provided with a loop compensation circuit, and the loop compensation circuit is realized through R10. The detailed implementation is shown in the related description of fig. 16, and will not be repeated here.

Fig. 15 is a schematic diagram of a reference voltage generation scheme according to some embodiments of the present description.

In some embodiments, the power supply device further comprises a reference voltage circuit for providing an adjustable reference voltage to the first feedback circuit (i.e. the power supply monitoring module) and the second feedback circuit (including the first comparison circuit and the second comparison circuit), thereby achieving the effect of adjusting the output voltage.

The reference voltage circuit includes various implementations, for example, as shown in scheme 1 of fig. 15, the processor MCU controls and outputs a second driving signal smps_pwm2 with a certain frequency, and the second driving signal is a PWM waveform, and then is filtered to obtain a direct current reference voltage hvctrl_ref. As shown in scheme 2 of fig. 15, the processor MCU outputs a voltage of a certain value by controlling the DAC, and then obtains the reference voltage hvctrl_ref through filtering.

The specific implementation of the reference voltage circuit mainly considers whether the reference voltage value can be adjusted or not and the accuracy of the adjustment of the reference voltage value. For scheme 1, the dc voltage value obtained by filtering is proportional to the duty cycle of the second driving signal, so the accuracy of the adjustment of the reference voltage is mainly determined by the frequency of the second driving signal and the adjustable range of the duty cycle. For scheme 2, the accuracy of the output controlled by the digital-to-analog converter DAC to adjust the reference voltage depends on the number of bits of the digital-to-analog converter DAC.

Fig. 16 is a schematic circuit configuration diagram of a reference voltage circuit according to some embodiments of the present description. Fig. 16 shows the filter circuit of fig. 15 after the second driving signal smps_pwm2 is outputted by the control of the processor MCU in scheme 1.

In some embodiments, the second driving signal smps_pwm2 may be generated by a second driving circuit having a similar structure to the first driving circuit. The processor MCU is connected with the second driving circuit and sends out an instruction to the second driving circuit, and the second driving circuit generates a second driving signal SMPS_PWM2. In some embodiments, the second driving signal smps_pwm2 obtains the reference voltage hvctrl_ref through two-stage RC filtering.

As shown in fig. 16, one end of smps_pwm2 outputs a reference voltage V through R13, R14 and R15 connected in series _REF . The connection point between one end of the smps_pwm2 and the resistor R13 is grounded through the resistor R12, the connection point between R13 and R14 is grounded through the capacitor C34, and the connection point between R14 and R15 is grounded through the capacitor C35.

In some implementations, the second driving signal smps_pwm2 of different duty cycle or frequency may be obtained by the processor MCU outputting different instructions, so that the magnitude of the reference voltage hvctrl_ref may be adjusted.

As shown in fig. 4, 14B and 16, R10 is disposed between the output terminal and the positive input terminal of the second comparator U6, the output terminal of the second comparator U6 and the driver U1The enable terminal of the driver U1 is also connected to the second power supply via R3. Thus, R10 will be pulled up to the third power supply (e.g. 7V power supply) through R3, and since the positive input terminal of the second comparator U6 is connected to the reference voltage V of FIG. 15 _REF R10, R13, R14, R15 can form a voltage divider circuit, and the generated voltage is superimposed on the reference voltage V _REF On the signal, will thus be at the output HVNT_nDIS of the second comparator U6 ₂ A certain feedback hysteresis is generated, thereby improving the stability of the feedback loop. The hysteresis resistor R10 can ensure that the charging time interval required by the load during the period when no pulse is emitted is not too frequent, and can effectively reduce frequent switching of the driver U1 and the switching elements Q1 and Q2, reduce switching loss, and improve power supply efficiency.

In some embodiments, the voltage divider circuit adds the voltage to the reference voltage V by dividing _REF The voltage of the signal can be calculated by the following formula (4):

the voltage fluctuation fed back to the output terminal can be calculated by the following equation (5):

V _hys ＝V _div ((R4+R5)/R5) (5)

wherein V is _div Superimposed to the reference voltage V for voltage division _REF Voltage value at V _hys For feedback voltage fluctuation to the output terminal, R3, R4, R5, R10, R13, R14, and R15 are resistance values of the resistors R3, R4, R5, R10, R13, R14, and R15, respectively.

When the processing unit 120 starts to operate, the reference voltage V _REF Greater than the first sampling voltage +HVmeans, the driver U1 enables, the voltage of the forward load supply gradually increases, when the voltage increases to (V _REF +V _div )At the time, the second comparator U6 outputs a low level, V _div =0v, so the output voltage drops to (V _REF )/>When the comparator U6 outputs the high level again to enable the driver U1, the driver U1 controls the two switching elements Q1 and Q2 to be turned on, and the resonant circuit resumes operation. Thus, there will be a fixed V at the output voltage _hys The power supply fluctuation of the drive is reduced, the switching loss is reduced, the power supply efficiency is improved, and the phase compensation effect is also realized on the loop stability. In some embodiments, the filter capacitors C36, C37 in fig. 10 also function as loop compensation, improving the stability of the system.

In some embodiments, as shown in fig. 17, embodiments of the present application also provide a medical device 10, the medical device 10 may include a power supply 100 and a detector 200. In some embodiments, power supply 100 may provide positive and negative load power to detector 200 for detector 200 to operate. The specific implementation of the power supply device 100 can be seen from the above description of fig. 1 to 16, and will not be repeated here. In some embodiments, the detector 200 may be a detection device that uses positive and negative high voltage electrical energy to acquire signals, particles, e.g., a spectrum detector, a radiation detector, an ultrasound detector, etc. The specific implementation of the detector 200 may refer to the above description of the load, which is not repeated here.

The power supply device 100 may be used in a production scenario where signals such as pulses and lasers are generated using positive and negative high-voltage power, or in a detection scenario where signals, particles, and the like are collected using positive and negative high-voltage power. The specific application scenario of the power supply device 100 is not limited in this application.

Possible beneficial effects of embodiments of the present application include, but are not limited to: (1) The first power supply is converted into a positive load power supply and a negative load power supply through the processing unit, so that positive and negative power supplies can be output simultaneously; (2) By setting the resonance frequency f of the processing unit outside the effective frequency range [ a, b ] of the load, the signal processed by the power supply device during operation and the output electric energy are difficult to influence the normal operation of the load in the effective frequency range, so that the EMI of the power supply device to the load is reduced; (3) The resonant circuit is adopted for electric energy conversion, so that the current of the positive load power supply and the current of the negative load power supply can be stable; (4) The electric energy output by the resonant circuit is respectively processed by adopting the same rectifying and filtering mode through the symmetrical structure of the rectifying and filtering circuit, so that the symmetry of a positive load power supply and a negative load power supply is improved, and the generation of second harmonic wave to cause EMI to the load is avoided; (5) The stability of the positive and negative load power supply is effectively improved through the multi-feedback control method of the first feedback circuit and the second feedback circuit.

While the basic concepts have been described above, it will be apparent to those skilled in the art that the foregoing detailed disclosure is by way of example only and is not intended to be limiting. Although not explicitly described herein, various modifications, improvements, and adaptations to the present disclosure may occur to one skilled in the art. Such modifications, improvements, and modifications are intended to be suggested within this specification, and therefore, such modifications, improvements, and modifications are intended to be included within the spirit and scope of the exemplary embodiments of the present invention.

Meanwhile, the specification uses specific words to describe the embodiments of the specification. Reference to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic is associated with at least one embodiment of the present description. Thus, it should be emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various positions in this specification are not necessarily referring to the same embodiment. Furthermore, certain features, structures, or characteristics of one or more embodiments of the present description may be combined as suitable.

Furthermore, the order in which the elements and sequences are processed, the use of numerical letters, or other designations in the description are not intended to limit the order in which the processes and methods of the description are performed unless explicitly recited in the claims. While certain presently useful inventive embodiments have been discussed in the foregoing disclosure, by way of various examples, it is to be understood that such details are merely illustrative and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements included within the spirit and scope of the embodiments of the present disclosure. For example, while the system components described above may be implemented by hardware devices, they may also be implemented solely by software solutions, such as installing the described system on an existing server or mobile device.

Likewise, it should be noted that in order to simplify the presentation disclosed in this specification and thereby aid in understanding one or more inventive embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof. This method of disclosure, however, is not intended to imply that more features than are presented in the claims are required for the present description. Indeed, less than all of the features of a single embodiment disclosed above.

In some embodiments, numbers describing the components, number of attributes are used, it being understood that such numbers being used in the description of embodiments are modified in some examples by the modifier "about," approximately, "or" substantially. Unless otherwise indicated, "about," "approximately," or "substantially" indicate that the number allows for a 20% variation. Accordingly, in some embodiments, numerical parameters set forth in the specification and claims are approximations that may vary depending upon the desired properties sought to be obtained by the individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and employ a method for preserving the general number of digits. Although the numerical ranges and parameters set forth herein are approximations that may be employed in some embodiments to confirm the breadth of the range, in particular embodiments, the setting of such numerical values is as precise as possible.

Each patent, patent application publication, and other material, such as articles, books, specifications, publications, documents, etc., referred to in this specification is incorporated herein by reference in its entirety. Except for application history documents that are inconsistent or conflicting with the content of this specification, documents that are currently or later attached to this specification in which the broadest scope of the claims to this specification is limited are also. It is noted that, if the description, definition, and/or use of a term in an attached material in this specification does not conform to or conflict with what is described in this specification, the description, definition, and/or use of the term in this specification controls.

Finally, it should be understood that the embodiments described in this specification are merely illustrative of the principles of the embodiments of this specification. Other variations are possible within the scope of this description. Thus, by way of example, and not limitation, alternative configurations of embodiments of the present specification may be considered as consistent with the teachings of the present specification. Accordingly, the embodiments of the present specification are not limited to only the embodiments explicitly described and depicted in the present specification.

Claims

1. A power supply device (100), characterized by comprising: a power supply circuit (110) and a processing unit (120), wherein,

The power supply circuit (110) is connected with the electric energy input end of the processing unit (120), and the power supply circuit (110) provides a first power supply for the processing unit (120);

the positive voltage output end of the processing unit (120) provides a positive load power supply, and the negative voltage output end of the processing unit (120) provides a negative load power supply;

the switching frequency of the processing unit (120) is out of the effective frequency range of the load, the processing unit (120) comprises a resonant circuit and a rectifying and filtering circuit, the input end of the rectifying and filtering circuit is in circuit connection with the output end of the resonant circuit, the rectifying and filtering circuit is symmetrically arranged by taking the resonant circuit as a center, the first output end of the rectifying and filtering circuit provides the positive load power supply, and the second output end of the rectifying and filtering circuit provides the negative load power supply.

2. The power supply device (100) according to claim 1, wherein the switching frequency of the processing unit (120) comprises a resonance frequency of the resonance circuit, which resonance frequency is outside an effective frequency range of the load and outside an n-harmonic range of the effective frequency range, and/or which n-harmonic of the resonance frequency is outside the effective frequency range and outside an n-harmonic range of the effective frequency range.

3. The power supply device (100) of claim 2, wherein the resonant circuit comprises a resonant capacitor bank and a resonant inductance, the resonant capacitor bank comprising one or more resonant capacitors, the resonant capacitor bank being in series with the resonant inductance.

4. A power supply device (100) as claimed in claim 3, characterized in that the set of resonance capacitors comprises a first subset of resonance capacitors and a second subset of resonance capacitors, one end of the first subset of resonance capacitors being connected to one end of the second subset of resonance capacitors, the other end of the first subset of resonance capacitors being arranged to receive a bias voltage, the other end of the second subset of resonance capacitors being connected to ground.

5. The power supply device (100) of claim 1, wherein the degree of symmetry of the positive load power supply and the negative load power supply is within a preset symmetry range, and wherein the current of the positive load power supply and the current of the negative load power supply are within a preset current range.

6. The power supply device (100) according to any one of claims 3-5, wherein the resonant circuit further comprises a switching element and a driver (U1), the power input of the driver (U1) being connected to the power supply circuit (110), the driver (U1) being arranged to receive a drive signal and to control the switching element, the switching element being connected to the power supply circuit (110), the switching element being arranged to receive the first power supply;

The difference between the frequency of the driving signal and the resonant frequency is within a preset range.

7. A power supply device (100), characterized by comprising: a power supply circuit (110) and a processing unit (120), wherein,

wherein the switching frequency of the processing unit (120) is outside the effective frequency range of the load;

the power supply device (100) further comprises a first feedback circuit and a second feedback circuit, the second feedback circuit comprising a first comparator (U5) and a second comparator (U6), wherein,

the first comparator (U5) outputs a first comparison result according to the positive load power supply and a reference voltage, and the second comparator (U6) outputs a second comparison result according to the negative load power supply and the reference voltage;

the second feedback circuit sends a second enabling signal and a third enabling signal to the processing unit (120) according to the first comparison result and the second comparison result.

8. The power supply device (100) of claim 7, wherein the first feedback circuit is configured to receive the positive load power supply, the negative load power supply, and the reference voltage and output to a processor (MCU) to cause the processor (MCU) to send a first enable signal to the processing unit (120).

9. The power supply device (100) according to claim 7, wherein the power supply device (100) further comprises a hysteretic resistor (R10), the hysteretic resistor (R10) being arranged between the positive input of the second comparator (U6) and the output of the second comparator (U6).

10. A medical device (10), characterized by comprising: a detector (200) and a power supply device (100) according to any of claims 1-6 or 7-9, the power supply device (100) providing a positive load power supply and a negative load power supply to the detector (200).