CN114068699A - A non-volatile memory device based on topological insulator polarization and its preparation method - Google Patents
A non-volatile memory device based on topological insulator polarization and its preparation method Download PDFInfo
- Publication number
- CN114068699A CN114068699A CN202111309860.XA CN202111309860A CN114068699A CN 114068699 A CN114068699 A CN 114068699A CN 202111309860 A CN202111309860 A CN 202111309860A CN 114068699 A CN114068699 A CN 114068699A
- Authority
- CN
- China
- Prior art keywords
- topological insulator
- layer
- buried gate
- memory device
- polarization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000012212 insulator Substances 0.000 title claims abstract description 69
- 230000010287 polarization Effects 0.000 title claims abstract description 32
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000003860 storage Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 15
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 9
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910002899 Bi2Te3 Inorganic materials 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052593 corundum Inorganic materials 0.000 claims description 5
- 229910052961 molybdenite Inorganic materials 0.000 claims description 5
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000000572 ellipsometry Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明公开一种基于拓扑绝缘体极化的非易失性存储器件及其制备方法。该基于拓扑绝缘体极化的非易失性存储器件包括：衬底；埋栅，形成在所述衬底中，其上表面与所述衬底上表面持平；第一高K介质层/拓扑绝缘体层/第二高K介质层叠层，覆盖所述埋栅，其中，所述拓扑绝缘体层封装于两层高K介质层之间，且所述拓扑绝缘体层长度与所述埋栅长度相当；二维沟道层，形成在所述第二高K介质层上，完全覆盖所述拓扑绝缘体层；源电极和漏电极，分别形成在所述衬底上、所述二维沟道层两侧，并部分覆盖所述二维沟道层，且与所述埋栅无重叠，其中，基于所述拓扑绝缘体层的极化反转实现非易失性存储。
The invention discloses a non-volatile memory device based on topological insulator polarization and a preparation method thereof. The non-volatile memory device based on topological insulator polarization includes: a substrate; a buried gate formed in the substrate, the upper surface of which is flush with the upper surface of the substrate; a first high-K dielectric layer/topological insulator layer/a second high-K dielectric stack layer covering the buried gate, wherein the topological insulator layer is encapsulated between two high-K dielectric layers, and the length of the topological insulator layer is equivalent to the length of the buried gate; two A two-dimensional channel layer is formed on the second high-K dielectric layer and completely covers the topological insulator layer; a source electrode and a drain electrode are respectively formed on the substrate and on both sides of the two-dimensional channel layer, and partially cover the two-dimensional channel layer without overlapping with the buried gate, wherein non-volatile storage is realized based on the polarization inversion of the topological insulator layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a nonvolatile memory device based on topological insulator polarization and a preparation method thereof.
Background
With the continuous development of integrated circuits, high-speed, high-density, and novel electrically accessible non-volatile memories (NVM) have been recognized as the key to the development of future information technology. Existing NVMs include molecular, random access, flash and ferroelectric NVMs, of which ferroelectric NVMs are of great interest for their low power consumption, high write-erase speed and high endurance performance. However, there are several obstacles to commercialization of perovskite ferroelectric NVM, such as low storage density, high integration cost, etc.;
a Topological Insulator (TI) is a material that is an insulator (or semiconductor) in the bulk, with the surface protected in the metallic state by time-reversal symmetry. Due to the quantum confinement effect of the TI material sub-surface, a two-dimensional electron gas (2DEG) is formed on the surface, making the surface band-gap-free. The electrons in the 2DEG can be viewed as a mass-free dirac fermi. Therefore, the electrons of the TI surface have higher mobility and response speed. However, there is currently little research on the polarization of TI materials and their application to memory.
Disclosure of Invention
The invention discloses a nonvolatile memory device based on topological insulator polarization, which comprises: a substrate; the buried gate is formed in the substrate, and the upper surface of the buried gate is flush with the upper surface of the substrate; the first high-K dielectric layer/topological insulator layer/second high-K dielectric layer lamination covers the buried gate, wherein the topological insulator layer is packaged between the two high-K dielectric layers, and the length of the topological insulator layer is equivalent to that of the buried gate; a two-dimensional channel layer formed on the second high-K dielectric layer, completely covering the topological insulator layer; and the source electrode and the drain electrode are respectively formed on the substrate and two sides of the two-dimensional channel layer, partially cover the two-dimensional channel layer and are not overlapped with the buried gate, and nonvolatile storage is realized based on polarization inversion of the topological insulator layer.
In the nonvolatile memory device based on the topological insulator polarization according to the present invention, preferably, the topological insulator layer is Bi2Se3Or Bi2Te3。
In the topological insulator polarization based nonvolatile memory device of the present invention, preferably, the first high-K dielectric layer and the second high-K dielectric layer are formed of a single dielectric materialThe K dielectric layer is BN or Al2O3、HfO2Or ZrO2。
In the non-volatile memory device based on topological insulator polarization according to the present invention, preferably, the two-dimensional channel layer MoS2Or WS2。
The invention also discloses a preparation method of the nonvolatile memory device based on the topological insulator polarization, which comprises the following steps: forming a buried gate in the substrate to enable the upper surface of the buried gate to be flush with the upper surface of the substrate; forming a first high-K dielectric layer on the buried gate, wherein the first high-K dielectric layer covers the buried gate; forming a topological insulator layer on the first high-K dielectric layer, wherein the length of the topological insulator layer is equivalent to that of the buried gate; forming a second high-K dielectric layer on the topological insulator layer, covering the topological insulator layer; forming a two-dimensional channel layer on the second high-K dielectric layer, which completely covers the topological insulator layer; and forming a source electrode and a drain electrode on the substrate and on two sides of the two-dimensional channel layer, wherein the source electrode and the drain electrode respectively partially cover the two-dimensional channel layer and are not overlapped with the buried gate, and nonvolatile storage is realized based on polarization inversion of the topological insulator layer.
In the method for manufacturing a non-volatile memory device based on topological insulator polarization, preferably, the third-generation topological insulator layer is Bi2Se3Or Bi2Te3。
In the method for manufacturing the nonvolatile memory device based on the topological insulator polarization, the first high-K dielectric layer and the second high-K dielectric layer are preferably BN and Al2O3、HfO2Or ZrO2。
In the method for manufacturing the non-volatile memory device based on the topological insulator polarization, preferably, the two-dimensional channel layer MoS2Or WS2。
Drawings
Fig. 1 is a flow chart of a method for fabricating a non-volatile memory device based on topological insulator polarization.
Fig. 2 is a schematic diagram of the device structure after forming the buried gate.
Fig. 3 is a schematic diagram of the device structure after forming the high-K dielectric layer/topological insulator layer/high-K dielectric layer.
Fig. 4 is a schematic view of a device structure after forming a two-dimensional channel layer.
Fig. 5 is a schematic view of the device structure after forming the source and drain electrodes.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
Fig. 1 is a flow chart of a method for fabricating a non-volatile memory device based on topological insulator polarization. As shown in fig. 1, the method comprises the following steps:
step S1, cleaning the Si100/SiO 2101 Substrate (SiO)2 Layer 101 thickness 285nm) and a series of 160 μm by 160 μm gate electrode (pad) patterns were lithographed; then, the SiO is etched by Reactive Ion Etching (RIE)2101 and the etching gas is CHF3The volume flow rate is 30sccm, the pressure is 1.3Pa, the RF power is 90W, and the etching rate is 20 nm/min; the etching process was continued for 4min15s, and then 85nm trenches were obtained. Ellipsometry measurements were performed with the coupons with errors within 2 nm. Next, Ti/Pt is deposited to form a buried gate 102 having an upper surface that is level with the upper surface of the substrate, and the resulting structure is shown in FIG. 2. Wherein the thickness of the Ti layer is 15nm, and the thickness of the Pt layer is 70 nm.
Step S2, depositing a first high-K dielectric HfO with a thickness of 30nm on a substrate at 300 ℃ by using an Atomic Layer Deposition (ALD) method 2103. First high-K dielectric HfO2103 completely cover the buried gate 102. Then, a mechanical stripping method is adopted to remove the two-dimensional topological insulator Bi2Se3104 to the first high-K dielectric HfO 2103 and making Bi2Se3104 in horizontal projection is within the range of the buried gate 102, and Bi2Se3104 are of a length comparable to the length of the buried gate 102. Next, a second high-K dielectric HfO with a thickness of 30nm was again deposited by ALD at 300 deg.C 2105, covering it with Bi2Se3104, the resulting structure is shown in fig. 3.
Step S5, adopting a mechanical stripping method to remove the MoS of the two-dimensional material 2106 are transferred to the second high-K dielectric 105 as a channel. The two-dimensional material 106 is sized and positioned to completely cover the topological insulator Bi2Se3104, and the resulting structure is shown in fig. 4.
In step S6, the source and drain regions are patterned by electron beam lithography, and then Ti/Au with a thickness of 15 nm/70 nm is deposited as the source electrode 107 and the drain electrode 108 by Physical Vapor Deposition (PVD), and the resulting structure is shown in fig. 5. A source electrode 107 and a drain electrode 108 formed on the substrate respectivelySeparately covering MoS 2106 and has no overlap with the projection of the buried gate 102 in the horizontal plane direction.
As shown in FIG. 5, the non-volatile memory device based on topological insulator polarization comprises a substrate of Si100/SiO 2101, a first electrode and a second electrode; a buried gate 102 formed in the substrate, the upper surface of which is flush with the upper surface of the substrate; the first high-K dielectric layer 103, the topological insulator layer 104 and the second high-K dielectric layer 105 are stacked to cover the buried gate 102, wherein the topological insulator layer 104 is packaged between the two high-K dielectric layers, the projection of the topological insulator layer 104 on the horizontal plane is positioned in the range of the buried gate 102, and the length of the topological insulator layer 104 is equivalent to that of the buried gate; a two-dimensional channel layer 106 formed on the second high-K dielectric layer 105 and completely covering the topological insulator layer 104; and a source electrode 107 and a drain electrode 108 which are respectively formed on the substrate and on both sides of the two-dimensional channel layer 106, and partially cover the two-dimensional channel layer 106 without overlapping the buried gate 102. Non-volatile storage is achieved based on polarization reversal of the topological insulator material by integrating the topological insulator material in the gate dielectric stack structure.
Although the back-gate structured nonvolatile memory device based on topological insulator polarization has been described as an example, the present invention is not limited thereto, and may be a top-gate structure. Furthermore, the topological insulator can also be Bi2Te3The high-K dielectric layer can also be BN or Al2O3、ZrO2Etc., the two-dimensional channel layer may also be WS2。
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (8)
1. A non-volatile memory device based on topological insulator polarization,
the method comprises the following steps:
a substrate;
the buried gate is formed in the substrate, and the upper surface of the buried gate is flush with the upper surface of the substrate;
the first high-K dielectric layer/topological insulator layer/second high-K dielectric layer lamination covers the buried gate, wherein the topological insulator layer is packaged between the two high-K dielectric layers, and the length of the topological insulator layer is equivalent to that of the buried gate;
a two-dimensional channel layer formed on the second high-K dielectric layer, completely covering the topological insulator layer;
a source electrode and a drain electrode respectively formed on the substrate and on both sides of the two-dimensional channel layer, and partially covering the two-dimensional channel layer without overlapping the buried gate,
wherein non-volatile storage is achieved based on polarization reversal of the topological insulator layer.
2. The topological insulator polarization based nonvolatile memory device of claim 1,
the topological insulator layer is Bi2Se3Or Bi2Te3。
3. The topological insulator polarization based nonvolatile memory device of claim 1,
the first high-K dielectric layer and the second high-K dielectric layer are BN and Al2O3、HfO2Or ZrO2。
4. The topological insulator polarization based nonvolatile memory device of claim 1,
the two-dimensional channel layer MoS2Or WS2。
5. A method for preparing a nonvolatile memory device based on topological insulator polarization is characterized in that,
the method comprises the following steps:
forming a buried gate in the substrate to enable the upper surface of the buried gate to be flush with the upper surface of the substrate;
forming a first high-K dielectric layer on the buried gate, wherein the first high-K dielectric layer covers the buried gate;
forming a topological insulator layer on the first high-K dielectric layer, wherein the length of the topological insulator layer is equivalent to that of the buried gate;
forming a second high-K dielectric layer on the topological insulator layer, covering the topological insulator layer;
forming a two-dimensional channel layer on the second high-K dielectric layer, which completely covers the topological insulator layer;
forming a source electrode and a drain electrode on the substrate and on two sides of the two-dimensional channel layer, wherein the source electrode and the drain electrode respectively partially cover the two-dimensional channel layer and are not overlapped with the buried gate,
wherein non-volatile storage is achieved based on polarization reversal of the topological insulator layer.
6. The method of fabricating a topological insulator polarization based nonvolatile memory device as in claim 5,
the third generation topological insulator layer is Bi2Se3Or Bi2Te3。
7. The method of fabricating a topological insulator polarization based nonvolatile memory device as in claim 5,
the first high-K dielectric layer and the second high-K dielectric layer are BN and Al2O3、HfO2Or ZrO2。
8. The method of fabricating a topological insulator polarization based nonvolatile memory device as in claim 5,
the two-dimensional channel layer MoS2Or WS2。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111309860.XA CN114068699B (en) | 2021-11-07 | 2021-11-07 | Non-volatile memory device based on topological insulator polarization and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111309860.XA CN114068699B (en) | 2021-11-07 | 2021-11-07 | Non-volatile memory device based on topological insulator polarization and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114068699A true CN114068699A (en) | 2022-02-18 |
| CN114068699B CN114068699B (en) | 2023-08-22 |
Family
ID=80274676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111309860.XA Active CN114068699B (en) | 2021-11-07 | 2021-11-07 | Non-volatile memory device based on topological insulator polarization and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114068699B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120273763A1 (en) * | 2011-04-29 | 2012-11-01 | Banerjee Sanjay K | Topological Insulator-Based Field-Effect Transistor |
| KR20190077917A (en) * | 2017-12-26 | 2019-07-04 | 한국과학기술원 | Low power nonvolatile memory device comprising 2d material semiconductor channel and polymer tunneling insulator and fabricating method |
| US20200194596A1 (en) * | 2018-12-14 | 2020-06-18 | Korea Advanced Institute Of Science And Technology | Thin film transistor comprising two dimensional material, display comprising the same and manufacturing method for the same |
| WO2021037335A1 (en) * | 2019-08-26 | 2021-03-04 | National Center For Scientific Research Demokritos | A negative quantum capacitance field effect transistor |
| CN113363317A (en) * | 2021-06-06 | 2021-09-07 | 复旦大学 | Negative quantum capacitor device and preparation method thereof |
| CN113363316A (en) * | 2021-06-06 | 2021-09-07 | 复旦大学 | Two-dimensional negative quantum capacitor transistor device and preparation method thereof |
-
2021
- 2021-11-07 CN CN202111309860.XA patent/CN114068699B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120273763A1 (en) * | 2011-04-29 | 2012-11-01 | Banerjee Sanjay K | Topological Insulator-Based Field-Effect Transistor |
| KR20190077917A (en) * | 2017-12-26 | 2019-07-04 | 한국과학기술원 | Low power nonvolatile memory device comprising 2d material semiconductor channel and polymer tunneling insulator and fabricating method |
| US20200194596A1 (en) * | 2018-12-14 | 2020-06-18 | Korea Advanced Institute Of Science And Technology | Thin film transistor comprising two dimensional material, display comprising the same and manufacturing method for the same |
| WO2021037335A1 (en) * | 2019-08-26 | 2021-03-04 | National Center For Scientific Research Demokritos | A negative quantum capacitance field effect transistor |
| CN113363317A (en) * | 2021-06-06 | 2021-09-07 | 复旦大学 | Negative quantum capacitor device and preparation method thereof |
| CN113363316A (en) * | 2021-06-06 | 2021-09-07 | 复旦大学 | Two-dimensional negative quantum capacitor transistor device and preparation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| ZHU HAO: "Novel non-volatile memory and topological insulator field-effect transistors", 《GEORGE MASON UNIVERSITY PROQUEST DISSERTATIONS 》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114068699B (en) | 2023-08-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10957711B2 (en) | Ferroelectric device with multiple polarization states and method of making the same | |
| CN100379002C (en) | Non-volatile semiconductor memory device | |
| TWI351756B (en) | Charge trapping devices with field distribution la | |
| US9236391B2 (en) | Method of forming split-gate cell for non-volative memory devices | |
| US20220336529A1 (en) | Novel hard mask for mtj patterning | |
| CN106098926A (en) | Three layers of Josephson's junction structure and forming method thereof | |
| US8125824B1 (en) | Nanotube random access memory (NRAM) and transistor integration | |
| US9203015B2 (en) | Magnetic storage device | |
| US7821821B2 (en) | Multibit electro-mechanical device and method of manufacturing the same | |
| US9054209B2 (en) | Compact charge trap multi-time programmable memory | |
| CN111627920A (en) | Ferroelectric memory cell | |
| JP2015167200A (en) | Non-volatile semiconductor storage device | |
| CN113035883A (en) | Three-dimensional memory and manufacturing method thereof | |
| CN110676260A (en) | Three-dimensional memory and forming method thereof | |
| US8264026B2 (en) | Nonvolatile memory devices and methods of manufacturing the same | |
| CN114068699A (en) | A non-volatile memory device based on topological insulator polarization and its preparation method | |
| CN114050163A (en) | Topological insulator nonvolatile memory device and preparation method thereof | |
| CN113363316B (en) | A two-dimensional negative quantum capacitor transistor device and preparation method thereof | |
| CN111446254A (en) | Semi-floating gate memory based on metal oxide semiconductor and preparation method thereof | |
| CN103390589B (en) | NOR structure flash memory and preparation method thereof | |
| WO2022000344A1 (en) | Memory and manufacturing method therefor | |
| CN113363384A (en) | HfO2Ferroelectric tunnel junction device and method for manufacturing the same | |
| CN114762117A (en) | Ferroelectric memory device containing two-dimensional charge carrier channel and method of fabricating the same | |
| US20240032300A1 (en) | 3d lateral patterning via selective deposition for ferroelectric devices | |
| US20230127162A1 (en) | Non-volatile memory device and operating method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |