CN114068520A - 半导体装置和半导体装置的制造方法 - Google Patents

半导体装置和半导体装置的制造方法 Download PDF

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CN114068520A
CN114068520A CN202110894943.3A CN202110894943A CN114068520A CN 114068520 A CN114068520 A CN 114068520A CN 202110894943 A CN202110894943 A CN 202110894943A CN 114068520 A CN114068520 A CN 114068520A
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汉斯-马丁·里特
斯特芬·霍兰
吉多·诺特曼斯
约阿希姆·乌茨格
纳加拉杰·瓦桑莎·库马尔·瓦达基雷
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Nexperia BV
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Abstract

本公开涉及一种半导体装置，包括：第一n+区域；第一p+区域，其位于第一n+区域内；第二n+区域；第二p+区域，其位于第一n+区域与第二n+区域之间。第一n+区域、第二n+区域和第二p+区域位于p‑区域内。第一空间电荷区域和第二空间电荷区域形成在p‑区域内。第一空间区域位于第一n+区域与第二p+区域之间，第二空间区域位于第二p+区域与第二n+区域之间。

Description

半导体装置和半导体装置的制造方法
技术领域
本发明涉及一种半导体装置。本发明还涉及一直制造半导体装置的方法。
背景技术
众所周知，静电放电(ESD)保护装置需要同时具有低电容、快速开启和低钳位电压。
大电容将妨碍数据传输。缓慢开启将意味着要保护的集成电路(IC)将必须经受住应力脉冲的第一部分。高钳位电压可能损坏要保护的装置。
已知的基于硅控整流器(SCR)的装置可能由于SCR中可能有非常深的快速回弹而具有非常低的钳位电压。
基于SCR的装置中的低电容可以通过使用低掺杂区域来实现，该低掺杂区域可以通过相邻结从载流子中耗尽：掺杂水平越低，耗尽区域越厚，电容越低。
SCR中的导通时间也取决于低掺杂区域的厚度。低掺杂区域越薄，切换(从隔离状态到导通状态的切换)越快。
可能无法同时实现快速切换和低电容。低掺杂区域随后将同时变薄和变厚。
一种解决方案可以是使用低掺杂区域，其目标是低电容，并避免在耗尽层一侧使用抗冲孔层进行穿通。
如图1a、图1b和图1c中所示，一种解决方案是在右侧外n+区域102旁边使用更高掺杂的p+型层100。p-区域104将被耗尽，并且由于耗尽层106而将给出低电容。
然而，使用这种方法，由于只有一个区域106具有低电容，因此在所需电容(厚低掺杂层)与所需切换时间(薄低掺杂层)之间存在冲突。
本领域中已知的实施抗冲孔层的另一种方式是将内部n-扩散放置在深p阱中，如图1d中所示。
发明内容
各种示例实施例针对如上所述的缺点和/或从以下公开中可以变得明显的其它缺点。
根据本发明的实施例，半导体装置包括：第一n+区域；第一p+区域，其位于第一n+区域内；第二n+区域；以及第二p+区域，其位于第一n+区域与第二n+区域之间。第一n+区域、第二n+区域和第二p+区域位于p-区域内。第一空间电荷区域和第二空间电荷区域形成在p-区域内。第一空间区域位于第一n+区域与第二p+区域之间，并且第二空间区域位于第二p+区域与第二n+区域之间。
以这种方式，基于SCR的ESD保护装置提供有串联的两个低电容区域。低电容区域位于一个掺杂区域内，并通过抗冲孔区域彼此分离，抗冲孔区域是具有较高掺杂水平的区域。
根据本发明的装置具有串联的两个低电容区域(两个厚耗尽层)。低电容区域通过抗冲孔区域彼此分离，抗冲孔区域是具有较高掺杂水平的区域。
由于导通时间非线性地取决于低掺杂区域的厚度，因此厚度减半的两个低掺杂区域的导通时间将比一个全厚度的低掺杂区域的导通时间短。电容线性地取决于耗尽区的反厚度(inverse thickness)；因此，厚度减半的两个耗尽区(串联)将与一个全厚度区域具有相同的低电容。
以这种方式，可以在一个装置中实现低电容和低导通时间。
p-区可以是低掺杂外延层。
第一空间区域和第二空间区域优选为2μm至3μm宽。
根据本发明的实施例，电隔离层布置在半导体装置的底部。
电隔离层可以为：
埋置p层，或者
埋置n层，或者
埋置p层和埋置n层，或者
埋置氧化物，或者
任意其它合适的隔离布置。
根据本发明的实施例，半导体装置还包括侧部电隔离层。
侧部电隔离层可以为沟槽或者一组深扩散部。
根据本发明的实施例，半导体装置包括用于将触发电流注入到半导体装置中的触发连接。触发电流由触发电流源提供。
触发连接可以为位于第一n+区域与第二p+区域之间的触发带。
根据本发明的实施例，半导体装置具有浮置基极和阳极，触发电流源连接在浮置基极与阳极之间。
触发电流源被实现为：
二极管串，二极管串包括至少1个二极管，或者
雪崩二极管，其具有6V至20V之间的范围内的击穿电压，或者
双极结型晶体管，或者
开路基极双极结型晶体管，或者
金属氧化物硅(MOS)晶体管，或者
以二极管配置的MOS晶体管，或者
任意其它合适的触发连接。
触发电流源可以被实现为具有6V以下的触发电压和4V以下的快速回弹电压的开路基极晶体管。
根据本发明的实施例，如以上实施例中描述的半导体装置可以被布置为多指布置。
根据本发明的实施例，一种第二半导体装置，其中如以上实施例中描述的半导体装置的结构被重复至少2次，使得第二半导体装置为双向装置。
本发明还涉及一种制造如以上实施例中描述的半导体装置的方法。
本发明使用用于降低电容的两个串联空间电荷区域。两个耗尽区域通过抗冲孔层彼此分离，抗冲孔层为限制耗尽区域的更高掺杂的薄层。抗冲孔层放置在两个耗尽区域之间。通过使用两个独立的耗尽层，可以实现低电容和快速切换两者。
在本发明的实施例中，高掺杂区域在与相邻的发射极区域和集电极区域等距的低掺杂基极区域内使用。这允许结合低电容和低泄漏，因为穿通被更高的掺杂抑制。
另一种可能性是省去更高掺杂的基极区域。然后基极宽度必须很大，这意味着发射极集电极空间必须非常大，尤其是在考虑与低掺杂连接的不可避免的工艺变化时。大的距离将导致高过冲和高导通电阻，这都是不希望的。
另一种可能性是使用沟槽或模具代替高掺杂区域。这将避免穿通，因为空间区域被缺失的硅分离。SCR内的电流必须围绕沟槽或模具流动，使得过冲和钳位电压两者将更高。
附图说明
为了可以详细地理解本公开的特征的方式，参照其中一些在附图中示出的实施例进行了更具体的描述。然而，要注意，附图仅示出了典型的实施例，因此不应被认为是对其范围的限制。附图用于促进对本公开的理解，因此不一定按比例绘制。结合附图阅读本说明书之后，所要求保护的主题的优点对于本领域技术人员将变得显而易见，
在附图中，同样的附图标记用于表示同样的元件，并且在附图中：
图1a、图1b、图1c和图1d示出本领域已知的装置；
图2a、图2b、图2c和图2d示出根据本发明的实施例的半导体装置；
图3a、图3b、图3c、图3d、图3e和图3f示出根据本发明的实施例的半导体装置；
图4示出根据本发明的实施例的半导体装置；
图5示出根据本发明的实施例的半导体装置；
图6示出根据本发明的实施例的半导体装置；
图7a和图7b示出根据本发明的实施例的半导体装置；
图8a和图8b示出根据本发明的实施例的半导体装置；
图9示出根据本发明的实施例的半导体装置；
图10示出根据本发明的实施例的半导体装置；
图11示出根据本发明的实施例的半导体装置；
图12示出根据本发明的实施例的半导体装置；
图13示出根据本发明的实施例的半导体装置；
图14示出根据本发明的实施例的半导体装置；
图15示出根据本发明的实施例的半导体装置以及相关电流-电压图；
图16示出根据本发明的实施例的半导体装置的电流-电压图；
图17a、图17b和图17c示出根据本发明的实施例的半导体装置。
具体实施方式
图2a、图2b、图2c和图2d中示出了本发明的实施例。
根据本实施例的半导体装置包括：
第一n+区域200，
第一p+区域202，其位于第一n+区域200内，
第二n+区域204，
第二p+区域206，其设置在第一n+区域200与第二n+区域204之间，
其中，第一n+区域200、第二n+区域204和第二p+区域206设置在p-区域208内。
半导体为由两个耦合的晶体管组成的SCR。pnp晶体管由第一p+区域202、第一n+区域200和包括第二p+区域206的p-区域208形成。npn晶体管由第二n+区域204、p-区域208和第一n+区域200形成。
以这种方式，两个空间电荷区域形成在p-区域208内：第一空间电荷区域210和第二空间电荷区域212。这两个空间电荷区域也被称作耗尽区域。
第二p+区域206保持浮置。其由夹在两个低掺杂层(p-区域208)之间的高掺杂p+层组成。第二p+区域206有助于避免穿通，低掺杂层优选在工作电压下耗尽(第一空间电荷区域210和第二空间电荷区域212)，并且降低SCR的电容。
图2d中示出了从该实施例产生的电容的示意图。
第一电容214为由第一p+/n+结形成的大电容，第一p+/n+结形成在第一n+区域200与第一p+区域202之间。其被电阻器216旁路。
第二电容218和第三电容220为相对小的电容，并且它们对应于两个空间电荷区域或耗尽区域(第一空间电荷区域210和第二空间电荷区域212)。这两个电容相对小，因为空间电荷区域较厚，例如，在几μm的范围内。
该布置的总电容为耗尽层之一的电容的一半，即，第二电容218的一半或第三电容220的一半。
图2a、图2b、图2c和图2d中所示的实施例只是形成这两个低电容耗尽层的可能性之一。本发明不限于图2a、图2b、图2c和图2d中所示的实施例。
如图3b中所示，浮置基极还可以为pnp的n掺杂基极，而不是npn的p掺杂基极，如图3a中所示。
此外，低掺杂区域可以为n掺杂或p掺杂，如图3c和图3d中所示。
低掺杂区域甚至可以为n掺杂层和p掺杂层的夹层，如图3e和图3f中所示。
许多其它实施例(即，组合)是可能的。
图4中示出了本发明的实施例。在该实施例中，半导体装置包括触发连接230。这种触发连接230限定击穿电压(BV)。
半导体装置包括：
触发连接230，
第一n+区域232，
第一p+区域234，其位于第一n+区域内，
第二n+区域236，
第二p+区域238，其设置在第一n+区域232与第二n+区域236之间，
其中，第一n+区域232、第二n+区域236和第二p+区域238设置在p-区域240内。
在限定的BV处，触发连接将注入电流，因此正向偏置右np结。注入的电子将在左侧n阱处收集并导致该阱中的电压降，最终将正向偏置左pn结并启动SCR的传导模式。
以这种方式，存在具有串联的两个低电容结(即，两个厚耗尽层)的SCR。即，两个n阱(第一n+区域和第二n+区域)放置在低掺杂外延层(p-区域)中，使得耗尽层可以扩展得很宽，例如在2μm至3μm的范围内。同时，两个n阱之间的距离必须足够小，因为长距离将导致高过冲电压和大导通电阻。如果两个结彼此靠得太近，则可能发生两个耗尽层合并，从而导致不想要的泄漏电流(所谓的穿通)。
图5中示出了本发明的实施例。在该实施例中，更高掺杂的抗冲孔层可以围绕所有侧的n-区域。这可以用埋置层250来实现。埋置层250可以是p型。
图6中示出了本发明的实施例。在此情况下，半导体装置包括两个埋置层：第一埋置层250和第二埋置层252。第一埋置层250可以是p型，第二埋置层252可以是n型。这两个埋置层额外地将SCR与载体衬底隔离。
图7a和图7b中示出了本发明的实施例。在此情况下，用埋置氧化物260将SCR与载体衬底隔离。埋置氧化物260可以基于绝缘体上硅(SOI)技术。图7b中所示的实施例包括接触第一n区域262的埋置氧化物260。
图8a和图8b中示出了本发明的实施例。在这些实施例中，提供了侧壁隔离。这可以通过第一侧壁隔离290和第二侧壁隔离292来实施。侧壁隔离290、292可以实施为沟槽或扩散部。
图8a中所示的实施例示出了包括第一埋置层294和第二埋置层296的半导体装置，第二埋置层296设置在第一埋置层294下方。
图8b中所示的实施例示出了包括埋置氧化物298的半导体装置。
先前的实施例涉及一种单向SCR。然而，本发明还涉及一种两个方向/双向SCR。双向SCR针对两种极性的行为都相似。实现双向SCR的一种可能性是复制单向SCR的整个结构并通过横向移位将其粘贴。
双向概念可以很容易地扩展到具有许多并联SCR的多指阵列结构。图9中示出了本发明的实施例。
在图10中所示的本发明的实施例中，示出了半导体装置的对称性，其解释了以上提及的多指结构布置。
无论引脚1(图9中的附图标记310)具有正电压(图10中的附图标记314)还是引脚2(图9中的附图标记312)具有正电压(图10中的附图标记316)，电流始终向右。
如图11中所示，在引脚1处用于正电压和负电压的电流路径不重叠，因为它们在半导体装置中放置在单独的位置。此外，电流方向针对两个极性是相同的。
这可以描述为横向对称。如果半导体装置将在横向方向上以固定节距移动，则其在那里将是相同的。
图11中示出了本发明的实施例。这是多指结构布置，其具有埋置隔离和触发注入，如图12中所示。
在本发明的实施例中，如图13中所示，可以使用本地触发带330代替触发连接(如图4中所示，具有附图标记230)。
具有本地触发带的该半导体装置可以与隔离方法结合，如以上实施例中所描述的，并且还可以以多指布置来布置。
触发带与n阱之间的击穿电压可以被定制为实际电压目标。
图14中的本发明的实施例中示出了多指布置的触发带330。
触发电流由开路基极结构提供。该npn晶体管具有浮置基极。击穿电压远低于6伏，尽管如此，触发具有低泄漏电流。因此，SCR将具有6伏以下的触发电压。
为了保持小的寄生电容，触发装置必须小。但是其必须足够大以能够传输必要的触发电流。
图15中示出了这种半导体装置的截面。如图15中所示，低于6V始终不存在泄漏。触发电压远低于6V，即，2V至3V。
击穿电压通过专用的p阱扩散进行微调。
布局将针对触发电流和低寄生电容下的低电压的最佳组合进行优化。
以这种方式，可以构建晶体管，使得在低电流电平下增益很大。对于这种开路基极晶体管，在低电流电平下达到快速回弹电压。快速回弹可以大大减少。
图16中示出了根据本发明实施例的开路基极晶体管340与正常开路基极晶体管342之间的电流-电压依赖性的差异。
根据本发明实施例的开路基极晶体管具有以下优点：其可以达到低至2V至4V的击穿电压并且仍然具有非常低的泄漏电流。
能够优化这种开路基极晶体管，使得在低电流电平下实现大电流增益，而没有快速回弹，基极集电极结阱的击穿电压远在7V以上，并且该结的泄漏非常低。
图17a、图17b和图17c中示出了用于开路基极晶体管的本发明的三个示例性实施例。
垂直晶体管如图17a中所示。此处增益在低电流时很高，因为基极与集电极的尺寸几乎相同。p和n的重叠被最小化，使得从发射极注入的电子不会误入歧途。
图17b中示出了基于使用绝缘体上硅的工艺的晶体管。这里，埋置氧化物用作发射电子的屏障，使得几乎所有注入的电子都在集电极中结束。
图17c中示出了开路基极晶体管的第三实施例。埋置p层反射注入的电子。这提高了低电流电平的电流增益。该开路基极晶体管具有大约3V的击穿电压和非常低的泄漏电流。因此，其最适合用作SCR的触发电流源。SCR显示出非常低的触发电压和低泄漏电流。
所附独立权利要求中阐述了本发明的特定和优选的方面。来自从属权利要求和/或独立权利要求的特征的组合可以适当地结合，而不仅是如权利要求中所阐述的。
本公开的范围包括任何新颖的特征或其中明确或隐含地公开的特征的组合或其任何概括，而不管其是否涉及要求保护的发明或减轻了本发明所解决的任何或所有问题。申请人特此通知，在起诉本申请或由此衍生的任何此类进一步申请期间，可以对这样的特征提出新的权利要求。特别地，参照所附权利要求，可以将从属权利要求的特征与独立权利要求的特征组合，并且可以以任何适当的方式而不是仅仅以权利要求中列举的特定组合来组合来自各个独立权利要求的特征。
在单独的实施例的上下文中描述的特征也可以在单个实施例中组合提供。相反，为简洁起见，在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合来提供
术语“包括”不排除其它元件或步骤，术语“一”或“一个”不排除多个。权利要求中的附图标记不应解释为限制权利要求的范围。

Claims (16)

1.一种半导体装置，包括：
第一n+区域，
第一p+区域，其位于所述第一n+区域内，
第二n+区域，
第二p+区域，其位于所述第一n+区域与所述第二n+区域之间，
其中，所述第一n+区域、所述第二n+区域和所述第二p+区域位于p-区域内，
其中，第一空间电荷区域和第二空间电荷区域形成在所述p-区域内，并且
其中，第一空间区域位于所述第一n+区域与所述第二p+区域之间，并且第二空间区域位于所述第二p+区域与所述第二n+区域之间。
2.根据权利要求1所述的半导体装置，其中，所述p-区域为低掺杂的外延层。
3.根据权利要求1或2所述的半导体装置，其中，所有极性被反转，即，所有p掺杂区域为n掺杂区域，并且所有n掺杂区域为p掺杂区域。
4.根据权利要求1、2和3中任一项所述的半导体装置，其中，所述第一空间区域和所述第二空间区域为2μm至3μm宽。
5.根据前述权利要求中任一项所述的半导体装置，其中，电隔离层布置在所述半导体装置的底部。
6.根据权利要求5所述的半导体装置，其中，所述电隔离层为：
埋置p层，或者
埋置n层和埋置n层，或者
埋置p层和埋置n层，或者
埋置氧化物，或者
任意其它合适的隔离布置。
7.根据前述权利要求中任一项所述的半导体装置，其中，所述半导体装置包括侧部电隔离层。
8.根据权利要求7所述的半导体装置，其中，所述侧部电隔离层为沟槽或一组深扩散部。
9.根据前述权利要求中任一项所述的半导体装置，其中，所述半导体装置包括触发连接，其用于将触发电流注入到所述半导体装置中。
10.根据权利要求9所述的半导体装置，其中，所述触发连接为位于所述第一n+区域与所述第二p+区域之间的触发带。
11.根据权利要求9所述的半导体装置，其中，所述半导体装置具有浮置基极和阳极，并且其中，触发电流源连接在所述浮置基极与所述阳极之间。
12.根据权利要求9所述的半导体装置，其中，触发电流源被实现为：
二极管串，二极管串包括至少1个二极管，或者
雪崩二极管，其具有6V至20V之间的范围内的击穿电压，或者
双极结型晶体管，或者
开路基极双极结型晶体管，或者
金属氧化物硅(MOS)晶体管，或者
以二极管配置的MOS晶体管，或者
任意其它合适的触发连接。
13.根据权利要求9所述的半导体装置，其中，触发电流源被实现为具有6V以下的触发电压和4V以下的快速回弹电压的开路基极晶体管。
14.根据前述权利要求中任一项所述的半导体装置，其中，所述半导体装置被布置为多指布置。
15.一种第二半导体装置，其中，根据前述权利要求中任一项所述的半导体装置的结构被重复至少2次，其中，所述第二半导体装置为双向装置。
16.一种制造根据前述权利要求中任一项所述的半导体装置的方法。
CN202110894943.3A 2020-08-05 2021-08-05 半导体装置和半导体装置的制造方法 Pending CN114068520A (zh)

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