CN114065693B - Method and system for optimizing layout of super-large-scale integrated circuit structure and electronic equipment - Google Patents
Method and system for optimizing layout of super-large-scale integrated circuit structure and electronic equipment Download PDFInfo
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Abstract
The application relates to the field of very large scale integrated circuits, and particularly discloses a method and a system for optimizing the structural layout of a very large scale integrated circuit and electronic equipment. Therefore, whether the voltage drop condition of each module is met or not in the chip layout can be accurately judged, and the manufactured integrated circuit is higher in performance.
Description
Technical Field
The present invention relates to the field of very large scale integrated circuits, and more particularly, to a method, system and electronic device for optimizing the layout of a very large scale integrated circuit structure.
Background
With the rapid development of very large scale integrated circuits, more and more modules are integrated on the same chip, and the design process based on grading becomes a necessary trend, so the layout planning becomes more and more important. In the layout stage, a logic unit layout, a standard unit or a macro module in a logic diagram is placed on a proper position of a chip according to the connection information of the logic diagram of the integrated circuit, and in the wiring stage, the units are interconnected according to logic signals.
In particular, as the integrated circuit technology develops, the operating voltage decreases, the power consumption density increases, and the problem of the voltage drop of the power supply network becomes more and more prominent. Therefore, it is expected to consider the voltage drop constraint in the layout planning stage to solve the grid drop problem at the initial stage of the physical design, so as to speed up the convergence of the physical design.
Specifically, the voltage drop of the power supply network is caused by the current passing through the resistor on the power supply network, and as the integrated circuit is continuously developed, the feature size is smaller and smaller, the operating frequency is higher and higher, and the current density and the wiring length on the chip are increased, which brings larger voltage drop. Meanwhile, the working voltage is continuously reduced, so that the maximum allowable voltage drop for normal operation is continuously reduced. The problem of voltage drop will be more and more prominent with the development of the process, and will soon become one of the key factors that restrict the performance of the integrated circuit. Therefore, in order to solve such problems, an optimization method of the layout of the vlsi structure is desired.
Disclosure of Invention
The present application is proposed to solve the above-mentioned technical problems. The embodiment of the application provides an optimization method, a system and electronic equipment for a super-large-scale integrated circuit structure layout, which are used for gridding a chip layout to determine grid positions corresponding to modules on the chip layout, extracting correlation characteristics among the corresponding modules by using a convolutional neural network model and performing spatial coding to obtain characteristic representation of a spatial relation according with current density, further calculating block resistance characteristic values in the horizontal direction and the vertical direction corresponding to the positions in a connected domain, and calculating a voltage drop model for each position based on a spatial path effect to obtain a voltage drop characteristic matrix so as to obtain a more accurate classification result. Therefore, whether the voltage drop condition of each module is met or not in the chip layout can be accurately judged, and the manufactured integrated circuit is higher in performance.
According to an aspect of the present application, there is provided a method for optimizing a layout of a very large scale integrated circuit structure, comprising:
obtaining a chip layout;
constructing an initial distance matrix for the chip layout diagram based on gridding processing of block modules and based on distances between each block module and a power pin in the chip layout diagram on a power ground network;
spatially encoding the initial distance matrix using a convolutional neural network to obtain an encoded distance matrix representing a feature distribution of a spatial relationship of current densities;
performing normalization processing based on the maximum value on the characteristic value of each position in the coding distance matrix by taking the maximum value in the characteristic value of each position in the coding distance matrix as the maximum value to obtain a current density characteristic matrix;
constructing a resistance feature matrix based on the encoded distance matrix;
calculating the distribution of the eigenvalues of other positions of each position in the resistance eigenvalue matrix in the horizontal direction and the vertical direction to determine a connected domain of the position, and taking the eigenvalue of each position in the connected domain of the position as the block resistance eigenvalue in the horizontal direction and the vertical direction corresponding to the position to obtain a block resistance eigenvalue matrix;
calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix based on characteristic values of all positions in the current density characteristic matrix to obtain a voltage drop characteristic matrix; and
and inputting the voltage drop characteristic matrix into a classifier to obtain a classification result for representing whether the chip layout meets the voltage drop condition of each module.
In the method for optimizing the layout of the vlsi structure, constructing an initial distance matrix for the chip layout based on the gridding process of the block modules and the distance between each block module and the power pins in the chip layout on the power ground network includes: performing gridding processing on the chip layout to determine the grid position of each block module in the chip layout; and filling the distance between the corresponding block module and the power pin on a power ground network in the corresponding grid position to obtain the initial distance matrix.
In the method for optimizing the layout of the vlsi structure, the spatially encoding the initial distance matrix using a convolutional neural network to obtain an encoded distance matrix representing a feature distribution of a spatial relationship of current densities, includes: the other layers of the convolutional neural network except the last layer spatially encode the initial distance matrix to obtain a feature map according to the following formula:
wherein, the first and the second end of the pipe are connected with each other,
is the input of the ith layer of convolutional neural network,
is the output of the ith layer of convolutional neural network,
is a filter of the ith layer convolutional neural network, an
Is a bias matrix of the i-th layer neural network,
representing a non-linear activation function; and the last layer of the convolutional neural network performs global pooling processing on the feature map along a channel dimension to obtain the coding distance matrix.
In the method for optimizing the layout of the vlsi structure, constructing a resistance feature matrix based on the coding distance matrix includes: and taking the characteristic value of each position in the coding distance matrix as the node resistance characteristic value of each position in the resistance characteristic matrix to obtain the resistance characteristic matrix.
In the method for optimizing the layout of the vlsi structure, calculating the characteristic value of the voltage drop at each position in the characteristic matrix of the resistance characteristic values of the block based on the characteristic value at each position in the characteristic matrix of the current density to obtain the characteristic matrix of the voltage drop, the method includes: calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix according to the following formula based on characteristic values of all positions in the current density characteristic matrix to obtain the voltage drop characteristic matrix;
wherein the formula is:
wherein
Is the eigenvalue of the corresponding position in the current density eigenvalue matrix,
and
are the path distances of the predetermined location in the width and height dimensions, respectively, and,
and
the block resistance characteristic values in the horizontal direction and the vertical direction corresponding to the position are respectively.
In the method for optimizing the layout of the VLSI structure, if the power supply position is (C)
) Then, then
And is made of
。
In the method for optimizing the layout of the vlsi structure, inputting the voltage drop characteristic matrix into a classifier to obtain a classification result indicating whether a chip layout satisfies a voltage drop condition of each module, the method includes: fully concatenating the voltage drop feature matrix using a plurality of fully concatenated layers of the classifier to obtain a classified feature vector; inputting the classification feature vector into a Softmax classification function of the classifier to obtain a first probability that the chip layout satisfies a voltage drop condition of each module and a second probability that the chip layout does not satisfy the voltage drop condition of each module; and determining the classification result based on a comparison of the first probability and the second probability.
According to another aspect of the present application, there is provided a system for optimizing a layout of a very large scale integrated circuit structure, comprising:
a layout acquiring unit for acquiring a chip layout;
a matrix constructing unit, configured to construct an initial distance matrix for the chip layout obtained by the layout obtaining unit based on gridding processing of block modules and based on distances between each block module and power pins in the chip layout on a power ground network;
a convolutional neural network processing unit for spatially encoding the initial distance matrix obtained by the matrix construction unit using a convolutional neural network to obtain an encoded distance matrix for a feature distribution representing a spatial relationship of current densities;
a normalization unit, configured to perform maximum-value-based normalization processing on the feature values of each position in the coding distance matrix with a maximum value of the feature values of each position in the coding distance matrix obtained by the convolutional neural network processing unit as a maximum value to obtain a current density feature matrix;
a resistance characteristic matrix constructing unit, configured to construct a resistance characteristic matrix based on the coding distance matrix obtained by the convolutional neural network processing unit;
a block resistance characteristic value feature matrix generating unit, configured to calculate distributions of characteristic values of other positions in the resistance characteristic matrix in the horizontal direction and the vertical direction of each position in the resistance characteristic matrix obtained by the resistance characteristic matrix constructing unit to determine a connected domain of the position, and use the characteristic value of each position in the connected domain of the position as a block resistance characteristic value in the horizontal direction and the vertical direction corresponding to the position, so as to obtain a block resistance characteristic value feature matrix;
a voltage drop characteristic matrix generating unit, configured to calculate, based on the characteristic value at each position in the current density characteristic matrix obtained by the normalizing unit, the voltage drop characteristic value at each position in the block resistance characteristic value characteristic matrix obtained by the block resistance characteristic value characteristic matrix generating unit to obtain a voltage drop characteristic matrix; and
and the classification unit is used for inputting the voltage drop characteristic matrix obtained by the voltage drop characteristic matrix generation unit into a classifier so as to obtain a classification result which is used for representing whether the chip layout meets the voltage drop condition of each module.
In the above system for optimizing an lsi structural layout, the matrix constructing unit is further configured to: performing gridding processing on the chip layout to determine the grid position of each block module in the chip layout; and filling the distance between the corresponding block module and the power pin on a power ground network in the corresponding grid position to obtain the initial distance matrix.
In the optimization system of the vlsi structure layout, the convolutional neural network processing unit is further configured to: the other layers of the convolutional neural network except the last layer spatially encode the initial distance matrix to obtain a feature map according to the following formula:
wherein the content of the first and second substances,
is the input of the ith layer of convolutional neural network,
is the output of the ith layer of convolutional neural network,
is a filter of the ith convolutional neural network, an
Is a bias matrix of the i-th layer neural network,
representing a non-linear activation function; and the last layer of the convolutional neural network performs global pooling processing on the feature map along a channel dimension to obtain the coding distance matrix.
In the system for optimizing the layout of the lsi structure, the resistance feature matrix constructing unit is further configured to: and taking the characteristic value of each position in the coding distance matrix as the node resistance characteristic value of each position in the resistance characteristic matrix to obtain the resistance characteristic matrix.
In the system for optimizing the layout of the vlsi structure, the voltage drop characteristic matrix generating unit is further configured to: calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix according to the following formula based on characteristic values of all positions in the current density characteristic matrix to obtain the voltage drop characteristic matrix;
wherein the formula is:
wherein
Is the eigenvalue of the corresponding position in the current density eigenvalue matrix,
and
are the path distances of the predetermined location in the width and height dimensions, respectively, and,
and
the block resistance characteristic values in the horizontal direction and the vertical direction corresponding to the position are respectively.
In the above-mentioned optimization system for VLSI structure layout, if the power source position is (C:)
) Then, then
And is and
。
in the system for optimizing the layout of the lsi structure, the classifying unit is further configured to: fully concatenating the voltage drop feature matrix using a plurality of fully concatenated layers of the classifier to obtain a classified feature vector; inputting the classification feature vector into a Softmax classification function of the classifier to obtain a first probability that the chip layout satisfies a voltage drop condition of each module and a second probability that the chip layout does not satisfy the voltage drop condition of each module; and determining the classification result based on a comparison of the first probability and the second probability.
According to yet another aspect of the present application, there is provided an electronic device including: a processor; and a memory in which are stored computer program instructions which, when executed by the processor, cause the processor to perform the method of optimizing a layout of a very large scale integrated circuit structure as described above.
According to yet another aspect of the present application, there is provided a computer readable medium having stored thereon computer program instructions which, when executed by a processor, cause the processor to perform the method of optimizing a layout of a very large scale integrated circuit structure as described above.
Compared with the prior art, the optimization method, the optimization system and the electronic equipment for the structural layout of the very large scale integrated circuit provided by the application are used for gridding a chip layout to determine grid positions corresponding to modules on the chip layout, extracting the correlation characteristics among the corresponding modules by using a convolutional neural network model and performing spatial coding to obtain the characteristic representation of the spatial relationship according with current density, further calculating block resistance characteristic values in the horizontal direction and the vertical direction corresponding to the positions in a connected domain, and then calculating a voltage drop model for each position based on a spatial path effect to obtain a voltage drop characteristic matrix so as to obtain a more accurate classification result. Therefore, whether the voltage drop condition of each module is met or not in the chip layout can be accurately judged, and the manufactured integrated circuit is higher in performance.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in more detail embodiments of the present application with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings, like reference numbers generally represent like parts or steps.
FIG. 1 is a diagram illustrating voltage drop distribution of a chip with uniformly distributed current according to an exemplary method for optimizing a layout of a VLSI structure;
FIG. 2 is a flow chart of a method for optimizing a layout of a VLSI structure according to an embodiment of the present application;
FIG. 3 is a system architecture diagram illustrating a method for optimizing a layout of a VLSI structure according to an embodiment of the present invention;
FIG. 4 is a block diagram of a system for optimizing a layout of a VLSI structure according to an embodiment of the present application;
fig. 5 is a block diagram of an electronic device according to an embodiment of the application.
Detailed Description
Hereinafter, example embodiments according to the present application will be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the present application and not all embodiments of the present application, and that the present application is not limited by the example embodiments described herein.
Overview of a scene
As mentioned above, as the integrated circuit technology develops, the operating voltage decreases, the power consumption density increases, and the problem of the power supply network voltage drop becomes more and more prominent. Therefore, it is expected to consider the voltage drop constraint in the layout planning stage to solve the grid drop problem at the initial stage of the physical design, so as to speed up the convergence of the physical design.
Specifically, the voltage drop of the power supply network is caused by the current passing through the resistor on the power supply network, and as the integrated circuit is continuously developed, the feature size is smaller and smaller, the operating frequency is higher and higher, and the current density and the wiring length on the chip are increased, which brings larger voltage drop. Meanwhile, the working voltage is continuously reduced, so that the maximum allowable voltage drop for normal operation is continuously reduced. The problem of voltage drop will be more and more prominent with the development of the process, and will soon become one of the key factors that restrict the performance of the integrated circuit. Therefore, in order to solve such problems, an optimization method of the layout of the vlsi structure is desired.
At design time, the voltage drop is related to the distance. The voltage drop is due to the current passing through a resistance on the power ground network. The large voltage drop will make the internal voltage value of the module unable to meet the requirement of normal operation, thereby causing the chip to generate logic errors. The voltage drop at a certain point inside the chip mainly depends on the resistance value on the power and ground network, and the resistance value is in direct proportion to the distance from the power pin to the point inside the chip, so that the voltage drop is closely related to the position of each module, and the position of each module is determined in the layout stage.
In the layout stage, when voltage drops of all points in a chip are estimated, voltage drops on a power supply ring and a ground ring around the chip are ignored, and the voltage drops are mainly caused by connection line resistance and through hole resistance of an internal power supply network.
Based on this, a voltage drop model is proposed:
wherein the content of the first and second substances,
is the current density of the electric current,R sx is the square resistance of the power grid in the horizontal direction,R sy the square resistance is vertical to the power grid. For the chip with uniform current distribution, the voltage drop distribution of the chip with uniform current distribution is
=
The point where the voltage drop is the largest occurs at the center of the chip as shown in fig. 1.
However, in practical situations, the current density on the chip is not uniformly distributed, and the current densities of the various modules are greatly different during the layout phase, and the voltage drops of different current densities are greatly different at the same position. Therefore, the voltage drop is not the same for each module, and it is not accurate to use only the distance as an objective function of the voltage drop in the floorplanning. The voltage drop influence degree of each module is different, some modules have strict voltage drop requirements, and other modules have not strict requirements on the voltage drop, so that the weight can be introduced into the voltage drop target value.
Specifically, in the technical scheme of the application, a chip layout is obtained first, the chip layout is gridded, grid positions corresponding to modules on the chip layout are determined, and distances between the modules and power pins on a power ground network are filled in the corresponding grids, so that an initial distance matrix is obtained. Then, it is considered that the current density reaching each module is not the same, and this current density is also substantially related to the spatial relationship of each module with respect to the whole on the chip layout, for example, when the module is close to the power supply, the current density is large, and if the module is far from the power supply and there are a plurality of other modules on the path, the current density is affected by both the resistance consumption at the distance and the current attenuation of other modules, and therefore, it is necessary to obtain the representation of the current density at each position based on the initial distance matrix.
Therefore, in the technical scheme of the application, the convolutional neural network is applied to perform spatial coding on the initial distance matrix so as to extract each node in the initial distance matrix, namely, the correlation characteristic between corresponding modules and perform spatial coding, thereby obtaining the characteristic representation of the spatial relationship conforming to the current density. Here, it is noted that the feature of the current density is substantially inversely proportional to the spatial feature based on the distance as described above, and therefore, after the initial distance matrix is input to the convolutional neural network to obtain the encoding distance matrix, the maximum feature value in the encoding distance matrix is divided into a numerator by the feature value of each position in the encoding distance matrix to obtain the current density feature matrix, so that the feature value is mapped into the probability interval of [0,1] to obtain the probability density feature value corresponding to the current density, and the current density feature inversely proportional to the spatial feature is also obtained.
And, since the node resistance is directly proportional to the position of the node from the power source, the eigenvalue of each position in the coding distance matrix can be directly used as the node resistance eigenvalue, i.e., the resistance characteristic matrix is obtained. Here, for each node to be calculated, in order to calculate the power grid horizontal direction block resistance and the power grid vertical direction block resistance based on the position of the node, connected domains are determined in the horizontal direction and the vertical direction based on the characteristic value of the position, respectively, wherein the threshold values of the connected domains in the horizontal direction and the vertical direction may be the same, thereby calculating the mean value of the characteristic values of each position within the connected domains as the block resistance characteristic values in the horizontal direction and the vertical direction corresponding to the position.
Finally, based on the spatial path effect, each location is calculated to obtain a voltage drop feature matrix using the following formula:
wherein
Are eigenvalues of corresponding positions in the current density eigenvalue matrix,
and
path distances of the predetermined position in the width and height dimensions, respectively, in particular if the power supply position is: (
) Then, then
And is and
in addition, the first and second substrates are, in addition,
and
respectively the horizontal direction and the vertical direction corresponding to the positionThe block resistance characteristic value in the direction.
And then inputting the voltage drop characteristic matrix into a classifier to obtain a classification result of whether the chip layout meets the voltage drop condition of each module.
Based on this, the present application provides a method for optimizing a layout of a very large scale integrated circuit structure, which includes: obtaining a chip layout; constructing an initial distance matrix for the chip layout diagram based on gridding processing of block modules and based on distances between each block module and a power pin in the chip layout diagram on a power ground network; spatially encoding the initial distance matrix using a convolutional neural network to obtain an encoded distance matrix representing a feature distribution of a spatial relationship of current densities; performing normalization processing based on the maximum value on the characteristic value of each position in the coding distance matrix by taking the maximum value in the characteristic value of each position in the coding distance matrix as the maximum value to obtain a current density characteristic matrix; constructing a resistance feature matrix based on the encoded distance matrix; calculating the distribution of the eigenvalues of other positions of each position in the resistance eigenvalue matrix in the horizontal direction and the vertical direction to determine a connected domain of the position, and taking the eigenvalue of each position in the connected domain of the position as the block resistance eigenvalue in the horizontal direction and the vertical direction corresponding to the position to obtain a block resistance eigenvalue matrix; calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix based on characteristic values of all positions in the current density characteristic matrix to obtain a voltage drop characteristic matrix; and inputting the voltage drop characteristic matrix into a classifier to obtain a classification result for representing whether the chip layout meets the voltage drop condition of each module.
Having described the general principles of the present application, various non-limiting embodiments of the present application will now be described with reference to the accompanying drawings.
Exemplary method
Fig. 2 illustrates a flow chart of a method of optimizing a layout of a very large scale integrated circuit structure. As shown in fig. 2, a method for optimizing a layout of a very large scale integrated circuit structure according to an embodiment of the present application includes: s110, obtaining a chip layout; s120, constructing an initial distance matrix for the chip layout diagram based on the gridding processing of the block modules and the distance between each block module and the power supply pin in the chip layout diagram on the power supply ground network; s130, using a convolutional neural network to spatially encode the initial distance matrix to obtain an encoding distance matrix of characteristic distribution representing spatial relation of current density; s140, carrying out normalization processing based on the maximum value on the characteristic value of each position in the coding distance matrix by taking the maximum value in the characteristic value of each position in the coding distance matrix as the maximum value to obtain a current density characteristic matrix; s150, constructing a resistance characteristic matrix based on the coding distance matrix; s160, calculating the distribution of the eigenvalues of other positions of each position in the resistance eigenvalue matrix in the horizontal direction and the vertical direction to determine a connected domain of the position, and taking the eigenvalue of each position in the connected domain of the position as the block resistance eigenvalue in the horizontal direction and the vertical direction corresponding to the position to obtain a block resistance eigenvalue matrix; s170, calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix based on characteristic values of all positions in the current density characteristic matrix to obtain a voltage drop characteristic matrix; and S180, inputting the voltage drop characteristic matrix into a classifier to obtain a classification result for indicating whether the chip layout meets the voltage drop condition of each module.
Fig. 3 is a schematic diagram illustrating an architecture of a method for optimizing a layout of a very large scale integrated circuit structure according to an embodiment of the present application. As shown IN fig. 3, IN the network architecture of the optimization method of the vlsi structure layout, first, an initial distance matrix (e.g., M1 as illustrated IN fig. 3) is constructed for the obtained chip layout (e.g., IN as illustrated IN fig. 3) based on the gridding process of the block modules and based on the distances between the respective block modules and the power pins IN the chip layout on the power ground network; then, spatially encoding the initial distance matrix using a convolutional neural network (e.g., CNN as illustrated in fig. 3) to obtain an encoded distance matrix (e.g., M2 as illustrated in fig. 3) for a feature distribution representing a spatial relationship of current densities; then, performing normalization processing based on the maximum value on the feature values of the positions in the encoding distance matrix by taking the maximum value in the feature values of the positions in the encoding distance matrix as the maximum value to obtain a current density feature matrix (for example, as MF1 illustrated in fig. 3); then, constructing a resistance signature matrix (e.g., MF2 as illustrated in fig. 3) based on the encoding distance matrix; then, calculating the distribution of the eigenvalues of other positions of each position in the resistance eigenvalue matrix in the horizontal direction and the vertical direction to determine a connected domain of the position, and taking the eigenvalue of each position in the connected domain of the position as the block resistance eigenvalue in the horizontal direction and the vertical direction corresponding to the position to obtain a block resistance eigenvalue eigen matrix (for example, MF3 as illustrated in fig. 3); then, based on the eigenvalues of the respective positions in the current density eigenvalue eigen matrix, calculating voltage drop eigenvalues (e.g., V as illustrated in fig. 3) of the respective positions in the block resistance eigenvalue eigen matrix to obtain a voltage drop eigen matrix (e.g., MF as illustrated in fig. 3); and, finally, inputting the voltage drop characteristic matrix into a classifier (e.g., a classifier as illustrated in fig. 3) to obtain a classification result representing whether the chip layout satisfies the voltage drop condition of each module.
In step S110 and step S120, a chip layout is acquired; and constructing an initial distance matrix for the chip layout diagram based on the gridding processing of the block modules and the distance between each block module and the power supply pin in the chip layout diagram on the power supply ground network. As mentioned above, the voltage drop is caused by the current passing through the resistance on the power ground network, and a larger voltage drop will make the voltage value inside the module fail to meet the requirement of normal operation, thereby causing a chip logic error, while the voltage drop at a certain point inside the chip mainly depends on the resistance value on the power ground network, which is proportional to the distance from the power pin to the point inside the chip, so that the voltage drop has a close relationship with the position of each module, and the position of the module is determined in the layout stage. Therefore, in the technical solution of the present application, a chip layout needs to be obtained first, and the chip layout is subjected to gridding processing based on block modules to determine grid positions corresponding to the modules on the chip layout, and the corresponding grids are filled with distances between the block modules and the power pins on the power ground network, so as to obtain an initial distance matrix, and facilitate subsequent feature extraction.
Specifically, in this embodiment of the present application, a process of constructing an initial distance matrix for the chip layout based on gridding processing of block modules and based on distances between each block module and a power pin in the chip layout on a power ground network includes: firstly, carrying out gridding processing on the chip layout diagram to determine the grid position of each block module in the chip layout diagram; then, filling the distances between the corresponding block modules and the power pins on a power ground network in the corresponding grid positions to obtain the initial distance matrix.
In step S130, the initial distance matrix is spatially encoded using a convolutional neural network to obtain an encoded distance matrix for a feature distribution representing a spatial relationship of current densities. It should be understood that, considering that the current densities reaching the modules are not the same, and such current densities are also substantially related to the spatial relationship of the modules with respect to the whole on the chip layout, for example, when the modules are close to the power supply, the current densities are larger, and if the modules are far away from the power supply and there are a plurality of other modules on the path, the current densities are affected by both the resistance consumption at the distance and the current attenuation of other modules, therefore, in the technical solution of the present application, the representation of the current densities at various positions needs to be obtained based on the initial distance matrix. That is, first, a convolutional neural network is applied to spatially encode the initial distance matrix to extract correlation features between nodes, i.e., corresponding modules, in the initial distance matrix and perform spatial encoding, so as to obtain a feature representation conforming to the spatial relationship of the current density.
Specifically, in the embodiment of the present application, the process of spatially encoding the initial distance matrix using a convolutional neural network to obtain an encoded distance matrix for representing a feature distribution of a spatial relationship of current densities includes: firstly, the other layers except the last layer of the convolutional neural network spatially encode the initial distance matrix to obtain a feature map according to the following formula:
wherein the content of the first and second substances,
is the input of the ith layer of convolutional neural network,
is the output of the ith layer of convolutional neural network,
is a filter of the ith convolutional neural network, an
Is a bias matrix of the i-th layer neural network,
representing a non-linear activation function. Then, the last layer of the convolutional neural network performs global pooling along the channel dimension on the feature map to obtain the coding distance matrix.
In step S140, a maximum value-based normalization process is performed on the feature values of the positions in the encoding distance matrix with the maximum value of the feature values of the positions in the encoding distance matrix as a maximum value to obtain a current density feature matrix. It should be understood that, considering that the characteristic of the current density is substantially inversely proportional to the spatial distance-based characteristic, in the technical solution of the present application, after the initial distance matrix is input to the convolutional neural network to obtain the coded distance matrix, the maximum value-based normalization processing is performed on the characteristic value of each position in the coded distance matrix by using the maximum value in the characteristic values of each position in the coded distance matrix as the maximum value. That is, in a specific example, the largest eigenvalue in the encoding distance matrix is taken as a numerator to be divided by the eigenvalue of each position in the encoding distance matrix to obtain a current density eigenvalue matrix, so that the eigenvalue is mapped to a probability interval of [0,1] to eliminate the dimensional influence between data characteristics, to facilitate measurement and subsequent calculation, to obtain a probability density eigenvalue corresponding to the current density, and to obtain a current density eigenvalue inversely proportional to the spatial characteristic.
In steps S150 and S160, a resistance feature matrix is constructed based on the encoding distance matrix, and the distribution of the feature values of other positions of each position in the resistance feature matrix in the horizontal direction and the vertical direction is calculated to determine the connected domain of the position, and the feature value of each position in the connected domain of the position is used as the block resistance feature value in the horizontal direction and the vertical direction corresponding to the position, so as to obtain a block resistance feature value feature matrix. It should be understood that, since the node resistance is directly proportional to the distance between the position of the node and the power supply, in the technical solution of the present application, the eigenvalue of each position in the coding distance matrix may be directly used as the node resistance eigenvalue. That is, a resistance feature matrix is constructed based on the encoding distance matrix, and in a specific example, a feature value of each position in the encoding distance matrix may be used as a node resistance feature value of each position in the resistance feature matrix to obtain the resistance feature matrix. Here, for each of the nodes to be calculated, in order to calculate a power grid horizontal direction block resistance and a power grid vertical direction block resistance based on a position of the node, connected domains are determined in a horizontal direction and a vertical direction based on a feature value of the position, respectively, wherein thresholds of the connected domains in the horizontal direction and the vertical direction may be the same, so that a mean value of feature values of each position in the connected domains is calculated as a block resistance feature value in the horizontal direction and the vertical direction corresponding to the position, and a block resistance feature value feature matrix is obtained based on the obtained block resistance feature values.
In step S170, voltage drop characteristic values of respective positions in the block resistance characteristic value characteristic matrix are calculated based on characteristic values of respective positions in the current density characteristic matrix to obtain a voltage drop characteristic matrix. That is, in the technical solution of the present application, after obtaining the block resistance eigenvalue feature matrix and the current density feature matrix, based on a spatial path effect, a voltage drop model formula is calculated for each position in the block resistance eigenvalue feature matrix, so as to obtain a voltage drop feature value, and then a voltage drop feature matrix is obtained based on the voltage drop feature value.
Specifically, in this embodiment of the present application, the process of calculating the voltage drop characteristic value of each position in the block resistance characteristic value characteristic matrix based on the characteristic value of each position in the current density characteristic matrix to obtain the voltage drop characteristic matrix includes: calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix according to the following formula based on characteristic values of all positions in the current density characteristic matrix to obtain the voltage drop characteristic matrix;
wherein the formula is:
wherein
Is the eigenvalue of the corresponding position in the current density eigenvalue matrix,
and
path distances of predetermined positions in width and height dimensions, respectively, in particular if the power supply position is: (
) Then, then
And is and
and, in addition,
and
the block resistance characteristic values in the horizontal direction and the vertical direction corresponding to the position are respectively.
In step S180, the voltage drop characteristic matrix is input to a classifier to obtain a classification result indicating whether the chip layout satisfies the voltage drop condition of each module. Accordingly, in one particular example, first, the voltage-drop feature matrix is fully-concatenated encoded using a plurality of fully-concatenated layers of the classifier to obtain a classification feature vector; then, inputting the classification feature vector into a Softmax classification function of the classifier to obtain a first probability that the chip layout meets the voltage drop condition of each module and a second probability that the chip layout does not meet the voltage drop condition of each module; finally, the classification result is determined based on a comparison of the first probability and the second probability. Specifically, when the first probability is greater than the second probability, the classification result is that the chip layout meets the voltage drop condition of each module; and when the first probability is smaller than the second probability, the classification result is that the chip layout does not meet the voltage drop condition of each module.
In summary, the optimization method of the vlsi structure layout according to the embodiment of the present application is elucidated, and the method performs gridding on a chip layout to determine grid positions corresponding to modules on the chip layout, and simultaneously extracts correlation features between corresponding modules by using a convolutional neural network model and performs spatial coding to obtain a feature representation of a spatial relationship conforming to current density, further calculates block resistance feature values in a horizontal direction and a vertical direction corresponding to the positions in a connected domain, and then performs calculation of a voltage drop model for each position based on a spatial path effect to obtain a voltage drop feature matrix, thereby obtaining a more accurate classification result. Therefore, whether the voltage drop condition of each module is met or not in the chip layout can be accurately judged, and the manufactured integrated circuit is higher in performance.
Exemplary System
FIG. 4 illustrates a block diagram of a system for optimizing a layout of a very large scale integrated circuit structure according to an embodiment of the application. As shown in fig. 4, a system 400 for optimizing a layout of a very large scale integrated circuit structure according to an embodiment of the present application includes: a map acquisition unit 410 for acquiring a chip map; a matrix constructing unit 420, configured to construct an initial distance matrix for the chip layout obtained by the layout obtaining unit 410 based on gridding processing of block modules and based on distances between each block module in the chip layout and power pins on a power ground network; a convolutional neural network processing unit 430 for spatially encoding the initial distance matrix obtained by the matrix construction unit 420 using a convolutional neural network to obtain an encoded distance matrix for a feature distribution representing a spatial relationship of current densities; a normalization unit 440, configured to perform maximum-value-based normalization processing on the feature values of each position in the encoding distance matrix obtained by the convolutional neural network processing unit 430 by using a maximum value in the feature values of each position in the encoding distance matrix as a maximum value to obtain a current density feature matrix; a resistance feature matrix constructing unit 450 for constructing a resistance feature matrix based on the encoding distance matrix obtained by the convolutional neural network processing unit 430; a block resistance characteristic value feature matrix generating unit 460, configured to calculate distributions of characteristic values of other positions of each position in the resistance characteristic matrix in the horizontal direction and the vertical direction, which are obtained by the resistance characteristic matrix constructing unit 450, to determine a connected domain of the position, and use the characteristic value of each position in the connected domain of the position as a block resistance characteristic value in the horizontal direction and the vertical direction corresponding to the position, so as to obtain a block resistance characteristic value feature matrix; a voltage drop characteristic matrix generating unit 470, configured to calculate voltage drop characteristic values of each position in the block resistance characteristic value characteristic matrix obtained by the block resistance characteristic value characteristic matrix generating unit 450 based on the characteristic values of each position in the current density characteristic matrix obtained by the normalizing unit 440 to obtain a voltage drop characteristic matrix; and a classification unit 480, configured to input the voltage drop feature matrix obtained by the voltage drop feature matrix generation unit 470 into a classifier to obtain a classification result indicating whether the chip layout satisfies the voltage drop condition of each module.
In an example, in the system 400 for optimizing the layout of the vlsi structure, the matrix constructing unit 420 is further configured to: performing gridding processing on the chip layout so as to determine the grid position of each module in the chip layout; and filling the distances between the corresponding block modules and the power pins on a power ground network in the corresponding grid positions to obtain the initial distance matrix.
In an example, in the system 400 for optimizing an lsi structural layout, the convolutional neural network processing unit 430 is further configured to: the other layers of the convolutional neural network except the last layer spatially encode the initial distance matrix to obtain a feature map according to the following formula:
wherein the content of the first and second substances,
is the input of the ith layer of convolutional neural network,
is the output of the ith layer of convolutional neural network,
is a filter of the ith convolutional neural network, an
Is a bias matrix of the i-th layer neural network,
representing a non-linear activation function; and the last layer of the convolutional neural network performs global pooling processing on the feature map along a channel dimension to obtain the coding distance matrix.
In one example, in the system 400 for optimizing the layout of the vlsi structure, the resistance characteristics matrix constructing unit 450 is further configured to: and taking the characteristic value of each position in the coding distance matrix as the node resistance characteristic value of each position in the resistance characteristic matrix to obtain the resistance characteristic matrix.
In an example, in the system 400 for optimizing a layout of an lsi structure, the voltage drop characteristic matrix generating unit 460 is further configured to: calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix according to the following formula based on characteristic values of all positions in the current density characteristic matrix to obtain the voltage drop characteristic matrix;
wherein the formula is:
wherein
Is the eigenvalue of the corresponding position in the current density eigenvalue matrix,
and
are the path distances of the predetermined location in the width and height dimensions, respectively, and,
and
the block resistance characteristic values in the horizontal direction and the vertical direction corresponding to the position, respectively.
In one example, in the system 400 for optimizing the layout of the VLSI structure, if the power source is located at (C)
) Then, then
And is and
。
in an example, in the system 400 for optimizing an lsi structural layout, the classifying unit 480 is further configured to: fully concatenating the voltage drop feature matrix using a plurality of fully concatenated layers of the classifier to obtain a classified feature vector; inputting the classification feature vector into a Softmax classification function of the classifier to obtain a first probability that the chip layout satisfies a voltage drop condition of each module and a second probability that the chip layout does not satisfy the voltage drop condition of each module; and determining the classification result based on a comparison of the first probability and the second probability.
Here, it will be understood by those skilled in the art that the specific functions and operations of the respective units and modules in the above-described system 400 for optimizing the layout of the vlsi structure have been described in detail in the above description of the method for optimizing the layout of the vlsi structure with reference to fig. 1 to 3, and thus, a repetitive description thereof will be omitted.
As described above, the system 400 for optimizing the layout of the vlsi structure according to the embodiment of the present application can be implemented in various terminal devices, such as a server for an optimization algorithm of the layout of the vlsi structure. In one example, the system 400 for optimizing the layout of a very large scale integrated circuit structure according to an embodiment of the present application may be integrated into a terminal device as a software module and/or a hardware module. For example, the system 400 for optimizing the layout of the vlsi architecture may be a software module in the operating system of the terminal device, or may be an application developed for the terminal device; of course, the system 400 for optimizing the layout of a very large scale integrated circuit structure can also be one of many hardware modules of the terminal device.
Alternatively, in another example, the system 400 for optimizing the layout of the vlsi structure and the terminal device may be separate devices, and the system 400 for optimizing the layout of the vlsi structure may be connected to the terminal device through a wired and/or wireless network and transmit the interaction information according to the agreed data format.
Exemplary electronic device
Next, an electronic apparatus according to an embodiment of the present application is described with reference to fig. 5. As shown in fig. 5, the electronic device 10 includes one or more processors 11 and memory 12. The processor 11 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.
In one example, the electronic device 10 may further include: an input system 13 and an output system 14, which are interconnected by a bus system and/or other form of connection mechanism (not shown).
The input system 13 may comprise, for example, a keyboard, a mouse, etc.
The output system 14 may output various information including classification results and the like to the outside. The output system 14 may include, for example, a display, speakers, a printer, and a communication network and its connected remote output devices, among others.
Of course, for simplicity, only some of the components of the electronic device 10 relevant to the present application are shown in fig. 5, and components such as buses, input/output interfaces, and the like are omitted. In addition, the electronic device 10 may include any other suitable components depending on the particular application.
Exemplary computer program product and computer-readable storage Medium
In addition to the above-described methods and apparatus, embodiments of the present application may also be a computer program product comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the functions of the method for optimizing a layout of a vlsi structure according to various embodiments of the present application described in the above-mentioned "exemplary methods" section of this specification.
The computer program product may be written with program code for performing the operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.
Furthermore, embodiments of the present application may also be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform the steps in the method for optimizing a layout of a vlsi structure described in the "exemplary methods" section of this specification above.
The computer-readable storage medium may take any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.
The block diagrams of devices, apparatuses, systems referred to in this application are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
It should also be noted that in the devices, apparatuses, and methods of the present application, the components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered as equivalents of the present application.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (9)
1. A method for optimizing a layout of a very large scale integrated circuit structure, comprising:
obtaining a chip layout;
constructing an initial distance matrix for the chip layout diagram based on gridding processing of block modules and based on distances between each block module and a power pin in the chip layout diagram on a power ground network;
spatially encoding the initial distance matrix using a convolutional neural network to obtain an encoded distance matrix representing a feature distribution of a spatial relationship of current densities;
performing normalization processing based on the maximum value on the characteristic value of each position in the coding distance matrix by taking the maximum value in the characteristic value of each position in the coding distance matrix as the maximum value to obtain a current density characteristic matrix;
constructing a resistance feature matrix based on the encoded distance matrix;
calculating the distribution of the eigenvalues of other positions of each position in the resistance eigenvalue matrix in the horizontal direction and the vertical direction to determine a connected domain of the position, and taking the eigenvalue of each position in the connected domain of the position as the block resistance eigenvalue in the horizontal direction and the vertical direction corresponding to the position to obtain a block resistance eigenvalue matrix;
calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix based on characteristic values of all positions in the current density characteristic matrix to obtain a voltage drop characteristic matrix; and
inputting the voltage drop characteristic matrix into a classifier to obtain a classification result for representing whether the chip layout meets the voltage drop condition of each module;
calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix based on characteristic values of all positions in the current density characteristic matrix to obtain a voltage drop characteristic matrix, wherein the voltage drop characteristic matrix comprises the following steps:
calculating voltage drop characteristic values of all positions in the block resistance characteristic value characteristic matrix according to the characteristic values of all positions in the current density characteristic matrix and the following formula so as to obtain the voltage drop characteristic matrix;
wherein the formula is:
wherein
Is the eigenvalue of the corresponding position in the current density eigenvalue matrix,
and
are the path distances of the predetermined location in the width and height dimensions, respectively, and,
and
。
2. the method of optimizing a layout of a very large scale integrated circuit structure of claim 1, wherein constructing an initial distance matrix for the chip layout based on a gridding process of block modules and based on distances between individual block modules and power pins in the chip layout over a power ground network comprises:
performing gridding processing on the chip layout to determine the grid position of each block module in the chip layout; and
and filling the distance between the corresponding block module and the power pin on a power ground network in the corresponding grid position to obtain the initial distance matrix.
3. The method of optimizing a very large scale integrated circuit structure layout of claim 2, wherein spatially encoding said initial distance matrix using a convolutional neural network to obtain an encoded distance matrix for a feature distribution representing a spatial relationship of current densities, comprises:
the other layers of the convolutional neural network except the last layer spatially encode the initial distance matrix to obtain a feature map according to the following formula:
wherein the content of the first and second substances,
is the input of the ith layer of convolutional neural network,
is the output of the ith layer of convolutional neural network,
is a filter of the ith convolutional neural network, an
Is a bias matrix of the i-th layer neural network,
representing a non-linear activation function; and
the last layer of the convolutional neural network performs global pooling along the channel dimension on the feature map to obtain the encoding distance matrix.
4. The method of optimizing layout of very large scale integrated circuit structures of claim 3, wherein constructing a matrix of resistive features based on said matrix of coding distances comprises:
and taking the characteristic value of each position in the coding distance matrix as the node resistance characteristic value of each position in the resistance characteristic matrix to obtain the resistance characteristic matrix.
5. The method of claim 4, wherein if the power source is in the position of (A)
) Then, then
And is made of
。
6. The method of optimizing a layout of a very large scale integrated circuit structure of claim 5, wherein inputting the voltage drop characteristic matrix into a classifier to obtain a classification result indicating whether the chip layout satisfies the voltage drop condition of each module comprises:
fully concatenating the voltage drop feature matrix using a plurality of fully concatenated layers of the classifier to obtain a classified feature vector;
inputting the classification feature vector into a Softmax classification function of the classifier to obtain a first probability that the chip layout satisfies a voltage drop condition of each module and a second probability that the chip layout does not satisfy the voltage drop condition of each module; and
determining the classification result based on a comparison of the first probability and the second probability.
7. A system for optimizing a layout of a very large scale integrated circuit structure, comprising:
a layout acquiring unit for acquiring a chip layout;
a matrix constructing unit, configured to construct an initial distance matrix for the chip layout obtained by the layout obtaining unit based on gridding processing of block modules and based on distances between each block module and power pins in the chip layout on a power ground network;
a convolutional neural network processing unit for spatially encoding the initial distance matrix obtained by the matrix construction unit using a convolutional neural network to obtain an encoded distance matrix for a feature distribution representing a spatial relationship of current densities;
the normalization unit is used for carrying out normalization processing based on the maximum value on the characteristic value of each position in the coding distance matrix by taking the maximum value in the characteristic value of each position in the coding distance matrix obtained by the convolution neural network processing unit as the maximum value so as to obtain a current density characteristic matrix;
a resistance feature matrix constructing unit configured to construct a resistance feature matrix based on the encoding distance matrix obtained by the convolutional neural network processing unit;
a block resistance characteristic value characteristic matrix generating unit, configured to calculate a distribution of characteristic values of other positions in the resistance characteristic matrix in the horizontal direction and the vertical direction, where the distribution is obtained by the resistance characteristic matrix constructing unit, of each position, determine a connected domain of the position, and use the characteristic value of each position in the connected domain of the position as a block resistance characteristic value in the horizontal direction and the vertical direction corresponding to the position, so as to obtain a block resistance characteristic value characteristic matrix;
a voltage drop characteristic matrix generating unit, configured to calculate, based on the characteristic value at each position in the current density characteristic matrix obtained by the normalizing unit, the voltage drop characteristic value at each position in the block resistance characteristic value characteristic matrix obtained by the block resistance characteristic value characteristic matrix generating unit to obtain a voltage drop characteristic matrix; and
and the classification unit is used for inputting the voltage drop characteristic matrix obtained by the voltage drop characteristic matrix generation unit into a classifier so as to obtain a classification result for representing whether the chip layout meets the voltage drop condition of each module.
8. The system for optimizing layout of very large scale integrated circuit structure of claim 7, wherein said matrix construction unit is further configured to:
performing gridding processing on the chip layout to determine the grid position of each block module in the chip layout; and filling the distance between the corresponding block module and the power pin on a power ground network in the corresponding grid position to obtain the initial distance matrix.
9. An electronic device, comprising:
a processor; and
memory in which are stored computer program instructions which, when executed by the processor, cause the processor to carry out the method of optimizing a layout of a very large scale integrated circuit structure according to any of claims 1 to 6.
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