CN114064369A - Driving device, system and method for testing display module - Google Patents

Abstract

The embodiment of the invention discloses a driving device, a system and a method for testing a display module, wherein the driving device comprises an ARM and an FPGA; the ARM comprises: the system comprises an instruction transceiving control module, a display module parameter management module, an image data management module and an FPGA equipment management module; the instruction receiving and transmitting control module is used for receiving and responding to a display instruction signal sent by the upper computer, reading test image data from a data memory of the ARM and sending the test image data to the image data management module; the display module parameter management module is used for receiving a display instruction file sent by the upper computer, generating a test signal according to the display instruction file and sending the test signal to the FPGA equipment management module; the image data management module is used for sending the test image data to DDR4 in the FPGA for storage and managing and scheduling the test image data; the FPGA equipment management module is used for sending the test signal to the FPGA and receiving the test result data to the upper computer.

Description

Driving device, system and method for testing display module

Technical Field

The invention relates to the technical field of test display module driving equipment, in particular to driving equipment, a system and a method for testing a display module.

Background

In the current display test scheme, because of differences of different product lines of different manufacturers, the test driver board needs to be driven by an ARM (Advanced RISC Machines, ARM processor) master control cooperating with an FPGA (Field-Programmable Gate Array) to fulfill test requirements in different scenarios. The ARM is used as a traditional CPU and mainly responsible for image data management and implementation of upper-layer test logic, the FPGA is mainly responsible for image data transcoding and interface implementation, and the ARM and the FPGA are matched to achieve various test requirements. In such non-standard system architectures, images cannot be managed using standard data management methods available on the market. In addition, because of the dynamic nature of the test requirements, an easy-to-use, portable and highly scalable management system is needed.

Disclosure of Invention

The invention aims to provide driving equipment, a system and a method for testing a display module.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention provides a driving device for testing a display module, which comprises an ARM and an FPGA;

the ARM comprises: the system comprises an instruction transceiving control module, a display module parameter management module, an image data management module and an FPGA equipment management module;

wherein the content of the first and second substances,

the instruction receiving and transmitting control module is used for receiving and responding to a display instruction signal sent by the upper computer, reading test image data from a data memory of the ARM and sending the test image data to the image data management module;

the display module parameter management module is used for receiving a display instruction file sent by an upper computer, generating a test signal according to the display instruction file and sending the test signal to the FPGA equipment management module;

the image data management module is used for sending the test image data to DDR4 in the FPGA for storage and managing and scheduling the test image data;

the FPGA equipment management module is used for sending a test signal to the FPGA and receiving test result data to the upper computer;

and the FPGA calls the test image data in the DDR4 according to the test signal to perform display test on the display module to be tested, and sends the test result data fed back by the display module to be tested to the FPGA equipment management module.

In a specific embodiment, the instruction transceiver control module can also receive a read-write instruction signal sent by the upper computer to complete the read-write operation of the ARM device data.

In a specific embodiment, the ARM and the FPGA communicate and transmit data through a PCIe bus.

In a specific embodiment, the ARM further includes: an I2C interface, a UART interface, a USB interface, a GPIO interface and an SDcard interface.

In a specific embodiment, the instruction transceiving control module, the display module parameter management module and the FPGA device management module are all implemented by LUA scripting language.

In one embodiment, the test image data is divided into: sleep, wait for transfer, ready to transfer, wait for display, show, and error seven states.

In one particular embodiment of the present invention,

the image data management module carries out image processing on the image in the dormant state, so that the image in the dormant state is converted into an image in a waiting transfer state;

if the image data management module detects that the image converted into the waiting state from the dormant state is the existing image in the waiting state, the image state is converted back to the dormant state;

the image data management module is used for preprocessing the image waiting for transferring and then converting the image into an image ready for transmission;

if the image data management module detects that the image which is converted from the waiting transfer state into the ready-to-transmit state is the existing image in the ready-to-transmit state, the state of the image is converted back to the dormant state;

the image data management module transfers the image data to be transmitted from the ARM to the FPGA, and the state of the image transferred by the image data to be tested is a transfer state;

the image transferred to the FPGA enters a waiting display state, and if the image data management module detects that the image converted from the transfer state to the waiting display state is the existing image in the waiting display state, the state of the image is converted back to the dormant state;

when the FPGA calls test image data in the DDR4 according to the test signal to perform display test on the display module to be tested, the image data management module converts an image in a waiting display state into an image in a display state for the FPGA to call, if the image data management module detects that the image in the display state is a displayed image, the image in the display state is deleted in the DDR4 to release the memory space of the DDR4, and the called display state image which is displayed can be converted back to the image in the waiting display state.

In one particular embodiment of the present invention,

if the image data management module detects that the image waiting for the transition state has the condition of influencing the normal display of the image, the state of the image is converted into an error state;

and if the image data management module detects that the image in the transition state affects the normal display of the image, the image data management module converts the state of the image into an error state.

A second aspect of the present invention provides a driving system for testing a display module, the driving system comprising:

the drive equipment and the upper computer of the test display module;

and the upper computer is used for sending a display instruction signal and a display instruction file to the driving equipment, receiving test result data sent by the display module to be tested through the driving equipment, and analyzing to obtain a test result.

A third aspect of the present invention provides a driving method for driving a driving device for testing a display module, the method comprising:

the upper computer sends a display instruction signal to an instruction transceiving control module of the ARM and sends a display instruction file to a display module parameter management module of the ARM;

the instruction transceiving control module responds to the display instruction signal, reads test image data from a data memory of the ARM and sends the test image data to an image data management module of the ARM, and the image data management module sends the test image data to DDR4 in the FPGA for storage and manages and dispatches the test image data;

the display module parameter management module generates a test signal according to the display instruction file and sends the test signal to the FPGA equipment management module of the ARM, and the FPGA equipment management module sends the test signal to the FPGA;

the FPGA calls test image data in the DDR4 according to the test signal to perform display test on the display module to be tested;

the tested display module responds to the display test and feeds back test result data to the FPGA equipment management module through the FPGA;

the FPGA equipment management module sends the received test result data to an upper computer;

and the upper computer receives the test result data and analyzes the test result data to obtain a test result.

The invention has the following beneficial effects:

according to the driving device, the system and the method for testing the display module, provided by the invention, a large amount of image data is managed in a limited memory by using a high-expansibility image data management module, the management of an FPGA (field programmable gate array) memory is matched, a large amount of image display requirements are realized, and meanwhile, the service requirements of module testing are realized by using the LUA script, so that the development time of new requirements is greatly reduced, and the development cost is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are one embodiment of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a block diagram illustrating a driving system for testing a display module according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating an ARM component structure in a driving apparatus for testing a display module according to an embodiment of the present invention.

Fig. 3 is a schematic diagram illustrating image state switching when an image data management module of an ARM in a driving device of a test display module manages and schedules test image data according to an embodiment of the present invention.

Detailed Description

In order to make the technical solution of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. The present invention will be described in detail with reference to specific examples, but the present invention is not limited to these examples. Variations and modifications may be made by those skilled in the art without departing from the principles of the invention and should be considered within the scope of the invention.

In one aspect, this embodiment provides a driving system for testing a display module, as shown in fig. 1, the driving system includes: host computer and test display module's drive arrangement. The upper computer is used for sending a display instruction signal and a display instruction file to the driving equipment when the display test is carried out on the display module to be tested, receiving test result data sent by the display module to be tested through the driving equipment, and analyzing to obtain a test result.

The hardware of the driving device comprises a driving substrate, an ARM and an FPGA; the driving substrate is used for providing a channel for signal or data transmission, and the ARM and the FPGA are arranged on the driving substrate.

The input end of the ARM is connected with the upper computer, the ARM and the FPGA are communicated and transmit data through a PCIe bus, and the FPGA is connected with the display module to be tested through the display interface. The PCIe bus can reach 32Gbps bus bandwidth, the actual effective rate can reach 2GBps, and the data transmission requirements of the current and future large-size display modules are completely met. In addition, the ARM also expands a common I2C interface, a UART interface, a USB interface, a GPIO interface and an SDcard interface, and is used for realizing additional control requirements or storage capacity expansion.

As shown in fig. 2, the software of the ARM is mainly composed of four modules, including: the device comprises an instruction transceiving control module, a display module parameter management module, an image data management module and an FPGA equipment management module.

The ARM also comprises a data memory, and the data memory is used for storing test image data.

And the instruction receiving and transmitting control module is used for receiving and responding to a display instruction signal sent by the upper computer, reading test image data from a data memory of the ARM and sending the test image data to the image data management module. Those skilled in the art can understand that the display command signal is only an example, and the command transceiver control module can receive and respond to various command signals from different external interfaces and different protocols, for example, the command transceiver control module can also receive a read-write command signal sent by an upper computer, and complete read-write operation on ARM device data, for example, add new test image data to a data memory of the ARM, read or delete existing test image data in the data memory of the ARM, modify or add device parameters for deleting the ARM, and the like.

The display module parameter management module is used for receiving a display instruction file sent by an upper computer, generating a test signal according to the display instruction file and sending the test signal to the FPGA equipment management module.

The image data management module is used for sending the test image data to DDR4 in the FPGA for storage, managing and scheduling the test image data, and displaying more and larger image data under limited resources.

And the FPGA equipment management module is used for sending the test signal to the FPGA and receiving the test result data to the upper computer.

And the FPGA calls the test image data in the DDR4 according to the test signal to perform display test on the display module to be tested, and sends the test result data fed back by the display module to be tested to the FPGA equipment management module.

The instruction transceiving control module, the display module parameter management module and the FPGA equipment management module are tightly matched with the LUA script language layer, namely the instruction transceiving control module, the display module parameter management module and the FPGA equipment management module are all realized by the LUA script language, and information related to module detection service is realized and scheduled by the LUA script language. The LUA script is used for realizing the service requirement of the display module test, the development time of new requirements is greatly shortened, the workload of maintenance personnel is reduced, and the development cost is reduced.

The ARM reads the test image data from the data storage, then transports the test image data to a DDR4 memory space of the FPGA through a PCIe high-speed bus for storage and ready display, the DDR4 is used as a buffer space, and when the total amount of the test image data to be displayed is larger than the memory space of the DDR4, a complete management mechanism is needed to solve the contradiction between the limited memory and a large amount of test image data, and the response time of the test image data is ensured. The management of the image data depends on the image data management module. And for the image required to be displayed in the test, checking the state of the image object, selecting a processing method according to the actual situation, and finally displaying the test image data in the DDR4 memory.

As shown in fig. 3, the test image data is divided into: sleep, wait for transfer, ready to transfer, wait for display, show, and error seven states.

For the image in the hibernation state, the image data management module performs image processing on the image in the hibernation state so that the image in the hibernation state is converted into an image in a waiting-to-transition state.

If the image data management module detects that the image in the dormant state, which is converted into the waiting state, is the existing image in the waiting state, the state of the image is converted back to the dormant state, and if the image data management module detects that the image in the waiting state has image missing or image errors which affect the normal display of the image, the state of the image is converted into an error state.

For the image waiting to be transferred, the image data management module performs image preprocessing on the image waiting to be transferred and then converts the image waiting to be transferred into an image ready for transmission; the preprocessing can extract key information of the test image data and convert effective data of the image into a uniform RAW format, so that the subsequent steps can be conveniently processed.

If the image data management module detects that the image which is converted from the waiting transfer state into the ready-to-transfer state is the image which is in the existing ready-to-transfer state, the state of the image is converted back to the dormant state.

For the image in the ready-to-transmit state, the image data management module transfers the image data to be transmitted from the ARM to the FPGA, and the state of the image transferred by the image data to be tested is a transfer state; if the image data management module detects that the image in the transition state has image missing or image error and the like which affect the normal display of the image, the state of the image is changed into an error state.

And if the image data management module detects that the image converted from the transition state to the display waiting state is the existing image in the display waiting state, the image state is converted back to the dormant state.

When the FPGA calls test image data in the DDR4 according to the test signal to perform display test on the display module to be tested, the image data management module converts an image in a waiting display state into an image in a display state for the FPGA to call, and if the image data management module detects that the image in the display state is a displayed image, the image in the display state is deleted in the DDR4, namely, the image is converted into a dormant state, so that the memory space of the DDR4 is released. The display state image after being normally called to complete display is converted back to the image in the standby display state.

Herein, a state of the test image data stored in the ARM data memory without any operation is referred to as a sleep state. The transition back to the dormant state means that no operation is performed on the image, and the test image data of the image is only stored in the ARM data memory.

The image data management module applies data structures such as queues, linked lists, hash tables and the like, so that the module has high expansibility and high adaptability, and can be quickly realized by only modifying configuration parameters for larger image data or more complex images in the future.

In another aspect, the present invention provides a driving method for testing a driving device of a display module according to the foregoing description, the method including:

the upper computer sends a display instruction signal to an instruction transceiving control module of the ARM and sends a display instruction file to a display module parameter management module of the ARM;

the instruction transceiving control module responds to the display instruction signal, reads test image data from a data memory of the ARM and sends the test image data to an image data management module of the ARM, and the image data management module sends the test image data to DDR4 in the FPGA for storage and manages and dispatches the test image data; the data memory of the ARM can store a large amount of test image data, and the instruction transceiving control module reads the required test image data from the instruction memory according to the display instruction signal.

The display module parameter management module generates a test signal according to the display instruction file and sends the test signal to the FPGA equipment management module of the ARM, and the FPGA equipment management module sends the test signal to the FPGA; the FPGA equipment management module completes configuration of a display control register of the FPGA through a PCIe bus in a mode of sending a test signal.

And the FPGA calls the test image data in the DDR4 according to the test signal to perform display test on the display module to be tested, wherein the test image data is called according to the test signal, namely the display control register of the FPGA configured according to the test signal.

And the tested display module responds to the display test and feeds back test result data to the FPGA equipment management module through the FPGA.

And the FPGA equipment management module sends the received test result data to an upper computer.

And the upper computer receives the test result data and analyzes the test result data to obtain a test result.

The driving device, the system and the method for testing the display module provided by the embodiment can realize data transmission and management among different processors, manage a large amount of image data in a limited memory by using a high-expansibility image data management module, and realize a large amount of image display requirements by matching with the management of an FPGA memory. Meanwhile, the LUA script is used for realizing the service requirement of the module test, the development time of new requirements is greatly shortened, the workload of maintainers is reduced, the development cost is reduced, the test requirement is quickly realized, the transplanting and expandability are realized, the strategy of adjusting the image management by the service requirement can be installed in the future, and the response time of image display in a specific scene is accelerated.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Claims (10)

1. The driving equipment for testing the display module is characterized by comprising an ARM and an FPGA;

the ARM comprises: the system comprises an instruction transceiving control module, a display module parameter management module, an image data management module and an FPGA equipment management module;

wherein the content of the first and second substances,

the instruction receiving and transmitting control module is used for receiving and responding to a display instruction signal sent by the upper computer, reading test image data from a data memory of the ARM and sending the test image data to the image data management module;

the display module parameter management module is used for receiving a display instruction file sent by an upper computer, generating a test signal according to the display instruction file and sending the test signal to the FPGA equipment management module;

the image data management module is used for sending the test image data to DDR4 in the FPGA for storage and managing and scheduling the test image data;

the FPGA equipment management module is used for sending a test signal to the FPGA and receiving test result data to the upper computer;

and the FPGA calls the test image data in the DDR4 according to the test signal to perform display test on the display module to be tested, and sends the test result data fed back by the display module to be tested to the FPGA equipment management module.

2. The driving device according to claim 1, wherein the command transceiving control module is further capable of receiving a read-write command signal sent by an upper computer to complete read-write operation of ARM device data.

3. The driver device as claimed in claim 1, wherein the ARM and the FPGA communicate and transfer data therebetween via a PCIe bus.

4. The drive apparatus of claim 1, wherein the ARM further comprises: an I2C interface, a UART interface, a USB interface, a GPIO interface and an SDcard interface.

5. The driving device according to claim 1, wherein the command transceiving control module, the display module parameter management module and the FPGA device management module are implemented by LUA scripting language.

6. The driving apparatus according to claim 1, wherein the test image data is divided into: sleep, wait for transfer, ready to transfer, wait for display, show, and error seven states.

7. The drive apparatus according to claim 6,

the image data management module carries out image processing on the image in the dormant state, so that the image in the dormant state is converted into an image in a waiting transfer state;

if the image data management module detects that the image converted into the waiting state from the dormant state is the existing image in the waiting state, the image state is converted back to the dormant state;

the image data management module is used for preprocessing the image waiting for transferring and then converting the image into an image ready for transmission;

if the image data management module detects that the image which is converted from the waiting transfer state into the ready-to-transmit state is the existing image in the ready-to-transmit state, the state of the image is converted back to the dormant state;

the image data management module transfers the image data to be transmitted from the ARM to the FPGA, and the state of the image transferred by the image data to be tested is a transfer state;

the image transferred to the FPGA enters a waiting display state, and if the image data management module detects that the image converted from the transfer state to the waiting display state is the existing image in the waiting display state, the state of the image is converted back to the dormant state;

when the FPGA calls test image data in the DDR4 according to the test signal to perform display test on the display module to be tested, the image data management module converts an image in a waiting display state into an image in a display state for the FPGA to call, if the image data management module detects that the image in the display state is a displayed image, the image in the display state is deleted in the DDR4 to release the memory space of the DDR4, and the called display state image which is displayed can be converted back to the image in the waiting display state.

8. The drive apparatus according to claim 7,

if the image data management module detects that the image waiting for the transition state has the condition of influencing the normal display of the image, the state of the image is converted into an error state;

and if the image data management module detects that the image in the transition state affects the normal display of the image, the image data management module converts the state of the image into an error state.

9. The utility model provides a drive system of test display module assembly which characterized in that, drive system includes:

the drive device and the upper computer of the test display module set according to any one of claims 1 to 8;

and the upper computer is used for sending a display instruction signal and a display instruction file to the driving equipment, receiving test result data sent by the display module to be tested through the driving equipment, and analyzing to obtain a test result.

10. A method for driving a driving apparatus for testing a display module according to any one of claims 1 to 8, the method comprising:

the upper computer sends a display instruction signal to an instruction transceiving control module of the ARM and sends a display instruction file to a display module parameter management module of the ARM;

the instruction transceiving control module responds to the display instruction signal, reads test image data from a data memory of the ARM and sends the test image data to an image data management module of the ARM, and the image data management module sends the test image data to DDR4 in the FPGA for storage and manages and dispatches the test image data;

the display module parameter management module generates a test signal according to the display instruction file and sends the test signal to the FPGA equipment management module of the ARM, and the FPGA equipment management module sends the test signal to the FPGA;

the FPGA calls test image data in the DDR4 according to the test signal to perform display test on the display module to be tested;

the tested display module responds to the display test and feeds back test result data to the FPGA equipment management module through the FPGA;

the FPGA equipment management module sends the received test result data to an upper computer;

and the upper computer receives the test result data and analyzes the test result data to obtain a test result.

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