CN114050825A - Multi-mode self-adaptive internal and external reference clock multiplexing distribution circuit - Google Patents
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Abstract
The invention discloses a multi-mode self-adaptive internal and external reference clock multiplexing and distributing circuit which can self-adaptively multiplex internal and external reference clocks and has clock frequency division and distribution capacity. The invention is realized by the following technical scheme: the FPGA uses a locking indication signal containing PLL resources and a grounding debugging interface control circuit input mode signal as judgment conditions, judges whether a working mode and an external reference clock are normal or not, outputs a gating signal through logic judgment, and selects an internal or external reference clock to a secondary phase-locked loop circuit to realize the self-adaptive multiplexing of the internal and external reference clocks; and the final-stage clock distribution network divides the frequency of the output clock of the secondary phase-locked loop circuit, provides a frequency division clock for each circuit component of the board stage, respectively obtains the specific clock frequency of each group of circuit components, and multiplexes the reference clocks in various working modes such as an adaptive test mode, a normal working mode, an external reference abnormal mode, an external reference recovery mode and the like, and completes the frequency division and distribution of the output clock of each circuit component in the module.
Description
Technical Field
The invention relates to a module-level multi-mode self-adaptive internal and external reference clock multiplexing distribution circuit and a method.
Background
In the integrated system, each function processing module is composed of a dedicated module and a general module, and each function processing module of the microcontroller has a complex clock system and usually has the requirements of homologous, common-frequency and same-phase clocks, so the integrated system usually sets a uniform clock reference source as a clock reference to be distributed to each module in the system. The coordination work among the functional modules such as the multifunctional clock generator, the phase-locked loop, the frequency-locked loop, the crystal oscillator system and the like in the clock system can provide a stable clock source for the MCU and various peripheral components on the module. In the existing system, a general module often sets a reference clock source working mode, and internal and external clocks are switched by switching a board-level management firmware program or replacing a resistor connection mode, so that the switching of the requirements of the internal and external clocks in a debugging mode and a complete machine application mode can be realized. Meanwhile, the frequency conversion is carried out in the module through analog phase-locked loop PLL resources of the programmable gate array FPGA, the FPGA is used for realizing the frequency division and the multi-path output of the high-frequency clock, the clock frequency actually used by the board level is obtained, and the clock frequency is distributed to subsequent circuits. A phase locked loop PLL is a closed loop control system that maintains a fixed phase relationship between the generated signal and the reference signal. In high speed applications, the clock distribution system requires a high speed and low noise phase locked loop to achieve the clock speed requirements. However, in the existing system, once the reference source module works abnormally, all functions have the possibility of failure. In addition, PLL resource output clock indexes of FPGA are not good, and when a clock is provided for a clock sensitive device, satisfactory technical indexes cannot be obtained. If the clock switches frequently and does not switch at reset, and a short error cannot be tolerated in the design, a synchronous design must be used to ensure that the registers do not violate timing, glitches on the clock signal, etc.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to improve the robustness of the system and improve the quality of the clock in the module, and provides a multi-mode self-adaptive internal and external reference clock multiplexing distribution circuit and a multi-mode self-adaptive internal and external reference clock multiplexing distribution method, which can realize that the module can self-adaptively multiplex the internal and external reference clocks in a debugging mode, a normal working mode, an external reference abnormal mode and an external reference recovery mode, have the capacity of frequency conversion and frequency multiplication of a high-spurious index clock signal and frequency division distribution of the clock, and ensure that a system functional thread does not fail within a certain range.
In order to achieve the above object, the present invention provides a multi-mode adaptive internal and external reference clock multiplexing distribution circuit, including: a secondary phase-locked loop circuit and a final clock distribution network, connected in series to the primary clock selection circuit, characterized by: the primary clock selection circuit takes a debugging interface control signal and an external reference clock Ext _ CLK as input signals, the Ext _ CLK1 is used as the input of a clock phase-locked loop (PLL) resource of an internally connected Field Programmable Gate Array (FPGA), the FPGA takes a locking indication Lock signal containing the PLL resource and a grounding debugging interface control circuit input mode T _ mode signal as a judgment condition, judges whether a working mode and the external reference clock are normal or not, outputs a gating signal Sel through logic judgment, selects the external reference clock Ext _ CLK2 or the internal reference clock Int _ CLK to a secondary phase-locked loop circuit, realizes the self-adaptive multiplexing of the internal and external reference clocks, and performs frequency conversion and frequency multiplication on the reference clock to a user clock; and the final-stage clock distribution network divides the frequency of the output clock of the secondary phase-locked loop circuit, provides a frequency division clock for each circuit component of the board stage, respectively obtains the specific clock frequency of each group of circuit components, and multiplexes the reference clocks in various working modes such as an adaptive test mode, a normal working mode, an external reference abnormal mode, an external reference recovery mode and the like, and completes the frequency division and distribution of the output clock of each circuit component in the module.
Compared with the prior art, the invention has the following beneficial effects:
1) the invention aims to improve the robustness of the system and the quality of the clock in the module, and adopts a primary clock selection circuit, a secondary phase-locked loop circuit and a final-stage clock distribution network. The primary clock selection circuit realizes the self-adaptive multiplexing of the internal and external reference clocks in a debugging mode, a normal working mode, an external reference abnormal mode and an external reference recovery mode. The primary clock selection circuit takes a debugging interface control signal and an external reference clock as input signals, realizes judgment through FPGA logic, can support self-adaptive internal and external reference clock multiplexing of a module in a debugging mode, a normal working mode, an external reference abnormal mode, an external reference recovery mode and other working modes, and avoids the change of a module firmware program or the replacement of resistance connection.
2) On the basis of a primary clock selection circuit, a debugging interface control signal and an external reference clock are used as input signals; using the Ext _ CLK1 as the input of an internal clock phase-locked loop (PLL) resource, using a locking indication Lock signal and an input mode T _ mode' signal of the PLL as judgment conditions by the FPGA to judge whether a working mode and an external reference clock are normal or not, outputting a gating control signal Sel through logic judgment, selecting the external clock Ext _ CLK2 or Int _ CLK to a secondary phase-locked loop circuit, realizing the self-adaptive multiplexing of the internal and external reference clocks, and carrying out frequency conversion and frequency multiplication on the reference clock to a user clock; the frequency conversion and frequency multiplication of high-quality clock signals in the module and the distribution of clock signals of circuit components in the module are realized by adding a secondary phase-locked loop circuit and a final-stage clock distribution network. The method has the capabilities of high spurious index clock signal frequency conversion frequency multiplication and clock frequency division distribution, and ensures that each functional thread in the integrated system does not lose effectiveness within a certain range.
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The technical solution of the present invention is further described below with reference to the accompanying drawings, but the present invention is not limited to the following.
FIG. 1 is a schematic diagram of a multi-mode adaptive internal and external reference clock multiplexing distribution circuit according to the present invention;
FIG. 2 is a state machine diagram of the multi-mode adaptive internal and external reference clock multiplexing distribution method of the present invention;
FIG. 3 is a flow chart of a multi-mode adaptive internal and external reference clock multiplexing distribution method of the present invention;
Detailed Description
See fig. 1. In an exemplary preferred embodiment described below, a multi-mode adaptive internal and external reference clock multiplexing distribution circuit includes: and a secondary phase-locked loop circuit and a final-stage clock distribution network which are connected in sequence with the primary clock selection circuit. The primary clock selection circuit takes a debugging interface control signal and an external reference clock Ext _ CLK as input signals, the Ext _ CLK1 is used as the input of a clock phase-locked loop (PLL) resource of an internally connected Field Programmable Gate Array (FPGA), the FPGA takes a locking indication Lock signal containing the PLL resource and a grounding debugging interface control circuit input mode T _ mode signal as a judgment condition, judges whether a working mode and the external reference clock are normal or not, outputs a gating signal Sel through logic judgment, selects the external reference clock Ext _ CLK2 or the internal reference clock Int _ CLK to a secondary phase-locked loop circuit, realizes the self-adaptive multiplexing of the internal and external reference clocks, and performs frequency conversion and frequency multiplication on the reference clock to a user clock; and the final-stage clock distribution network divides the frequency of the output clock of the secondary phase-locked loop circuit, provides a frequency division clock for each circuit component of the board stage, respectively obtains the specific clock frequency of each group of circuit components, and multiplexes the reference clocks in various working modes such as an adaptive test mode, a normal working mode, an external reference abnormal mode, an external reference recovery mode and the like, and completes the frequency division and distribution of the output clock of each circuit component in the module.
The primary clock selection circuit includes: the system comprises a clock one-to-two circuit connected with an Ext _ CLK signal input module, a debugging interface control circuit, a programmable gate array (FPGA) connected with the clock one-to-two circuit, and a clock one-to-two circuit connected with the output end of the FPGA, wherein the clock one-to-two circuit comprises: the debugging interface controls to input a T _ mode signal into the FPGA through a discrete control line, the Ext _ CLK signal input module inputs an external reference clock Ext _ CLK into a clock one-to-two circuit, and the generated Ext _ CLK1 and Ext _ CLK2 are respectively provided for the FPGA and a clock one-to-one circuit; the FPGA uses the Ext _ clk1 as the input of an internal clock phase-locked loop (PLL) resource, uses a locking indication Lock signal and a T _ mode signal of the PLL as a judgment condition, judges whether a working mode and an external reference clock are normal or not, and outputs a gating signal Sel as the input of the clock alternative circuit.
An alternative circuit: according to the internal reference clock Int _ CLK output by the high-precision constant-temperature crystal oscillator or the temperature compensation crystal oscillator, the external reference clock Ext _ CLK2 or the internal reference clock Int _ CLK is selected by utilizing the gating control signal Sel of the FPGA, and the frequency consistency of the internal reference clock and the external reference clock is ensured.
In a debugging mode, when single-module debugging is needed, an external reference clock does not exist at the moment, a debugging interface control circuit controls a debugging interface to close a switch, an input mode T _ mode signal is '0', an internal logic output Sel signal of the FPGA is '0', and a clock gates an internal reference clock Int _ CLK.
In a normal operating mode: the debugging interface control circuit is used for controlling the opening of a debugging interface control switch, and a control signal is '1'; when the external reference clock is normal and the Lock signal output of the PLL in the FPGA is '1', the Sel signal output by the logic in the FPGA is '1', and the clock alternative circuit gates the external reference clock.
In the external reference abnormal mode: the debugging interface control circuit is used for controlling the opening of a debugging interface control switch, and a control signal is '1'; when the external reference clock is abnormal and the Lock signal output of the PLL in the FPGA is '0', the Sel signal output by the logic in the FPGA is '0', and the internal reference clock is selected by the clock alternative circuit.
In the external reference recovery mode: when the external reference abnormal mode is adopted, the input external reference clock Ext _ CLK is recovered to be normal, the Lock signal output of the PLL in the FPGA is '1', and at the moment, the Ext _ CLK2 signal input module is used for gating the external reference clock Ext _ CLK2 through the clock alternative circuit, so that the self-adaptive internal and external reference clock multiplexing is realized.
The secondary phase-locked loop circuit includes: the clock frequency divider 0 of the clock alternative circuit is connected with the clock phase discriminator in series, and the voltage-controlled oscillator, the clock phase discriminator and the loop filter of the parallel loop and the clock frequency divider 1 are formed through the voltage-controlled oscillator connected with the clock phase discriminator in series, so that a standard phase-locked loop circuit is formed.
Frequency f generated by clock alternative circuitiObtaining a reference frequency f after the clock frequency divider 0refWith the feedback frequency f of the clock divider 1fdRespectively sending them to two reverse input ends of a clock frequency discriminator, outputting a DC voltage reflecting the quotient of the two, and passing through a low-passFilterAfter the LPF filters the AC component, the AC component is provided to the VCO to output a frequency signal foutFrequency multiplication of voltage-controlled oscillator, automatic tracking and capturing frequency of input signal by phase-locked loop, and main frequency division of output to generate FvcoPressure controlOutput frequency f of oscillatoroutWithin the controllable range of the voltage-controlled oscillator, the common multiple of the required working frequency of each circuit component of the board level.
The frequency multiplication operation of the main frequency of the phase-locked loop PLL is set by a digital phase-locked loop DPLL through which the clock outputs a frequency F of a larger multipleCLKWhen the external clock FinWhen the clock enters a phase-locked loop PLL, the clock frequency divider 0 performs pre-frequency division processing on the clock to obtain a reference signal FrefA signal for a subsequent divided phase reference; frefWill enter the clock phase discriminator for the first time to finish FrefAnd FvcoThe voltage-controlled oscillator converts the control signal into a voltage signal which is circulated to the input of the clock divider 1 by the loop filter, FvcoInto a clock phase detector and FrefAnd comparing the phase difference with the frequency difference, if the phase difference is different, continuing to enter a cycle, if the phase difference is not different, stopping sending a clock signal by the clock phase discriminator, enabling the phase-locked loop to enter a phase locking state, and when the phase-locked loop enters the phase locking state, outputting the output of the voltage-controlled oscillator VCO to an MPLL register or a clock power supply management unit UPLL through the rear frequency divider 1.
The last-stage clock distribution network includes: a clock frequency divider 2 communicated with the voltage-controlled oscillator, a clock-one-multiple frequency divider and a multi-stage frequency divider connected in series with the clock frequency divider 2. The clock-one-to-multiple frequency divider divides the frequency of the output clock of the secondary phase-locked loop circuit through the multistage frequency divider, the multistage frequency divider provides clock frequency division and distribution for each circuit component in the module, the clock is distributed for each circuit component on the board level, and the specific clock frequency of each group of circuit components is obtained respectively.
The final clock distribution network provides clock division and distribution circuitry for each circuit component within the module, including clock divide-by-many and multi-stage clock dividers. The output clock of the secondary phase-locked loop circuit is divided by the clock distribution circuits 2, 3, 4 and the like to respectively obtain the specific clock frequency of each group of circuit components.
See fig. 2. When the module is powered on until the FPGA program is loaded, the module is in a powered-on state; if the debugging control T _ mode signal is '0', the state is switched to a debugging mode state, and at the moment, an internal reference clock is selected; after the system is powered on, if the T _ mode signal is '1' and the external reference clock is normal, the system is switched from a system power-on state to a normal working mode state, and the external reference clock is selected at the moment; once the supply of the external reference clock is interrupted, the system is switched in a self-adaptive mode, the state of a normal working mode is switched to an external reference abnormal mode, and at the moment, the internal reference clock is selected; if the external reference clock is recovered and supplied, the system is switched in a self-adaptive mode, the state of the external reference abnormal mode is switched to the external reference recovery mode, and the external reference clock is selected at the moment; if the system is powered on, the T _ mode is '1' but the external reference clock is abnormal, the system is directly switched to the external reference abnormal normal working state from the system power-on state, and the internal reference clock is selected at the moment.
See fig. 3. After the module is powered on, the FPGA firstly finishes program loading, configures configuration parameters such as the output frequency of a secondary phase-locked loop, clock frequency division 0, clock frequency division 1 and the like according to specific requirements of a board level, and finishes clock frequency doubling required by a user; then configuring frequency division parameters of a last-stage clock frequency division equal frequency division circuit 2, an equal frequency division circuit 3, an equal frequency division circuit 4 and the like to complete clock frequency division of the module-stage circuit assembly; judging the value of an input debugging interface control T _ mode signal, if the value is '0', outputting Sel to be '0', and using an internal reference clock at the moment; if the clock signal is '1', judging a Lock locking indication signal of the PLL resource in the FPGA, if the clock signal is '0', using an internal reference clock, and if the clock signal is '1', using an external reference clock. The Lock locking indication signal is continuously monitored in the power-on process, once the level of the Lock signal changes, the Sel output signal is correspondingly changed, and the self-adaptive multiplexing of the internal clock and the external clock is realized.
The present invention is not limited to the above-described embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements are also considered to be within the scope of the present invention. Those not described in detail in this specification are within the skill of the art.
Claims (10)
1. A multi-mode adaptive internal and external reference clock multiplexing distribution circuit comprising: a secondary phase-locked loop circuit and a final clock distribution network, connected in series to the primary clock selection circuit, characterized by: the primary clock selection circuit takes a debugging interface control signal and an external reference clock Ext _ CLK as input signals, the Ext _ CLK1 is used as the input of a clock phase-locked loop (PLL) resource of an internally connected Field Programmable Gate Array (FPGA), the FPGA takes a locking indication Lock signal containing the PLL resource and a grounding debugging interface control circuit input mode T _ mode signal as a judgment condition, judges whether a working mode and the external reference clock are normal or not, outputs a gating signal Sel through logic judgment, selects the external reference clock Ext _ CLK2 or the internal reference clock Int _ CLK to a secondary phase-locked loop circuit, realizes the self-adaptive multiplexing of the internal and external reference clocks, and performs frequency conversion and frequency multiplication on the reference clock to a user clock; the final-stage clock distribution network divides the frequency of the output clock of the secondary phase-locked loop circuit, provides a frequency division clock for each circuit component of the board stage, respectively obtains the specific clock frequency of each group of circuit components, and a self-adaptive test mode, a normal working mode, an external reference abnormal mode and an external reference recovery mode, multiplexes reference clocks under various working modes, and completes the frequency division and distribution of the output clock of each circuit component in the module.
2. The multi-mode adaptive internal and external reference clock multiplexing distribution circuit of claim 2, wherein: the debugging interface controls to input a T _ mode signal into the FPGA through a discrete control line, the Ext _ CLK signal input module inputs an external reference clock Ext _ CLK into a clock one-to-two circuit, and the generated Ext _ CLK1 and Ext _ CLK2 are respectively provided for the FPGA and a clock one-to-one circuit; the FPGA uses the Ext _ clk1 as the input of an internal clock phase-locked loop (PLL) resource, uses a locking indication Lock signal and a T _ mode signal of the PLL as a judgment condition, judges whether a working mode and an external reference clock are normal or not, and outputs a gating signal Sel as the input of the clock alternative circuit.
3. The multi-mode adaptive internal and external reference clock multiplexing distribution circuit of claim 1, wherein: in a debugging mode, when single-module debugging is needed, an external reference clock does not exist at the moment, a debugging interface control circuit debugs an interface control switch to be closed, an input mode T _ mode signal is '0', an internal logic output Sel signal of the FPGA is '0', and a clock gates an internal reference clock Int _ CLK; in a normal operating mode: the debugging interface control circuit is used for controlling the opening of a debugging interface control switch, and a control signal is '1'; when the external reference clock is normal and the Lock signal output of the PLL in the FPGA is '1', the Sel signal output by the logic in the FPGA is '1', and the clock alternative circuit gates the external reference clock.
4. The multi-mode adaptive internal and external reference clock multiplexing distribution circuit of claim 1, wherein: in the external reference abnormal mode: the debugging interface control circuit is used for controlling the opening of a debugging interface control switch, and a control signal is '1'; when the external reference clock is abnormal and the Lock signal output of PLL in the FPGA is '0', the Sel signal output by logic in the FPGA is '0', and the internal reference clock is selected by the clock alternative circuit; in the external reference recovery mode: when the external reference abnormal mode is in, the input external reference clock Ext _ CLK is recovered to be normal, the Lock signal output of the PLL in the FPGA is '1', at the moment, the Ext _ CLK2 signal is input into the module again through the clock alternative circuit, and the external reference clock Ext _ CLK2 is gated, so that the self-adaptive internal and external reference clock multiplexing is realized.
5. The multi-mode adaptive internal and external reference clock multiplexing distribution circuit of claim 1, wherein: the secondary phase-locked loop circuit includes: the clock frequency divider 0 of the clock alternative circuit is connected with the clock phase discriminator in series, and the voltage-controlled oscillator, the clock phase discriminator and the loop filter of the parallel loop and the clock frequency divider 1 are formed through the voltage-controlled oscillator connected with the clock phase discriminator in series, so that a standard phase-locked loop circuit is formed.
6. The multi-mode adaptive internal and external reference clock multiplexing distribution circuit of claim 5, wherein: clock alternative powerFrequency f of the circuit generationiObtaining a reference frequency f after the clock frequency divider 0refWith the feedback frequency f of the clock divider 1fdRespectively sending them to two reverse input ends of a clock frequency discriminator, outputting a DC voltage reflecting the quotient of the two, and passing through a low-passFiltering Device for cleaning the skinAfter the LPF filters the AC component, the AC component is provided to the VCO to output a frequency signal foutFrequency multiplication of voltage-controlled oscillator, automatic tracking and capturing frequency of input signal by phase-locked loop, and main frequency division of output to generate FvcoOutput frequency f of voltage controlled oscillatoroutWithin the controllable range of the voltage-controlled oscillator, the common multiple of the required working frequency of each circuit component of the board level.
7. The multi-mode adaptive internal and external reference clock multiplexing distribution circuit of claim 1, wherein: the clock outputs a greater multiple of frequency F through a phase-locked loop PLLCLKWhen the external clock FinWhen the clock enters a phase-locked loop PLL, the clock frequency divider 0 performs pre-frequency division processing on the clock to obtain a reference signal FrefA signal for a subsequent divided phase reference; frefWill enter the clock phase discriminator for the first time to finish FrefAnd FvcoThe voltage-controlled oscillator converts the control signal into a voltage signal which is circulated to the input of the clock divider 1 by the loop filter, FvcoInto a clock phase detector and FrefAnd comparing the phase difference with the frequency difference, if the phase difference is different, continuing to enter a cycle, if the phase difference is not different, stopping sending a clock signal by the clock phase discriminator, enabling the phase-locked loop to enter a phase locking state, and when the phase-locked loop enters the phase locking state, outputting the output of the voltage-controlled oscillator VCO to an MPLL register or a clock power supply management unit UPLL through the rear frequency divider 1.
8. The multi-mode adaptive internal and external reference clock multiplexing distribution circuit of claim 1, wherein: the last-stage clock distribution network includes: the clock frequency divider 2 is communicated with the voltage-controlled oscillator, and the clock one-to-many frequency divider and the multi-stage frequency divider are connected with the clock frequency divider 2 in series, the clock one-to-many frequency divider divides the frequency of the output clock of the secondary phase-locked loop circuit through the multi-stage frequency divider, the multi-stage frequency divider provides clock frequency division and distribution for each circuit component in the module, distributes the clock for each circuit component on the board level, and obtains the specific clock frequency of each circuit component respectively.
9. The multi-mode adaptive internal and external reference clock multiplexing distribution circuit of claim 1, wherein: when the module is powered on until the FPGA program is loaded, the module is in a powered-on state; if the debugging control T _ mode signal is '0', the state is switched to a debugging mode state, and at the moment, an internal reference clock is selected; after the system is powered on, if the T _ mode signal is '1' and the external reference clock is normal, the system is switched from a system power-on state to a normal working mode state, and the external reference clock is selected at the moment; once the supply of the external reference clock is interrupted, the system is switched in a self-adaptive mode, the state of a normal working mode is switched to an external reference abnormal mode, and at the moment, the internal reference clock is selected; if the external reference clock is recovered and supplied, the system is switched in a self-adaptive mode, the state of the external reference abnormal mode is switched to the external reference recovery mode, and the external reference clock is selected at the moment; if the system is powered on, the T _ mode is '1' but the external reference clock is abnormal, the system is directly switched to the external reference abnormal normal working state from the system power-on state, and the internal reference clock is selected at the moment.
10. The multi-mode adaptive internal and external reference clock multiplexing distribution circuit of claim 1, wherein: after the module is powered on, the FPGA firstly finishes program loading, configures configuration parameters such as the output frequency of a secondary phase-locked loop, clock frequency division 0, clock frequency division 1 and the like according to specific requirements of a board level, and finishes clock frequency doubling required by a user; then configuring frequency division parameters of a last-stage clock frequency division equal frequency division circuit 2, an equal frequency division circuit 3, an equal frequency division circuit 4 and the like to complete clock frequency division of the module-stage circuit assembly; judging the value of an input debugging interface control T _ mode signal, if the value is '0', outputting Sel to be '0', and using an internal reference clock at the moment; if the current level is '1', judging a Lock locking indication signal of a PLL resource in the FPGA, if the current level is '0', using an internal reference clock, if the current level is '1', using an external reference clock, continuously monitoring the Lock locking indication signal in the power-on process, and once the level of the Lock signal changes, changing a Sel output signal correspondingly to realize the self-adaptive multiplexing of the internal clock and the external clock.
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| 涂申俊等: "全数字化PET系统时间信号基准模块设计", 《计算机与数字工程》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114637370A (en) * | 2022-03-25 | 2022-06-17 | 北京中科飞鸿科技股份有限公司 | Circuit, device and method for switching internal and external different frequency reference clock signals |
| CN114637370B (en) * | 2022-03-25 | 2024-02-20 | 北京中科飞鸿科技股份有限公司 | Internal and external different frequency reference clock signal switching circuit, device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114050825B (en) | 2023-02-28 |
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