CN114050167A

CN114050167A - Medical field-oriented semiconductor silicon-based hybrid imaging chip and preparation method thereof

Info

Publication number: CN114050167A
Application number: CN202210034379.2A
Authority: CN
Inventors: 刘伟; 贾波; 何兵; 张�杰
Original assignee: Rocket Force University of Engineering of PLA
Current assignee: Rocket Force University of Engineering of PLA
Priority date: 2022-01-13
Filing date: 2022-01-13
Publication date: 2022-02-15
Anticipated expiration: 2042-01-13
Also published as: CN114050167B

Abstract

The application provides a silica-based hybrid imaging chip of semiconductor towards medical field and preparation method thereof, the hybrid imaging chip includes semiconductor substrate and at least one pixel unit, every pixel unit includes the microbridge structure, electricity connection support column and beam structure, the microbridge structure includes from the top down and stacks gradually the last dielectric layer of arranging, first semiconductor layer, the second semiconductor layer, third semiconductor layer and lower dielectric layer, the thickness of second semiconductor layer is greater than the thickness of first semiconductor layer, the thickness of second semiconductor layer is greater than the thickness of third semiconductor layer, through setting up noise abatement like this.

Description

Medical field-oriented semiconductor silicon-based hybrid imaging chip and preparation method thereof

Technical Field

The application relates to the technical field of semiconductors, in particular to a semiconductor silicon-based hybrid imaging chip for the medical field and a preparation method thereof.

Background

A hybrid imaging chip relates to the technical field of semiconductors, and is a thermal detector.

However, when a sensitive layer for detecting the intensity of infrared light is provided in the microbridge structure, a large noise exists in a signal detected on the sensitive layer.

Disclosure of Invention

An embodiment of the present application provides a silicon-based hybrid imaging chip of semiconductor towards medical treatment field, and hybrid imaging chip includes semiconductor substrate and at least one pixel unit, and every pixel unit includes: the micro-bridge structure, the electric connection supporting column and the beam structure;

the electric connection supporting column is positioned on the semiconductor substrate, supports the micro-bridge structure through the beam structure and leads a first electric signal on the micro-bridge structure out of the semiconductor substrate;

the micro-bridge structure comprises an upper dielectric layer, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a lower dielectric layer which are sequentially arranged in a stacking mode from top to bottom; the thickness of the second semiconductor layer is greater than that of the first semiconductor layer, and the thickness of the second semiconductor layer is greater than that of the third semiconductor layer.

In an embodiment, the ion doping concentration of the second semiconductor layer is greater than that of the first semiconductor layer, and the ion doping concentration of the second semiconductor layer is greater than that of the third semiconductor layer.

In one embodiment, the first semiconductor layer and the third semiconductor layer are N-type semiconductor layers, and the second semiconductor layer is a P-type semiconductor layer.

In one embodiment, the micro-bridge structure is provided with a first electrode hole and a second electrode hole;

the first electrode hole is positioned in the upper dielectric layer, the first semiconductor layer and the second semiconductor layer; the second electrode hole is positioned in the upper dielectric layer, the first semiconductor layer and the second semiconductor layer;

the micro-bridge structure further comprises a first electrode and a second electrode; the first electrode is positioned in the first electrode hole, and the second electrode is positioned in the second electrode hole.

In one embodiment, the first electrode hole and the second electrode hole are in an inverted trapezoid shape;

the distance from the bottom of the first electrode hole to the lower surface of the third semiconductor layer is greater than a first preset distance threshold; the distance from the bottom of the second electrode hole to the lower surface of the third semiconductor layer is greater than a first preset distance threshold;

the contact surface between the first electrode and the first semiconductor layer is lower than the upper surface of the first semiconductor layer; and the contact surface between the second electrode and the first semiconductor layer is lower than the upper surface of the first semiconductor layer.

In one embodiment, the beam structure includes a first serpentine beam, a second serpentine beam, a third serpentine beam, and a fourth serpentine beam; the electric connection supporting column comprises a first supporting column, a second supporting column, a third supporting column, a fourth supporting column, a fifth supporting column and a sixth supporting column;

the first and second serpentine beams are located in a first plane, the third and fourth serpentine beams are located in a second plane, and the microbridge structure is located in a third plane; the third plane, the second plane and the first plane are arranged from top to bottom in sequence; the projection of the first serpentine beam on the semiconductor substrate is partially overlapped with the projection of the third serpentine beam on the semiconductor substrate, and the projection of the second serpentine beam on the semiconductor substrate is partially overlapped with the projection of the fourth serpentine beam on the semiconductor substrate;

the first end of the first supporting column is positioned on the semiconductor substrate, the second end of the first supporting column is connected with the first end of the first serpentine beam, the second end of the first serpentine beam is connected with the first end of the third supporting column, the second end of the third supporting column is connected with the first end of the third serpentine beam, the second end of the third serpentine beam is connected with the first end of the fifth supporting column, and the second end of the fifth supporting column supports the micro-bridge structure;

the first end of the second supporting column is located on the semiconductor substrate, the second end of the second supporting column is connected with the first end of the second serpentine beam, the second end of the second serpentine beam is connected with the first end of the fourth supporting column, the second end of the fourth supporting column is connected with the first end of the fourth serpentine beam, the second end of the fourth serpentine beam is connected with the first end of the sixth supporting column, and the second end of the sixth supporting column supports the micro-bridge structure.

Another embodiment of the present application provides a method for preparing a semiconductor silicon-based hybrid imaging chip for the medical field, including:

obtaining a semiconductor substrate, and forming a beam structure on the semiconductor substrate;

forming a micro-bridge structure on the beam structure; wherein forming the microbridge structure on the beam structure includes: forming a third sacrificial layer on the beam structure, and sequentially depositing a dielectric material and a semiconductor material on the third sacrificial layer to form a lower dielectric layer and a semiconductor base layer; forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer which are sequentially arranged from top to bottom in the semiconductor base layer through an ion implantation process; depositing a dielectric material on the semiconductor base layer to form an upper dielectric layer;

electrical connection support posts are formed on the microbridge structure.

In one embodiment, forming the microbridge structure on the beam structure further comprises:

photoetching the upper dielectric layer and the semiconductor base layer to form a first electrode hole in an inverted trapezoid shape and a second electrode hole in an inverted trapezoid shape;

continuing to deposit metal materials in the first electrode hole and the second electrode hole, and removing the metal materials in the first electrode hole close to the upper surface of the semiconductor base layer and the metal materials in the second electrode hole close to the upper surface of the semiconductor base layer to form a first base of the first electrode and a second base of the second electrode;

continuing to deposit dielectric materials in the first electrode hole and the second electrode hole, removing the dielectric materials above the first electrode hole and the dielectric materials above the second electrode hole, and exposing the first base of the first electrode and the second base of the second electrode;

the deposition of the metal material is continued and the patterning is performed to form a first lead-out portion of the first electrode and a second lead-out portion of the second electrode.

In an embodiment, the photoetching of the upper dielectric layer and the semiconductor substrate to form a first electrode hole in an inverted trapezoid shape and a second electrode hole in an inverted trapezoid shape specifically includes:

forming a photoresist layer on the semiconductor base layer, controlling the focusing positions of the first light beam and the second light beam to be in the photoresist layer, and controlling the distance between the first light beam and the upper surface of the photoresist layer to be less than half of the thickness of the photoresist layer;

controlling a first light beam to irradiate the photoresist layer through a first through hole of the upper photoetching plate so as to form a first electrode hole at the position of the first through hole; and controlling the second light beam to irradiate the photoresist layer through the second through hole of the upper photoetching plate so as to form a second electrode hole at the position of the second through hole.

In one embodiment, forming a beam structure on a semiconductor substrate specifically includes:

sequentially forming a first sacrificial layer, a first serpentine beam, a second sacrificial layer, a third serpentine beam and a fourth serpentine beam on a semiconductor substrate;

correspondingly, forming an electric connection support column on the micro-bridge structure, specifically comprising:

a first main groove, a second main groove, a third main groove, a fourth main groove, a fifth main groove and a sixth main groove are formed in the microbridge structure, the first main groove, the third main groove and the fifth main groove are located above the first serpentine beam, the second main groove, the fourth main groove and the sixth main groove are located above the second serpentine beam, and the bottom of the first main groove and the bottom of the sixth main groove extend to the lower surface of the third sacrificial layer;

a first sub-groove is formed in the position, corresponding to the first main groove, of the third serpentine beam, a second sub-groove is formed in the position, corresponding to the second main groove, of the fourth serpentine beam, a third sub-groove is formed in the position, corresponding to the third main groove, of the third serpentine beam, a fourth sub-groove is formed in the position, corresponding to the fourth main groove, of the fourth serpentine beam, and the bottom of the first sub-groove and the bottom of the fourth sub-groove extend to the lower surface of the second sacrificial layer;

a first slave groove is formed in the position, corresponding to the first sub-groove, of the first serpentine beam, a second slave groove is formed in the position, corresponding to the second sub-groove, of the second serpentine beam, and the bottom of the first slave groove and the bottom of the second slave groove both extend to the lower surface of the first sacrificial layer;

and forming a conductive structure consisting of multiple layers of thin films in the first slave groove, the second slave groove, the third sub-groove, the fourth sub-groove, the fifth main groove and the sixth main groove to obtain a first supporting column, a second supporting column, a third supporting column, a fourth supporting column, a fifth supporting column and a sixth supporting column.

The application provides a semiconductor silicon-based hybrid imaging chip oriented to the medical field and a preparation method thereof. When carriers flow in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, the flow rate of the carriers in the second semiconductor layer is at least one order of magnitude larger than that in the first semiconductor layer, and the flow rate of the carriers in the second semiconductor layer is at least one order of magnitude larger than that in the third semiconductor layer. Through the arrangement, the current carriers mainly flow in the second semiconductor layer, the flow of the current carriers on the first semiconductor layer is reduced, the scattering effect on the interface between the first semiconductor layer and the upper dielectric layer is reduced, and the noise intensity is reduced or the noise is eliminated.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic view of a microbridge structure provided herein;

fig. 2 is a schematic structural diagram of a semiconductor silicon-based hybrid imaging chip for the medical field according to an embodiment of the present application;

fig. 3A is a schematic structural diagram of a semiconductor silicon-based hybrid imaging chip facing the medical field according to the embodiment of fig. 2, the structural diagram being on a first plane;

fig. 3B is a schematic structural diagram of a second plane of the semiconductor silicon-based hybrid imaging chip facing the medical field according to the embodiment shown in fig. 2;

fig. 3C is a schematic structural diagram of a semiconductor silicon-based hybrid imaging chip facing the medical field in a third plane according to the embodiment shown in fig. 2;

fig. 4A to fig. 4E are process diagrams of manufacturing a microbridge structure in a semiconductor silicon-based hybrid imaging chip for the medical field according to an embodiment of the present application;

fig. 5A to 5K are process diagrams illustrating a manufacturing process of an electrical connection supporting pillar in a semiconductor silicon-based hybrid imaging chip for medical field according to an embodiment of the present application.

With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The semiconductor silicon-based hybrid imaging chip (hereinafter referred to as hybrid imaging chip) oriented to the medical field is mainly applied to the medical field, for example: the hybrid imaging chip is used for monitoring the human body temperature, namely, infrared light emitted by human body heat radiation is monitored by using the hybrid imaging chip, so that the non-contact monitoring of the human body temperature is realized, and the efficiency of monitoring the human body temperature can be improved.

The hybrid imaging chip generally includes a semiconductor substrate and a plurality of pixel units, each including a micro-bridge structure, an electrical connection support pillar, and a beam structure. The micro-bridge structure, the electric connection support column and the beam structure are positioned above the semiconductor substrate. The electric connection support column supports the micro-bridge structure through the beam structure, the beam structure is used for leading out a first electric signal generated by the micro-bridge structure to the electric connection support column, the beam structure also plays a role in heat insulation, and heat is prevented from being transmitted to the electric connection support column from the micro-bridge structure. The electrical connection support column is used for leading the first electrical signal out to a processing circuit in the semiconductor substrate, and the electrical connection support column is also used for supporting the micro-bridge structure.

The semiconductor substrate is also provided with a visible light area, when the first optical signal enters from the bottom of the hybrid imaging chip, the visible light area absorbs visible light in the optical signal and generates a second electric signal, and the visible light intensity can be obtained by analyzing the second electric signal. And the second optical signal emitted from the visible light region is continuously emitted upwards to the micro-bridge structure, the micro-bridge structure absorbs infrared light in the second optical signal to generate a first electric signal, and the first electric signal is led out to a processing circuit in the semiconductor substrate through the beam structure and the electric connection supporting column.

As shown in fig. 1, a sensing resistor is generally disposed on the micro-bridge structure, and the sensing resistor includes a first dielectric protection layer 501, a second dielectric protection layer 503, and a sensing layer 502, and a first terminal 504 and a second terminal 505 are further disposed on the sensing resistor. Wherein the sensitive layer 502 is located between the first protective dielectric layer 501 and the second protective dielectric layer 503. A first terminal 504 and a second terminal 505 are located in the first dielectric protection layer 501, and the first terminal 504 and the second terminal 505 are both in contact with the upper surface of the sensitive layer 502, so that a first electrical signal generated on the sensitive layer 502 is output by the first terminal 504 and the second terminal 505.

Generally, when manufacturing the sensitive resistor, a dielectric material is deposited to form the second dielectric protection layer 503, a metal material is deposited on the second dielectric protection layer 503 to form the sensitive layer 502, a metal material is deposited on the sensitive layer 502 to form an electrode layer, a first lead-out terminal 504 and a second lead-out terminal 505 are formed by patterning the electrode layer, and finally a first dielectric protection layer 501 is formed by depositing the dielectric material.

However, when the electrode layer is patterned to generate the first and

second terminals

504 and 505, the etching process and the cleaning process during the patterning process may damage the upper surface of the sensitive layer 502, and a large number of defects may be formed on the upper surface of the sensitive layer 502, for example: the dangling bond, the upper surface of the electrode layer is in contact with the lower surface of the first dielectric protection layer 501, and the material of the electrode layer is different from that of the first dielectric protection layer, so that more defects are formed on the interface between the upper surface of the electrode layer and the lower surface of the first dielectric protection layer 501. In general, the carrier flow path S1 on the upper surface of the sensitive layer 502 is the shortest, the carrier flow path S2 on the lower surface of the sensitive layer 502 is the longest, and the carriers in the sensitive layer 502 mainly flow on the upper surface of the sensitive layer 502. A large number of defects on the upper surface of the sensitive layer 502 may cause scattering of carriers, thereby making the noise in the first electrical signal large.

In order to solve the above technical problem, an embodiment of the present invention provides a hybrid imaging chip to reduce the noise intensity generated by a sensitive resistor on a microbridge structure. The technical idea of the application is as follows: the sensitive layer 502 is provided as three semiconductor layers, which are labeled in sequence as a first semiconductor layer 702, a second semiconductor layer 703 and a third semiconductor layer 704. When carriers flow in the first semiconductor layer 702, the second semiconductor layer 703, and the third semiconductor layer 704, the flow rate of carriers in the second semiconductor layer 703 is larger than the flow rate of carriers in the first semiconductor layer 702 by at least one order of magnitude, and the flow rate of carriers in the second semiconductor layer 703 is larger than the flow rate of carriers in the third semiconductor layer 704 by at least one order of magnitude. With this arrangement, carriers mainly flow in the second semiconductor layer 703, and the flow rate of carriers on the first semiconductor layer 702 is reduced, so that the scattering effect at the interface between the first semiconductor layer 702 and the upper dielectric layer 701 is reduced, and the noise intensity is reduced or noise is eliminated.

As shown in fig. 2, an embodiment of the present application provides a semiconductor silicon-based hybrid imaging chip for medical field, which includes a micro-bridge structure 700, an electrical connection support pillar, a beam structure, and a semiconductor substrate 600.

The electrically connected supporting pillars are located on the semiconductor substrate 600, the electrically connected supporting pillars support the micro-bridge structure 700 through the beam structure, the electrically connected supporting pillars are further used for leading out the first electrical signal on the micro-bridge structure 700 into the semiconductor substrate 600, and the processing circuit in the semiconductor substrate 600 analyzes the first electrical signal to obtain the infrared light intensity. The beam structure, in addition to directing the first electrical signal on the microbridge structure 700 to the electrical connection support posts, also serves to insulate heat and prevent heat on the microbridge structure 700 from transferring to the electrical connection support posts. A visible light region 605 is also provided within the semiconductor substrate 600 for absorbing visible light and generating a second electrical signal.

The microbridge structure 700 includes an upper dielectric layer 701, a first semiconductor layer 702, a second semiconductor layer 703, a third semiconductor layer 704, and a lower dielectric layer 705, which are sequentially stacked from top to bottom. The carrier flow rate in the first semiconductor layer 702, the second semiconductor layer 703, and the third semiconductor layer 704 is changed according to the change in the absorbed heat. An infrared absorption layer (not shown) is disposed in the microbridge structure 700 for absorbing infrared light and generating heat, and transferring the heat to the first semiconductor layer 702 to the third semiconductor layer 704 to change the flow rate of carriers in the first semiconductor layer 702 to the third semiconductor layer 704.

The doping concentrations or doping types of the first semiconductor layer 702, the second semiconductor layer 703, and the third semiconductor layer 704 are different, so that the flow rates of carriers in the first semiconductor layer 702 to the third semiconductor layer 704 are different. And when carriers flow in the first semiconductor layer 702, the second semiconductor layer 703, and the third semiconductor layer 704, the flow rate of carriers in the second semiconductor layer 703 is larger than the flow rate of carriers in the first semiconductor layer 702 by at least one order of magnitude, and the flow rate of carriers in the second semiconductor layer 703 is larger than the flow rate of carriers in the third semiconductor layer 704 by at least one order of magnitude.

In an embodiment, the thickness of the second semiconductor layer 703 is greater than that of the first semiconductor layer 702, and the thickness of the second semiconductor layer 703 is greater than that of the third semiconductor layer 704, so that it can be further ensured that carriers are mainly in the second semiconductor layer 703, and the scattering effect on the interface between the first semiconductor layer 702 and the upper dielectric layer 701 can be reduced.

In the above-described embodiment, the first semiconductor layer 702, the second semiconductor layer 703, and the third semiconductor layer 704 are provided. By controlling the ion doping concentration or the ion doping type in the first semiconductor layer 702 to the third semiconductor layer 704, the flow rate of carriers in the first semiconductor layer 702 to the third semiconductor layer 704 is made different, and when carriers flow in the first semiconductor layer 702 to the third semiconductor layer 704, the flow rate of carriers in the second semiconductor layer 703 is made larger than the flow rate of carriers in the first semiconductor layer 702 by at least one order of magnitude, so that the flow rate of carriers in the second semiconductor layer 703 is made larger than the flow rate of carriers in the third semiconductor layer 704 by at least one order of magnitude. With the above arrangement, carriers are controlled to mainly flow in the second semiconductor layer 703, and the flow rate of carriers on the first semiconductor layer 702 is reduced, so that the scattering effect on the interface between the first semiconductor layer 702 and the upper dielectric layer 701 is reduced, and further, the noise intensity is reduced or noise is eliminated.

In an embodiment, when the flow rate of carriers in the first semiconductor layer 702 is greater than that in the first semiconductor layer 702, and the flow rate of carriers in the second semiconductor layer 703 is greater than that in the third semiconductor layer 704 by at least one order of magnitude, the flow rate of carriers in the second semiconductor layer 703 is greater than that in the first semiconductor layer 702 and the third semiconductor layer 703 is greater than that in the third semiconductor layer 703, and thus the flow rate of carriers in the second semiconductor layer 703 is greater than that in the third semiconductor layer 704 by at least one order of magnitude.

In an embodiment, the first semiconductor layer 702 and the third semiconductor layer 704 may be undoped amorphous silicon, the second semiconductor layer 703 is doped amorphous silicon, when carriers flow in the first semiconductor layer 702 to the third semiconductor layer 704, the carriers mainly pass through the doped amorphous silicon, the number of carriers in the undoped amorphous silicon is small, and the number of carriers on the surface of the undoped amorphous silicon is small, so that the scattering effect of the carriers is reduced, and the noise intensity is reduced or the noise is eliminated.

In an embodiment, the first semiconductor layer 702 and the third semiconductor layer 704 are N-type semiconductor layers, the second semiconductor layer 703 is a P-type semiconductor layer, a PN junction is formed between the first semiconductor layer 702 and the second semiconductor layer 703, and a PN junction is formed between the second semiconductor layer 703 and the third semiconductor layer 704, so that carriers in the P-type semiconductor layer cannot enter the N-type semiconductor layers on both sides, and thus the carriers mainly flow in the second semiconductor layer 703, the flow rate of internal carriers of the first semiconductor layer 702 and the third semiconductor layer 704 is reduced, the scattering on the interface between the first semiconductor layer 702 and the upper dielectric layer 701 is reduced, and the scattering on the interface between the second semiconductor layer 703 and the third semiconductor layer 704 is reduced, so as to achieve the effect of reducing noise.

In an embodiment, with continued reference to fig. 2, the micro-bridge structure 700 further includes a first electrode 711 and a second electrode 708, and the micro-bridge structure 700 defines a first electrode hole 729 and a second electrode hole 728. The first electrode 711 is positioned within the first electrode hole 729 and the second electrode 708 is positioned within the second electrode hole 728. The first electrode hole 729 is located in the upper dielectric layer 701, the first semiconductor layer 702, and the second semiconductor layer 703, and the second electrode hole 728 is located in the upper dielectric layer 701, the first semiconductor layer 702, and the second semiconductor layer 703. That is, the first electrode 711 and the second electrode 708 are spaced from the lower surface of the third semiconductor layer 704, so that the electric field intensity in the third semiconductor layer 704 is reduced, the flow rate of carriers in the third semiconductor layer 704 can be further reduced, the scattering at the contact interface between the third semiconductor layer 704 and the lower dielectric layer 705 is reduced, and the noise is reduced.

In an embodiment, the first electrode hole 729 and the second electrode hole 728 are in an inverted trapezoid shape, and when the first electrode 711 and the second electrode 708 are formed by a deposition process, the side walls of the first electrode hole 729 and the side walls of the second electrode hole 728 can be better acted, so that defects on a contact surface between the first electrode 711 and the second semiconductor layer 703 and defects on a contact surface between the second electrode 708 and the second semiconductor layer 703 are reduced, current distribution on the second semiconductor layer 703 is more uniform, and noise caused by non-uniformity of the first electrical signal output by each pixel unit is reduced.

In an embodiment, a distance d1 from the bottom of the first electrode hole 729 to the lower surface of the third semiconductor layer 704 is greater than a first preset distance threshold, and a distance d2 from the bottom of the second electrode hole 728 to the lower surface of the third semiconductor layer 704 is greater than the first preset distance threshold. A distance d1 from the bottom of the first electrode hole 729 to the lower surface of the third semiconductor layer 704 is less than a second preset distance threshold, and a distance d2 from the bottom of the second electrode hole 728 to the lower surface of the third semiconductor layer 704 is less than the second preset distance threshold. The first predetermined distance threshold may be D3, D3 is the thickness of the third semiconductor layer 704, the second predetermined distance threshold may be 50% × D2+ D3, and D2 is the thickness of the second semiconductor layer 703. With this arrangement, when the first electrode 711 is formed by depositing a metal material in the first electrode hole 729 and the second electrode 708 is formed by depositing a metal material in the second electrode hole 728, a distance is ensured between the first electrode 711 and the second electrode 708 and the lower surface of the third semiconductor layer 704, so that the electric field intensity in the third semiconductor layer 704 is reduced, the flow rate of carriers in the third semiconductor layer 704 can be further reduced, the scattering at the contact interface between the third semiconductor layer 704 and the lower dielectric layer 705 is reduced, and the noise is reduced.

In one embodiment, the contact surface 712 between the first electrode 711 and the first semiconductor layer 702 is lower than the upper surface 713 of the first semiconductor layer 702, and the contact surface 714 between the second electrode 708 and the first semiconductor layer 702 is lower than the upper surface 713 of the first semiconductor layer 702, so that the first electrode 711 does not contact with the upper surface of the first semiconductor layer 702, the electric field in the first semiconductor layer 702 is concentrated in a region close to the lower surface of the first semiconductor layer 702, the flow rate of carriers on the upper surface of the first semiconductor layer 702 is further reduced, the scattering is reduced, and the noise is reduced. In addition, the first electrode 711 and the second electrode 708 are not in contact with the upper surface of the first semiconductor layer 702, so that the electric field region moves downward, and when the first semiconductor layer 702 is an N-type region and the second semiconductor layer 703 is a P-type region, and a depletion region is formed in the first semiconductor layer 702, the flow rate of carriers in the first semiconductor layer 702 can be further reduced, the scattering effect on the upper surface of the first semiconductor layer 702 can be further reduced, and the effect of reducing noise can be achieved.

In one embodiment, referring to fig. 2, 3A-3C, the beam structure comprises a first serpentine beam 100, a second serpentine beam 200, a third serpentine beam 300, and a fourth serpentine beam 400, and the electrically connected support columns comprise a first support column 901, a second support column 902, a third support column 903, a fourth support column 904, a fifth support column 905, and a sixth support column 906.

Wherein the first serpentine beam 100 and the second serpentine beam 200 lie in a first plane, the third serpentine beam 300 and the fourth serpentine beam 400 lie in a second plane, and the microbridge structure 700 lies in a third plane. The third plane, the second plane and the first plane are arranged from top to bottom in sequence. And the projection of the first serpentine beam 100 on the semiconductor substrate 600 overlaps the projection of the third serpentine beam 300 on the semiconductor substrate 600, and the projection of the second serpentine beam 200 on the semiconductor substrate 600 overlaps the projection of the fourth serpentine beam 400 on the semiconductor substrate 600.

A first support column 901 is positioned between the semiconductor substrate 600 and the first serpentine beam 100. referring to fig. 3A, a first end of the first support column 901 is positioned on the semiconductor substrate 600 and a second end of the first support column 901 is connected to the first end of the first serpentine beam 100. The third support column 903 is positioned between the first serpentine beam 100 and the third serpentine beam 300. referring to figure 3A, the second end of the first serpentine beam 100 is attached to the first end of the third support column 903. referring to figure 3B, the second end of the third support column 903 is attached to the first end of the third serpentine beam 300. The fifth support column 905 is positioned between the third serpentine beam 300 and the microbridge structure 700. referring to FIG. 3B, the second end of the third serpentine beam 300 is connected to the first end of the fifth support column 905. referring to FIG. 3C, the second end of the fifth support column 905 supports the microbridge structure 700. Wherein the fifth supporting pillar 905 is connected to the first electrode 711 on the micro-bridge structure 700. With this arrangement, the fifth support column 905, the third serpentine beam 300, the third support column 903, the first serpentine beam 100, and the first support column 901 not only support the micro-bridge structure 700, but also form a signal leading-out path to lead out the first electrical signal output by the first electrode 711 to a processing circuit in the semiconductor substrate 600.

The second support column 902 is positioned between the semiconductor substrate 600 and the second serpentine beam 200. referring to fig. 3A, a first end of the second support column 902 is positioned on the semiconductor substrate 600 and a second end of the second support column 902 is connected to a first end of the second serpentine beam 200. The fourth support column 904 is positioned between the second serpentine beam 200 and the fourth serpentine beam 400. referring to figure 3A, the second end of the second serpentine beam 200 is attached to the first end of the fourth support column 904. referring to figure 3B, the second end of the fourth support column 904 is attached to the first end of the fourth serpentine beam 400. The sixth support column 906 is positioned between the fourth serpentine beam 400 and the microbridge structure 700. referring to FIG. 3B, the second end of the fourth serpentine beam 400 is connected to the first end of the sixth support column 906. referring to FIG. 3C, the second end of the sixth support column 906 supports the microbridge structure 700. Wherein the sixth supporting pillars 906 are connected to the second electrodes 708 on the microbridge structure 700. By such an arrangement, the micro-bridge structure 700 is supported by the sixth supporting column 906, the fourth serpentine beam 400, the fourth supporting column 904, the second serpentine beam 200 and the second supporting column 902, and another signal leading-out path is formed, so that an electrical signal output by the second electrode 708 is led out into the semiconductor substrate 600.

Referring to fig. 5I, 5J, and 5K, the first support column 901, the second support column 902, the third support column 903, the fourth support column 904, the fifth support column 905, and the sixth support column 906 have the same structure, and are all hollow structures. The structure of the first support column 901 is described below by taking the first support column 901 as an example, where the first support column 901 includes a first metal conducting layer, a first isolation protection layer and a first dielectric thin film layer, the first isolation protection layer is located at the outermost layer, the first dielectric thin film layer is located at the innermost layer, and the first metal conducting layer is located between the first dielectric thin film layer and the first isolation protection layer. The first metal conducting layer is used for leading out an electric signal, and the first isolation protective layer and the first medium thin film layer play roles in protection and isolation.

With continued reference to fig. 1, a back-end interconnect layer 606 is formed over the semiconductor substrate 600, the back-end interconnect layer 606 including two landing metal layers 604. One of the landing metal layers 604 is in contact with the first support column 901, the other landing metal layer 604 is in contact with the second support column 902, and both landing metal layers 604 are connected to the processing circuit in the semiconductor substrate 600 through the subsequent interconnect layer 606, so as to lead out the electrical signal on the micro-bridge structure 700 to the processing circuit for processing.

First serpentine beam 100 includes a first serpentine metal layer 102, a first upper serpentine dielectric layer 101, and a first lower serpentine dielectric layer 103, with first serpentine metal layer 102 being positioned between first upper serpentine dielectric layer 101 and first lower serpentine dielectric layer 103. The second serpentine beam 200 includes a second serpentine metal layer 202, a second upper serpentine dielectric layer 201, and a second lower serpentine dielectric layer 203, the second serpentine metal layer 202 being positioned between the second upper serpentine dielectric layer 201 and the second lower serpentine dielectric layer 203.

The first end of the first serpentine metal layer 102 is connected to the first metal conductive layer in the first support column 901, the second end of the first serpentine metal layer 102 is connected to the third metal conductive layer in the third support column 903, the first end of the second serpentine metal layer 202 is connected to the second metal conductive layer in the second support column 902, and the second end of the second serpentine metal layer 202 is connected to the fourth metal conductive layer in the fourth support column 904.

The third serpentine beam 300 includes a third serpentine metal layer 302, a third upper serpentine dielectric layer 301, and a third lower serpentine dielectric layer 303, the third serpentine metal layer 302 being positioned between the third upper serpentine dielectric layer 301 and the third lower serpentine dielectric layer 303. Fourth serpentine beam 400 includes a fourth serpentine metal layer 402, a fourth upper serpentine dielectric layer 401, and a fourth lower serpentine dielectric layer 403, with fourth serpentine metal layer 402 being between fourth upper serpentine dielectric layer 401 and fourth lower serpentine dielectric layer 403.

The first end of the third serpentine metal layer 302 is connected to the third metal conductive layer in the third support column 903, the second end of the third serpentine metal layer 302 is connected to the fifth metal conductive layer in the fifth support column 905, the first end of the fourth serpentine metal layer 402 is connected to the fourth metal conductive layer in the fourth support column 904, and the second end of the fourth serpentine metal layer 402 is connected to the sixth metal conductive layer in the sixth support column 906.

In the above technical solution, the microbridge structure 700 occupies a single layer, so that the fill factor is the highest and the infrared absorption is the most sufficient. The second serpentine beam 200 and the first serpentine beam 100 occupy a complete layer, the third serpentine beam 300 and the fourth serpentine beam 400 occupy a complete layer, and the beam structures can be designed to be structures with lower thermal conductivity, so that the hybrid imaging chip can realize higher infrared absorption rate and higher sensitivity, and is beneficial to reading and processing of subsequent processing circuits. Meanwhile, the process can be compatible with a CMOS process, the advantage of large-scale production of CMOS foundries is easier to utilize, and large-scale mass production of products is realized. And the supporting column in the whole structure does not penetrate any one of the four serpentine beams, so that the difficulty of the manufacturing process is reduced. And the beam structure is placed under the microbridge structure 700 to increase the infrared absorption or light sensing area and improve performance.

In general, when a hybrid imaging chip is manufactured, the manufacturing sequence is: the first step is to manufacture a first supporting column 901 and a second supporting column 902 which are positioned on the same layer, the second step is to manufacture a first serpentine beam 100 and a second serpentine beam 200 which are positioned on the same layer, the third step is to manufacture a third supporting column 903 and a fourth supporting column 904 which are positioned on the same layer, the fourth step is to manufacture a third serpentine beam 300 and a fourth serpentine beam 400 which are positioned on the same layer, the fifth step is to manufacture a fifth supporting column 905 and a sixth supporting column 906 which are positioned on the same layer, and the sixth step is to manufacture a micro-bridge structure 700, because the first supporting column 901 and the second supporting column 902 are hollow structures, after the first support columns 901 and the second support columns 902 are formed, and then the deposition of the material is continued to form a subsequent structure, pits are formed at the positions of the first support columns 901, the surface unevenness of a layer structure formed by a subsequent deposition material also has influence on a subsequent etching process, thereby causing influence on the performance of a hybrid imaging chip. In addition, a material which is not easily removed, such as: metallic or dielectric materials, which also affect the performance of the hybrid imaging chip.

An embodiment of the present application provides a method for preparing a semiconductor silicon-based hybrid imaging chip for the medical field, and the method specifically includes the following steps:

s101, a semiconductor substrate 600 is obtained, and a beam structure is formed on the semiconductor substrate 600.

The forming of the beam structure on the semiconductor substrate 600 specifically includes: a first sacrificial layer 601, a first serpentine beam 100, a second serpentine beam 200, a second sacrificial layer 602, a third serpentine beam 300, and a fourth serpentine beam 400 are sequentially formed on a semiconductor substrate 600.

More specifically, referring to fig. 2 and 4A, a visible light region 605 and a subsequent interconnect layer 606 are formed first in a semiconductor substrate 600. More specifically, the visible light region 605 is formed by implanting ions into the semiconductor substrate to form a P-type region and an N-type region. A back-end interconnect layer 606 is formed over the visible light region 605 by deposition and patterning processes, the back-end interconnect layer 606 including two landing metal layers 604. The deposition of the sacrificial layer material on the semiconductor substrate 600 is continued to form a first sacrificial layer 601. Sequentially depositing a dielectric material on the first sacrificial layer 601 to form a first dielectric layer, depositing a metal material on the first dielectric layer to form a first metal layer, depositing a dielectric material on the first metal layer to form a second dielectric layer, and patterning the first dielectric layer, the first metal layer and the second dielectric layer to form a first serpentine metal layer 102, a first upper serpentine dielectric layer 101, a first lower serpentine dielectric layer 103, a second serpentine metal layer 202, a second upper serpentine dielectric layer 201 and a second lower serpentine dielectric layer 203. Wherein, the first serpentine metal layer 102, the first upper serpentine dielectric layer 101, and the first lower serpentine dielectric layer 103 form a first serpentine beam 100, and the second serpentine metal layer 202, the second upper serpentine dielectric layer 201, and the second lower serpentine dielectric layer 203 form a second serpentine beam 200.

A sacrificial layer material is deposited over the first serpentine beam 100 and the second serpentine beam 200 to form a second sacrificial layer 602. Depositing a dielectric material on the second sacrificial layer 602 in sequence to form a third dielectric layer, depositing a metal material on the third dielectric layer to form a second metal layer, depositing a dielectric material on the second metal layer to form a fourth dielectric layer, and patterning the third dielectric layer, the second metal layer, and the fourth dielectric layer to form a third serpentine metal layer 302, a third upper serpentine dielectric layer 301, a third lower serpentine dielectric layer 303, a fourth serpentine metal layer 402, a fourth upper serpentine dielectric layer 401, and a fourth lower serpentine dielectric layer 403. A third serpentine metal layer 302, a third upper serpentine dielectric layer 301, and a third lower serpentine dielectric layer 303 comprise a third serpentine beam 300, and a fourth serpentine metal layer 402, a fourth upper serpentine dielectric layer 401, and a fourth lower serpentine dielectric layer 403 comprise a fourth serpentine beam 400.

And S102, forming a micro-bridge structure 700 on the snake-shaped beam.

Wherein a third sacrificial layer 603 is formed on the third serpentine beam 300 and the fourth serpentine beam 400, and a dielectric material and a semiconductor material are sequentially deposited on the third sacrificial layer 603 to form a lower dielectric layer 705 and a semiconductor base layer. A first semiconductor layer 702, a second semiconductor layer 703, and a third semiconductor layer 704 are formed by ion implantation in a semiconductor base layer. A dielectric material is deposited on the semiconductor base layer to form an upper dielectric layer 701.

In one embodiment, when ions are implanted into the semiconductor base layer, the concentration of the implanted ions may be controlled such that the ion concentration of the upper surface region of the semiconductor base layer is lower than that of the lower surface region of the semiconductor base layer, and the ion concentration of the middle region of the semiconductor base layer is higher, so that the doping concentration of the first semiconductor layer 702 is lower than that of the second semiconductor layer 703, and the doping concentration of the third semiconductor layer 704 is lower than that of the second semiconductor layer 703.

In an embodiment, the first semiconductor layer 702, the second semiconductor layer 703 and the third semiconductor layer 704 may be formed by controlling the type of the implanted ions so that the upper surface region of the semiconductor base layer and the lower surface region of the semiconductor base layer are N-type regions and the middle region of the semiconductor base layer is a P-type region.

After the lower dielectric layer 705, the first semiconductor layer 702, the second semiconductor layer 703, the third semiconductor layer 704, and the lower dielectric layer 705 are formed, the upper dielectric layer 701 and the semiconductor base layer are etched using light to form the first electrode hole 729 and the second electrode hole 728 of the inverted trapezoid shape. By controlling the photolithography process, a distance from the bottom of the first electrode hole 729 to the lower surface of the third semiconductor layer 704 is greater than a first preset distance threshold, a distance from the bottom of the first electrode hole 729 to the lower surface of the third semiconductor layer 704 is less than a second preset distance threshold, a distance from the bottom of the second electrode hole 728 to the lower surface of the third semiconductor layer 704 is greater than the first preset distance threshold, and a distance from the bottom of the second electrode hole 728 to the lower surface of the third semiconductor layer 704 is less than the second preset distance threshold.

When the upper dielectric layer 701 and the semiconductor base layer are photo-etched to form the first electrode hole 729 and the second electrode hole 728 having the inverted trapezoid shapes, a focus up-shifting process is used for photo-etching. The following scheme is adopted specifically:

with continuing reference to fig. 4A and 4B, a photoresist layer 721 is formed on the semiconductor substrate, the focusing positions of the first and second beams are controlled to be both inside the photoresist layer 721 and a distance L1 between each and the upper surface of the photoresist layer 721 is less than half the thickness L2/2 of the photoresist layer 721, and the first beam is irradiated to the photoresist layer 721 through the first through hole 726 of the photolithography mask 725 positioned above to form a first electrode hole 729 at the position of the first through hole 726 and the second beam is irradiated to the photoresist layer 721 through the second through hole 727 of the photolithography mask 725 positioned above to form a second electrode hole 728 at the position of the second through hole 727.

In the above technical solution, by controlling the focusing positions of the first and second light beams to be within the photoresist layer 721 and the distance between the focusing positions and the upper surface of the photoresist layer 721 to be less than half of the thickness of the photoresist layer 721, the upper half area of the photoresist layer 721 is over-exposed, the etching size is larger, the lower half area of the photoresist layer 721 is under-exposed, and the etching size is smaller, so as to obtain a shape of an inclined angle, as shown in fig. 4A, and the shape is transferred to the lower upper dielectric layer 701 and the lower semiconductor substrate, as shown in fig. 4B, thereby forming the first and second electrode holes 729 and 728 having inverse trapezoids.

As shown in fig. 2 and 4C, the deposition of the metal material in the first electrode hole 729 and the second electrode hole 728 is continued, and the metal material in the first electrode hole 729 near the surface of the semiconductor base layer and the metal material in the second electrode hole 728 near the surface of the semiconductor base layer are removed to form the first pedestal 709 of the first electrode 711 and the second pedestal 706 of the second electrode 708. As shown in fig. 2 and 4D, the deposition of the dielectric material in the first electrode hole 729 and the second electrode hole 728 is continued to form the second dielectric thin film layer 722, and the dielectric material above the first electrode hole 729 and the second electrode hole 728 is removed to expose the first pedestal 709 of the first electrode 711 and the second pedestal 706 of the second electrode 708. The deposition of the metal material and patterning are continued to form the first lead-out portion 710 of the first electrode 711 and the second lead-out portion 707 of the second electrode 708, and the deposition of the dielectric material is continued to form a third dielectric thin film layer 724, as shown in fig. 4E. Through the above process, it is possible to realize that the contact surface between the first electrode 711 and the first semiconductor layer 702 is lower than the upper surface of the first semiconductor layer 702, and the contact surface between the second electrode 708 and the first semiconductor layer 702 is lower than the upper surface of the first semiconductor layer 702.

And S103, forming an electric connection supporting column on the micro-bridge structure 700.

Referring to fig. 5A, 5B and 5C, a first main groove 811, a second main groove 812, a third main groove 813, a fourth main groove 814, a fifth main groove 815 and a sixth main groove 816 are formed in the microbridge structure 700, the first main groove 811, the third main groove 813 and the fifth main groove 815 are located above the first serpentine beam 100, the second main groove 812, the fourth main groove 814 and the sixth main groove 816 are located above the second serpentine beam 200, and the bottom of the first main groove 811, the bottom of the second main groove 812, the bottom of the third main groove 813, the bottom of the fourth main groove 814, the bottom of the fifth main groove 815 and the sixth main groove 816 extend to the lower surface of the third sacrificial layer 603.

In one embodiment, referring to fig. 5D, a first primary recess 811 is located at a first vertex of the upper surface of the microbridge structure 700, a second primary recess 812 is located at a second vertex of the upper surface of the microbridge structure 700, and the first vertex and the second vertex are located on the same diagonal. A third primary recess 813 is located on the first side of the microbridge structure 700 near the midpoint of the first side, and a fourth primary recess 814 is located on the second side of the microbridge structure 700 near the midpoint of the second side. A fifth primary groove 815 is located on the third side of the microbridge structure 700 near the midpoint of the third side, and a sixth primary groove 816 is located on the fourth side of the microbridge structure 700 near the midpoint of the fourth side. Wherein, the straight line C-C is a straight line passing through the middle point of the first edge and the middle point of the second edge, the first edge and the second edge are opposite edges, and the third edge and the fourth edge are opposite edges.

Referring to fig. 5E, a first sub-groove 821 is opened on the third serpentine beam 300 at a position corresponding to the first main groove 811, and a bottom of the first sub-groove 821 extends to a lower surface of the second sacrificial layer 602, and the first main groove 811 and the first sub-groove 821 constitute a first intermediate stepped groove. Referring to fig. 5F, a second sub-groove 822 is formed in a position of the fourth serpentine beam 400 corresponding to the second main groove 812, and a bottom of the second sub-groove 822 extends to a lower surface of the second sacrificial layer 602, and the second main groove 812 and the second sub-groove 822 form a second intermediate stepped groove. Referring to fig. 5E, a third sub-groove 823 is formed in a position corresponding to the third main groove 813 on the third serpentine beam 300, the bottom of the third sub-groove 823 extends to the lower surface of the second sacrificial layer 602, and the third main groove 813 and the third sub-groove 823 form a third step groove. Referring to fig. 5F, a fourth sub-groove 824 is formed in the fourth serpentine beam 400 at a position corresponding to the fourth main groove 814, and a bottom of the fourth sub-groove 824 extends to a lower surface of the second sacrificial layer 602, and the fourth main groove 814 and the fourth sub-groove 824 form a fourth step groove.

Referring to fig. 5G, a first slave recess 831 is opened at a position corresponding to the first slave recess 821 on the first serpentine beam 100, and the bottom of the first slave recess 831 extends to the lower surface of the first sacrificial layer 601, and the first master recess 811, the first slave recess 831, and the first slave recess 821 constitute a first stepped groove. Referring to fig. 5H, a second auxiliary groove 832 is formed in the second serpentine beam 200 at a position corresponding to the second sub-groove 822, and the second auxiliary groove 832 extends from the bottom of the groove 832 to the lower surface of the first sacrificial layer 601. The second master groove 812, the second slave groove 832, and the second sub groove 822 constitute a second stepped groove.

The dielectric material, the metal material and the dielectric material are sequentially deposited, and the dielectric material and the metal material in the third main groove 813, the fourth main groove 814, the first sub-groove 821, the first main groove 811, the second main groove 812 and the second sub-groove 822 are removed to realize that a conductive structure composed of multiple layers of thin films is formed in the first slave groove 831, the second slave groove 832, the third sub-groove 823, the fourth sub-groove 824, the fifth main groove 815 and the sixth main groove 816 to obtain the first support pillar 901, the second support pillar 902, the third support pillar 903, the fourth support pillar 904, the fifth support pillar 905 and the sixth support pillar 906, as shown in fig. 5I, fig. 5J and fig. 5K.

More specifically, when depositing the dielectric material first, and removing the dielectric material at the bottom of the first slave recess 831, the dielectric material at the bottom of the second slave recess 832, the dielectric material at the bottom of the third slave recess 823, the dielectric material at the bottom of the fourth slave recess 824, the dielectric material at the bottom of the fifth master recess 815, and the dielectric material at the bottom of the sixth master recess 816, it is also necessary to remove the dielectric material at the top region of the sidewall of the first slave recess 831, the dielectric material at the top region of the sidewall of the second slave recess 832, the dielectric material at the top region of the sidewall of the third slave recess 823, the dielectric material at the top region of the sidewall of the fourth slave recess 824, the dielectric material at the top region of the sidewall of the fifth master recess 815, and the dielectric material at the top region of the sidewall of the sixth master recess 816, and then continuing to deposit the metal materials to form the third metal conductive layer in the third support pillar and the fourth metal conductive layer in the fourth support pillar, the first metal conductive layer in the first support pillar and the second metal conductive layer in the second support pillar may be connected to the serpentine metal in the corresponding serpentine beam and the landing metal layer 604, and the fifth metal conductive layer in the fifth support pillar and the sixth metal conductive layer in the sixth support pillar may be connected to the serpentine metal in the corresponding serpentine beam and the microbridge structure 700.

And sequentially depositing a metal material and a dielectric material, and removing the dielectric material and the metal material in the third main groove 813, the fourth main groove 814, the first sub-groove 821, the first main groove 811, the second main groove 812 and the second sub-groove 822, so as to form a conductive structure composed of multiple layers of thin films in the first slave groove 831, the second slave groove 832, the third sub-groove 823, the fourth sub-groove 824, the fifth main groove 815 and the sixth main groove 816, so as to obtain the first support pillar 901, the second support pillar 902, the third support pillar 903, the fourth support pillar 904, the fifth support pillar 905 and the sixth support pillar 906.

In the above technical solution, a first sacrificial layer 601, a first serpentine beam 100, a second serpentine beam 200, a second sacrificial layer 602, a third serpentine beam 300, a fourth serpentine beam 400, a third sacrificial layer 603, and a micro-bridge structure 700 are sequentially formed on a semiconductor substrate 600, and then a first support column 901, a second support column 902, a third support column 903, a fourth support column 904, a fifth support column 905, and a sixth support column 906 are formed by slotting and deposition. When the first serpentine beam 100, the second serpentine beam 200, the third serpentine beam 300, the fourth serpentine beam 400 and the micro-bridge structure 700 are formed, no groove with a larger depth is formed, and the flatness of each layer formed by material deposition is better, so that six serpentine beams and the micro-bridge structure 700 can be formed by etching. And finally, six support columns are formed, and redundant materials which cannot be removed cannot be deposited in the hollow structures of the support columns. Through the arrangement, the performance is improved in the aspect of removing materials in the hollow structures of the flatness of each layer and each support column.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A semiconductor silicon-based hybrid imaging chip for the medical field, the hybrid imaging chip comprising a semiconductor substrate and at least one pixel unit, each pixel unit comprising: the micro-bridge structure, the electric connection supporting column and the beam structure;

the electric connection supporting column is positioned on the semiconductor substrate, supports the micro-bridge structure through the beam structure and leads out a first electric signal on the micro-bridge structure into the semiconductor substrate;

the micro-bridge structure comprises an upper dielectric layer, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a lower dielectric layer which are sequentially arranged in a stacked mode from top to bottom; the thickness of the second semiconductor layer is greater than that of the first semiconductor layer, and the thickness of the second semiconductor layer is greater than that of the third semiconductor layer.

2. The hybrid imaging chip of claim 1, wherein the second semiconductor layer has an ion doping concentration greater than that of the first semiconductor layer, and wherein the second semiconductor layer has an ion doping concentration greater than that of the third semiconductor layer.

3. The hybrid imaging chip of claim 1, wherein the first semiconductor layer and the third semiconductor layer are N-type semiconductor layers and the second semiconductor layer is a P-type semiconductor layer.

4. The hybrid imaging chip according to any one of claims 1 to 3, wherein the microbridge structure is provided with a first electrode hole and a second electrode hole;

5. The hybrid imaging chip of claim 4, wherein the first electrode hole and the second electrode hole are each in the shape of an inverted trapezoid;

the distance from the bottom of the first electrode hole to the lower surface of the third semiconductor layer is larger than a first preset distance threshold value; the distance from the bottom of the second electrode hole to the lower surface of the third semiconductor layer is larger than a first preset distance threshold value;

6. A hybrid imaging chip according to any one of claims 1 to 3, wherein the beam structure comprises a first serpentine beam, a second serpentine beam, a third serpentine beam, and a fourth serpentine beam; the electric connection supporting column comprises a first supporting column, a second supporting column, a third supporting column, a fourth supporting column, a fifth supporting column and a sixth supporting column;

said first and second serpentine beams lie in a first plane, said third and fourth serpentine beams lie in a second plane, and said microbridge structure lies in a third plane; the third plane, the second plane and the first plane are arranged from top to bottom in sequence; and a projection of the first serpentine beam on the semiconductor substrate and a projection of the third serpentine beam on the semiconductor substrate overlap, and a projection of the second serpentine beam on the semiconductor substrate and a projection of the fourth serpentine beam on the semiconductor substrate overlap;

a first end of the first support column is located on the semiconductor substrate, a second end of the first support is connected with a first end of the first serpentine beam, a second end of the first serpentine beam is connected with a first end of the third support column, a second end of the third support column is connected with a first end of a third serpentine beam, a second end of the third serpentine beam is connected with a first end of the fifth support column, and a second end of the fifth support column supports the microbridge structure;

the first end of second support column is located on the semiconductor substrate, the second end that the second supported with the first end of second snake-shaped beam is connected, the second end of second snake-shaped beam with the first end of fourth support column is connected, the second end of fourth support column is connected with the first end of fourth snake-shaped beam, the second end of fourth snake-shaped beam with the first end of sixth support column is connected, the second end of sixth support column supports the microbridge structure.

7. A preparation method of a semiconductor silicon-based hybrid imaging chip for the medical field is characterized by comprising the following steps:

forming a micro-bridge structure on the beam structure; wherein forming a microbridge structure on the beam structure comprises: forming a third sacrificial layer on the beam structure, and sequentially depositing a dielectric material and a semiconductor material on the third sacrificial layer to form a lower dielectric layer and a semiconductor base layer; forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer which are sequentially arranged from top to bottom in the semiconductor base layer through an ion implantation process; depositing a dielectric material on the semiconductor base layer to form an upper dielectric layer;

forming an electrical connection support post on the microbridge structure.

8. The method of manufacturing according to claim 7, wherein forming a microbridge structure on the beam structure further comprises:

continuing to deposit a metal material in the first electrode hole and the second electrode hole, and removing the metal material in the first electrode hole close to the upper surface of the semiconductor base layer and the metal material in the second electrode hole close to the upper surface of the semiconductor base layer to form a first pedestal of the first electrode and a second pedestal of the second electrode;

continuing to deposit dielectric materials in the first electrode hole and the second electrode hole, and removing the dielectric materials above the first electrode hole and the dielectric materials above the second electrode hole to expose a first base of the first electrode and a second base of the second electrode;

and continuing to deposit the metal material and patterning to form a first lead-out part of the first electrode and a second lead-out part of the second electrode.

9. The method according to claim 8, wherein the photo-etching the upper dielectric layer and the semiconductor substrate to form a first electrode hole having an inverted trapezoid shape and a second electrode hole having an inverted trapezoid shape comprises:

controlling a first light beam to irradiate the photoresist layer through a first through hole of the upper photoetching plate so as to form a first electrode hole at the position of the first through hole; and controlling a second light beam to irradiate the photoresist layer through a second through hole of the upper photoetching plate so as to form a second electrode hole at the position of the second through hole.

10. The method according to claim 7, wherein forming a beam structure on the semiconductor substrate specifically comprises:

sequentially forming a first sacrificial layer, a first serpentine beam, a second sacrificial layer, a third serpentine beam and a fourth serpentine beam on the semiconductor substrate;

forming a first main groove, a second main groove, a third main groove, a fourth main groove, a fifth main groove and a sixth main groove on the microbridge structure, wherein the first main groove, the third main groove and the fifth main groove are positioned above the first serpentine beam, the second main groove, the fourth main groove and the sixth main groove are positioned above the second serpentine beam, and the bottom of the first main groove and the bottom of the sixth main groove extend to the lower surface of the third sacrificial layer;

a first sub-groove is formed in the position, corresponding to the first main groove, of the third serpentine beam, a second sub-groove is formed in the position, corresponding to the second main groove, of the fourth serpentine beam, a third sub-groove is formed in the position, corresponding to the third main groove, of the third serpentine beam, a fourth sub-groove is formed in the position, corresponding to the fourth main groove, of the fourth serpentine beam, and the bottoms of the first sub-groove and the fourth sub-groove extend to the lower surface of the second sacrificial layer;

a first slave groove is formed in the first serpentine beam at a position corresponding to the first sub-groove, a second slave groove is formed in the second serpentine beam at a position corresponding to the second sub-groove, and the bottom of the first slave groove and the bottom of the second slave groove both extend to the lower surface of the first sacrificial layer;