CN114050166A - Hybrid imaging chip based on semiconductor COMS technology for medical imaging - Google Patents
Hybrid imaging chip based on semiconductor COMS technology for medical imaging Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
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- A61B5/0059—Measuring for diagnostic purposes; Identification of persons using light, e.g. diagnosis by transillumination, diascopy, fluorescence
- A61B5/0075—Measuring for diagnostic purposes; Identification of persons using light, e.g. diagnosis by transillumination, diascopy, fluorescence by spectroscopy, i.e. measuring spectra, e.g. Raman spectroscopy, infrared absorption spectroscopy
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- A—HUMAN NECESSITIES
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- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/01—Measuring temperature of body parts ; Diagnostic temperature sensing, e.g. for malignant or inflamed tissue
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/34—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using capacitors, e.g. pyroelectric capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14649—Infrared imagers
- H01L27/1465—Infrared imagers of the hybrid type
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
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- G—PHYSICS
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- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J2005/0077—Imaging
Abstract
The application provides a mixed imaging chip based on semiconductor COMS technology for medical imaging, includes: the micro-bridge is provided with a P-type semiconductor layer, a deformation layer and an infrared absorption layer which are sequentially arranged from top to bottom, a transistor pair array is formed in the P-type semiconductor layer, each transistor pair comprises two first N-type regions arranged on the top region of the P-type semiconductor layer, two second N-type regions arranged on the bottom region, a first gate dielectric layer arranged above the two first N-type regions, a second gate dielectric layer arranged below the two second N-type regions, a first gate electrode, a second gate electrode, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode, and through the arrangement, the sensitivity is higher.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a hybrid imaging chip based on a semiconductor COMS process for medical imaging.
Background
A hybrid imaging chip relates to the technical field of semiconductors, and is a thermal detector. Therefore, increasing the sensitivity of the hybrid imaging chip is an important part of the design of the hybrid imaging chip.
Disclosure of Invention
An embodiment of the present application provides a hybrid imaging chip based on semiconductor cmos process for medical imaging, including: the structure comprises a semiconductor substrate, a micro-bridge structure, a serpentine beam structure and an upper electric connection supporting column;
the upper electric connection supporting column is positioned on the semiconductor substrate and is connected with the micro-bridge structure through the serpentine beam structure, so that the micro-bridge structure is suspended above the semiconductor substrate; the micro-bridge structure is internally provided with a variable capacitor, and the capacitance of the variable capacitor changes after the micro-bridge structure absorbs infrared light;
the microbridge structure comprises a microbridge surface, wherein the microbridge surface comprises a P-type semiconductor layer, a deformation layer and an infrared absorption layer which are sequentially arranged from the top to the bottom; forming a transistor pair array in the P-type semiconductor layer; each transistor pair includes: the semiconductor device comprises two first N-type regions arranged at the top region of a P-type semiconductor layer, two second N-type regions arranged at the bottom region of the P-type semiconductor layer, a first gate dielectric layer arranged above the two first N-type regions, a first gate electrode arranged on the first gate dielectric layer, a first source electrode arranged around one first N-type region, a first drain electrode arranged around the other first N-type region, a second gate dielectric layer arranged below the two second N-type regions, a second gate electrode arranged below the second gate dielectric layer, a second source electrode arranged around one second N-type region, and a second drain electrode arranged around the other second N-type region;
when the infrared absorption layer absorbs infrared light to generate heat to cause the deformation layer to warp, the current of a first channel between the two first N-type regions is reduced, and the current of a second channel between the two second N-type regions is increased; the first channel current and the second channel current are a pair of differential current signals, and the differential current signals are used for determining the infrared light intensity.
In the above technical solution, by providing the transistor pair on the micro-bridge surface, when the micro-bridge surface is warped, a channel current at the top of the P-type semiconductor layer in the transistor pair becomes smaller, and a channel current at the bottom of the P-type semiconductor layer becomes larger, thereby forming a differential current signal. After acquiring the charge-discharge current signals generated by capacitance change of the interdigital capacitor and the plate capacitor in the micro-bridge structure and the differential current signals output by the transistor pair, the infrared light intensity is analyzed by combining the charge-discharge current signals and the differential current signals. Due to the fact that differential current signals generated by the transistor pairs are increased during analysis, chip sensitivity can be further improved.
In one embodiment, the first gate electrode is in a U-shaped structure, the second gate electrode is in a U-shaped structure, and the first gate electrode and the second gate electrode are connected to form a ring-shaped gate electrode; wherein, the plane of the annular gate electrode is vertical to the plane of the deformation layer.
In the technical scheme, by the arrangement, a plurality of gate electrodes are not required to be manufactured, the process can be simplified, channels can be generated in the top and the bottom of the P-type semiconductor layer, and in addition, channels can be generated in the two side areas of the P-type semiconductor layer, so that the source-drain current is further increased.
In one embodiment, the microbridge surface further comprises an upper horizontal electrode parallel to the infrared absorbing layer and a vertically disposed overhung electrode; the upper electric connection supporting column comprises a plurality of metal conducting layers; the width of the overhang electrode is twice the thickness of the outermost metal conductive layer of the upper electric connection support post, and the overhang electrode and the outermost metal conductive layer of the upper electric connection support post are formed by one-time metallization.
In one embodiment, in forming the overhang electrode and the metal conductive layer of the outermost layer of the upper electric connection support column, the overhang electrode is formed by forming a sacrificial layer on the semiconductor substrate, etching a trench of the overhang electrode and a trench of the upper electric connection support column on the sacrificial layer, depositing a metal material in the trench of the overhang electrode and the trench of the upper electric connection support column to form metal thin film layers on a bottom and both sidewalls of the trench of the overhang electrode and a bottom and both sidewalls of the trench of the upper electric connection support column, and the thickness of the deposited metal material is the thickness of the metal conductive layer of the outermost layer of the upper electric connection support column to bring the metal thin film layers of both sidewalls of the trench of the overhang electrode into contact.
In the above technical solution, when the upper portions of the overhang electrode and the upper electrical connection supporting pillar are usually manufactured, it is usually required to first etch the trench of the overhang electrode, fill titanium nitride TiN in the trench to form the overhang electrode, then continue to etch the trench of the upper electrical connection supporting pillar, deposit a metal material in the trench to form an outermost metal conductive layer, and then sequentially deposit a dielectric layer and a metal conductive layer to form metal conductive layers and dielectric layers arranged at intervals. That is, the metal conductive layer at the outermost layer of the overhang electrode and the upper electrical connection support post is formed by two metallizations, so that the number of metallizations is increased, and the metal conductive layer needs to be repositioned when the trench of the upper electrical connection support post is etched, thereby increasing the process difficulty. This application is through setting up the width of dangling electrode and is the twice of the thickness of the outermost metal conducting layer of electricity connection support column, and the thickness of deposit metal material is the thickness of the outermost metal conducting layer of electricity connection support column in the ditch groove of last electricity connection support column, and the metal film layer contact of two lateral walls of the ditch groove of the electrode that dangles forms the electrode that dangles, need not to divide twice etching ditch groove, reduces the number of times of metallization, reduces the technology degree of difficulty, simplifies the process.
In one embodiment, the micro bridge surface further comprises a plurality of connecting metals; a portion of the connection metal is located between the first drain electrodes of two adjacent transistor pairs to interconnect the first drain electrodes of the two adjacent transistor pairs, a portion of the connection metal is located between the second drain electrodes of the two adjacent transistor pairs to interconnect the second drain electrodes of the two adjacent transistor pairs, a portion of the connection metal is located between the first source electrodes of the two adjacent transistor pairs to interconnect the first source electrodes of the two adjacent transistor pairs, and a portion of the connection metal is located between the second source electrodes of the two adjacent transistor pairs to interconnect the second source electrodes of the two adjacent transistor pairs.
In one embodiment, the microbridge surface further comprises a first force-sensitive resistance layer and a second force-sensitive resistance layer; the area of the first force sensitive resistor layer is the same as that of the second force sensitive resistor layer, and the area of the first force sensitive resistor layer is the same as that of the deformation layer;
the resistance value of the first force sensitive resistance layer becomes small after being stressed, and the resistance value of the second force sensitive resistance layer becomes large after being stressed; one end of the first force-sensitive resistance layer is connected with the first drain electrode of each transistor pair; one end of the second force sensitive layer is connected to the second drain electrode of each transistor pair.
In the above technical solution, when the deformation amount of the deformation layer is larger, the current of the channel at the top is smaller, the resistance of the first force sensitive resistor layer is smaller, and the voltage drop on the first force sensitive resistor layer is smaller. When the deformation variable of the deformation layer is larger, the channel current at the bottom is larger, the resistance value of the second force sensitive resistance layer is also larger, the voltage drop on the second force sensitive resistance layer is larger, the obtained differential voltage signal is larger, the differential voltage signal is input into the processing circuit for analysis, the infrared light intensity is obtained, and therefore the sensitivity of the hybrid imaging chip can be improved.
In one embodiment, an electrode absorption layer is attached to the surface of the suspension electrode, the electrode absorption layer comprises a silicon nitride film layer, a silicon oxynitride film layer and a silicon dioxide film layer which are sequentially arranged from outside to inside, infrared light which is reflected for multiple times between the suspension electrodes is absorbed by the electrode absorption layer for multiple times, the electrode absorption layer generates heat after absorbing the infrared light, and the suspension electrode is used for transferring heat to the micro-bridge surface.
In one embodiment, after etching the trench of the overhang electrode and the trench of the electrical connection support post on the sacrificial layer, depositing a multi-layer absorption layer film in the trench of the overhang electrode and the trench of the electrical connection support post to form a multi-layer absorption layer film on the bottom and both sidewalls of the trench of the overhang electrode and the bottom and both sidewalls of the trench of the electrical connection support post, and removing the absorption layer film on the bottom of the trench of the electrical connection support post and the absorption layer film on the surface of the sacrificial layer using a vertical anisotropic etching process to form an electrode absorption layer in the trench of the overhang electrode and an isolation protection layer in the trench of the electrical connection support post; and depositing a metal material on the electrode absorption layer and the isolation protection layer to form a metal film layer so as to form the overhanging electrode and the outermost metal conducting layer of the upper electric connection supporting column through once metallization.
In the technical scheme, the electrode absorption layer is of a laminated film structure and is used for absorbing infrared light and then heating, the suspension electrodes are made of metal materials and have good heat conduction performance, and therefore after the infrared light is reflected and absorbed between the two suspension electrodes for multiple times, the heat can be conducted to the micro bridge floor through the suspension electrodes so as to enhance the absorption effect. And the electrode absorption layer is a silicon nitride film layer, a silicon oxynitride film layer and a silicon dioxide film layer which are arranged from outside to inside in sequence, so that the absorption efficiency of the electrode absorption layer can be improved.
In one embodiment, a seventh transistor and an eighth transistor are formed within a semiconductor substrate;
the seventh transistor is provided with a third source electrode, a third drain electrode, a third gate electrode and a third substrate end; the eighth transistor is provided with a fourth source electrode, a fourth drain electrode, a fourth gate electrode and a fourth substrate end;
a third substrate end of the seventh transistor is connected with a third drain electrode, the third drain electrode is used as a first end of the variable filter resistor, the third source electrode is used as a second end of the variable filter resistor, and the third gate electrode is used as a control end of the variable filter resistor;
a fourth drain electrode, a fourth source electrode and a fourth substrate end of the eighth transistor are connected and then serve as a first end of the filter capacitor, and a fourth gate electrode serves as a second end of the filter capacitor;
the second end of the filter capacitor is connected with the second power supply end with adjustable amplitude, the control end of the variable filter resistor is connected with the first power supply end with adjustable amplitude, the first end of the filter capacitor is connected with the second end of the variable capacitor, and the first end of the variable filter resistor is connected with the second end of the variable capacitor.
In one embodiment, the signal applied to the third gate electrode of the seventh transistor is adjusted according to the magnitude of the current signal output by the upper horizontal electrode to adjust the resistance value of the variable filter resistor; and adjusting a voltage applied to the fourth gate electrode of the eighth transistor according to a magnitude of the current signal output from the upper horizontal electrode to adjust a capacitance of the eighth transistor.
In the above technical scheme, a resonant cavity is formed in the micro-bridge structure, so that a high-frequency alternating current signal is doped in the interdigital capacitor and a charge-discharge current signal of the interdigital capacitor, and the frequency of the high-frequency alternating current signal is related to the intensity of infrared light, that is, the amplitude of the high-frequency alternating current signal is variable.
Drawings
In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a front view of a hybrid imaging chip according to an embodiment of the present application;
FIG. 2 is a front view of a transistor pair in a P-type semiconductor layer according to an embodiment of the present application;
FIG. 3 is a schematic illustration of a lattice in a P-type semiconductor layer provided in the embodiment of FIG. 2 herein;
FIG. 4 is a cross-sectional view of a transistor pair in a P-type semiconductor layer provided in the embodiment of FIG. 2 of the present application;
fig. 5 is a top view of a P-type semiconductor layer according to an embodiment of the present disclosure;
FIG. 6 is a schematic circuit diagram of the transistor pair in the P-type semiconductor layer shown in FIG. 5;
FIG. 7 is a front view of a power-on connection support post provided in accordance with an embodiment of the present application;
FIG. 8 is a front view of a semiconductor substrate according to an embodiment of the present application
FIG. 9 is a graph illustrating capacitance characteristics of transistors according to an embodiment of the present application;
fig. 10A to 10D are schematic views illustrating the formation of upper electrical connection support pillars and overhang electrodes according to an embodiment of the present application.
Detailed Description
To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The hybrid imaging chip provided by the application is mainly applied to the medical field, for example: the hybrid imaging chip is used for monitoring the human body temperature, namely, infrared light emitted by human body heat radiation is monitored by using the hybrid imaging chip, so that the non-contact monitoring of the human body temperature is realized, and the efficiency of monitoring the human body temperature can be improved.
As shown in fig. 1, an embodiment of the present application provides a hybrid imaging chip based on semiconductor cmos process for medical imaging, which includes a semiconductor substrate 700, a micro-bridge structure 100, an upper electrical connection support column 400, a lower electrical connection support column 500, and a serpentine beam structure 800.
The upper electrical connection support pillars 400 and the lower electrical connection support pillars 500 are located on the semiconductor substrate 700, and the upper electrical connection support pillars 400 are connected with the micro-bridge structure 100 through the serpentine beam structure 800, so that the micro-bridge structure 100 is suspended above the semiconductor substrate 700. A plurality of lower horizontal electrodes 502 and a plurality of vertical electrodes 501 are provided in the semiconductor substrate 700. The lower horizontal electrode 502 and the vertical electrode 501 are electrically connected, and the lower horizontal electrode 502 and the lower electrical connection support column 500 are electrically connected.
The micro-bridge structure 100 comprises a micro-bridge deck 101 and an overhang electrode 111, wherein the micro-bridge deck 101 comprises an upper horizontal electrode 112, and the upper horizontal electrode 112 is electrically connected with the overhang electrode 111. The upper horizontal electrode 112 and the lower horizontal electrode 502 are oppositely disposed, so that a plate capacitor is formed between the upper horizontal electrode 112 and the lower horizontal electrode 502. The overhang electrodes 111 and the vertical electrodes 501 are oppositely arranged, each overhang electrode 111 is arranged adjacent to at least one vertical electrode 501, and each vertical electrode 501 is arranged adjacent to at least one overhang electrode 111, so that an interdigital capacitor is formed between two adjacent vertical electrodes 501 and the overhang electrodes 111. The variable capacitance within the microbridge structure 100 includes plate capacitance and interdigital capacitance.
A visible light region 704 and a front device region 703 are provided in the bottom of the semiconductor substrate 700, and a processing circuit 620 is provided in the front device region 703. Light rays are incident through the bottom of the hybrid imaging chip, and output electric signals after being absorbed by the visible light area 704, and then the electric signals output by the visible light area 704 are analyzed by the processing circuit 620 to obtain the visible light intensity. The micro bridge deck 101 further includes a deformation layer 113 and an infrared absorption layer 114, and light is incident to the micro bridge structure 100 after being absorbed in a visible light region 704. The infrared absorption layer 114 is used for absorbing infrared light and then heating, the infrared absorption layer 114 is in contact with the deformation layer 113, the deformation layer 113 deforms after absorbing heat generated by the infrared absorption layer 114, the micro-bridge surface 101 is warped, the suspension electrode 111 is driven to move relative to the vertical electrode 501, the upper horizontal electrode 112 is driven to move relative to the lower horizontal electrode 502, capacitance of the interdigital capacitor and capacitance of the flat capacitor are changed, the interdigital capacitor and the flat capacitor are charged and discharged, charging and discharging currents are generated, the charging and discharging currents are read through the processing circuit 620, and infrared light intensity is obtained according to the magnitude of the charging and discharging currents.
With continued reference to fig. 1, the micro bridge surface 101 further includes a P-type semiconductor layer 115, where the P-type semiconductor layer 115 is made of a material with a large forbidden band width, such as: InP, AsGa, etc. The P-type semiconductor layer 115, the deformation layer 113, and the infrared absorption layer 114 are sequentially arranged from top to bottom.
As shown in fig. 2, an array of transistor pairs is formed within the P-type semiconductor layer 115. Each transistor pair 102 includes two first N-type regions 131, two second N-type regions 141, a first gate dielectric layer 133, a second gate dielectric layer 143, a first gate electrode 136, a second gate electrode 146, a first drain electrode 134, a second drain electrode 144, a first source electrode 135, and a second source electrode 145.
Two first N-type regions 131 are disposed on a top region of the P-type semiconductor layer 115, a first gate dielectric layer 133 is disposed over the two first N-type regions 131, a first gate electrode 136 is disposed over the first gate dielectric layer 133, a first source electrode 135 is disposed around one of the first N-type regions 131, and a first drain electrode 134 is disposed around the other first N-type region 131, forming a first channel (not shown) between the two first N-type regions 131.
Two second N-type regions 141 are disposed at a bottom region of the P-type semiconductor layer 115, a second gate dielectric layer 143 is disposed under the two second N-type regions 141, a second gate electrode 146 is disposed under the second gate dielectric layer 143, a second source electrode 145 is disposed around one of the second N-type regions 141, and a second drain electrode 144 is disposed around the other second N-type region 141, forming a second channel (not shown) between the two second N-type regions 141.
As shown in FIG. 3, when the infrared absorption layer 114 absorbs infrared light and generates heat, the deformation layer 113 is deformed, and the micro bridge deck 101 is warped. The upper surface of the P-type semiconductor layer 115 is compressive stress and the electron mobility is reduced. The lower surface of the P-type semiconductor layer 115 is tensile stressed, the lattice constant becomes large, electrons are weakened by lattice scattering, and the electron mobility becomes large. At the same voltage, the current in the first channel located at the top of the P-type semiconductor layer 115 is small, and the current in the second channel located at the bottom of the P-type semiconductor layer 115 is large. So that the first channel current between the two first N-type regions 131 becomes small and the second channel current between the two second N-type regions 141 becomes large, so that the first channel current and the second channel current are a pair of differential current signals, and the differential current signals are used for determining the intensity of the infrared light.
In the above-described configuration, by providing the transistor pair 102 on the micro-bridge surface 101, when the micro-bridge surface 101 is warped, the channel current at the top of the P-type semiconductor layer 115 in the transistor pair 102 becomes small, and the channel current at the bottom of the P-type semiconductor layer 115 becomes large, thereby forming a differential current signal. After the charge and discharge current signals generated by the capacitance change of the interdigital capacitor and the plate capacitor in the micro-bridge structure 100 and the differential current signals output by the transistor pair 102 are obtained, the infrared light intensity is analyzed by combining the charge and discharge current signals and the differential current signals. The chip sensitivity can be further improved due to the addition of the differential current signal generated by the transistor pair 102 during the analysis.
In an embodiment, the control signals of the two gate electrodes in the transistor pair 102 are the same, so the first gate electrode 136 and the second gate electrode 146 are made into a wrap gate structure, as shown in fig. 4, the first gate electrode 136 is U-shaped, the second gate electrode 146 is U-shaped, and the first gate electrode 136 and the second gate electrode 146 are connected to form a ring-shaped gate electrode, and the plane of the ring-shaped gate electrode is perpendicular to the plane of the deformation layer 113. Correspondingly, the first gate dielectric layer 133 and the second gate dielectric layer 143 also annularly surround the P-type semiconductor layer 115, so that a plurality of gate electrodes are not required to be manufactured, the process can be simplified, channels can be generated in the two side regions of the P-type semiconductor layer 115 besides the top and the bottom of the P-type semiconductor layer 115, and the source-drain current is further increased.
In an embodiment, with continued reference to fig. 5, the microbridge surface 101 also includes a plurality of connecting metals 103. Wherein a portion of the connection metal 103 is located between the first drain electrodes 134 of two adjacent transistor pairs 102 to connect the first drain electrodes 134 of two adjacent transistor pairs 102 to each other. A portion of the connection metal 103 is located between the second drain electrodes 144 of two adjacent transistor pairs 102 (not shown) to connect the second drain electrodes 144 of two adjacent transistor pairs 102 to each other. A portion of the connection metal 103 is located between the first source electrodes 135 of two adjacent transistor pairs 102 to connect the first source electrodes 135 of two adjacent transistor pairs 102 to each other. A portion of the connection metal 103 is located between the second source electrodes 145 of two adjacent transistor pairs 102 (not shown) to connect the second source electrodes 145 of two adjacent transistor pairs 102 to each other. A portion of the connection metal 103 is located between the first gate electrodes 136 of two adjacent transistor pairs 102 to connect the first gate electrodes 136 of the two adjacent transistor pairs 102 to each other. A portion of the connection metal 103 is located between the second gate electrodes 146 of two adjacent transistor pairs 102 (not shown) so as to connect the second gate electrodes 146 of two adjacent transistor pairs 102 to each other. By such an arrangement, the transistors of the transistor pair 102, whose channel currents become larger as the microbridge structure 100 warps, are connected in parallel, and the transistors of the transistor pair 102, whose channel currents become smaller as the microbridge structure 100 warps, are connected in parallel, and an equivalent circuit diagram thereof is shown in fig. 6.
With continued reference to fig. 6, the first transistor N11 and the second transistor N12 are a transistor pair 102, the third transistor N21 and the fourth transistor N22 are a transistor pair 102, the fifth transistor N31 and the sixth transistor N32 are a transistor pair 102, and the first transistor N11, the third transistor N21 and the fifth transistor N31 have the same structure, and each include two first N-type regions 131, a first gate dielectric layer 133, a first source electrode 135, a first drain electrode 134 and a first gate electrode 136, that is, each is a transistor whose channel current decreases as the microbridge structure 100 warps. The second transistor N12, the fourth transistor N22, and the sixth transistor N32 have the same structure, and each include two second N-type regions 141, a second gate dielectric layer 143, a second source electrode 145, a second drain electrode 144, and a second gate electrode 146, that is, the transistors whose channel current increases as the microbridge structure 100 warps.
With continued reference to fig. 6, the micro-bridge plane 101 further includes a first force-sensitive resistor layer and a second force-sensitive resistor layer; the area of the first force sensitive resistor layer is the same as the area of the second force sensitive resistor layer, and the area of the first force sensitive resistor layer is the same as the area of the deformation layer 113. Thus, even if the deformation layer 113 is slightly deformed, the first force sensitive resistor layer and the second force sensitive resistor layer can sense the deformation, and the sensitivity of the hybrid imaging chip is increased by reacting to the resistance values of the first force sensitive resistor layer and the second force sensitive resistor layer. Further, the resistance R1 of the first resistance layer becomes smaller after being subjected to pressure, and the resistance R2 of the second resistance layer becomes larger after being subjected to pressure. That is, after the microbridge structure 100 is warped, the resistance R1 of the first force-sensitive resistance layer becomes smaller, and the resistance R2 of the second force-sensitive resistance layer becomes larger. Here, if the channel current of each transistor pair 102 on the top of the P-type semiconductor layer 115 becomes smaller, one end of the first force-sensitive resistor layer is connected to the first drain electrode 134 of each transistor pair 102, the channel current of each transistor pair 102 on the bottom of the P-type semiconductor layer 115 becomes larger, and one end of the second force-sensitive resistor layer is connected to the second drain electrode 144 of each transistor pair 102. The first and second force sensitive layers are for converting a channel current to a voltage signal. Through such an arrangement, when the deformation amount of the deformation layer 113 is larger, the channel current at the top is smaller, the resistance R1 of the first force sensitive resistor layer is smaller, the voltage drop on the first force sensitive resistor layer is further smaller, the channel current at the bottom is larger, the resistance R2 of the second force sensitive resistor layer is also larger, the voltage drop on the second force sensitive resistor layer is further larger, the obtained differential voltage signal is larger, and the differential voltage signal is input into the processing circuit 620 arranged in the front device region 703 for analysis, so as to obtain the infrared light intensity, thereby improving the sensitivity of the hybrid imaging chip.
In an embodiment, referring to fig. 1 and 7, a first portion 401 of the upper electrical connection support column 400 is located above the semiconductor substrate 700 and a second portion 402 of the upper electrical connection support column 400 is located within the semiconductor substrate 700. The first portion 401 of the upper electrical connection support column 400 located above the semiconductor substrate 700 is a multi-layered hollow structure including a multi-layered dielectric layer 425, an isolation protection layer 424, and a multi-layered metal conductive layer 423 disposed from the outside to the inside. The isolation protection layer 424 is located at the outermost side and used for buffering the dielectric layer and blocking etching, the dielectric layer 425 is located between the two metal conductive layers 423 and used for isolating the metal conductive layers 423, and the metal conductive layers 423 are used for leading out electrical signals on the micro-bridge structure 100. For example: the voltages of the first and second force-sensitive resistor layers are drawn, and the currents on the upper horizontal electrode 112 and the overhang electrode 111 are drawn.
The second portion 402 of the upper electrical connection supporting column 400 located in the semiconductor substrate 700 includes a metal via 421 and a metal block 422, the metal via 421 is formed on the semiconductor substrate 700 by a through silicon via process, the multi-layer metal conductive layer 423 in the upper electrical connection supporting column 400 is connected to the metal via 421 through the metal block 422 in the semiconductor substrate 700, and the metal via 421 is connected to the processing circuit 620, so as to introduce the electrical signal on the micro-bridge structure 100 into the processing circuit 620. The processing circuit 620 is used for converting the electrical signal into infrared light intensity.
In one embodiment, the back-end interconnect layer 702 is electrically connected to the upper electrical connection support column 400, and the back-end interconnect layer 702 is further connected to the processing circuit 620, so as to lead out the charge and discharge current signal and the differential voltage signal on the micro-bridge surface 101 to the processing circuit 620. The lower electrical connection support column 500 is connected with a processing circuit 620 in the semiconductor substrate 700 through a subsequent interconnect layer 702, so as to lead out charge and discharge current signals of the lower horizontal electrode 502 and the vertical electrode 501 in the semiconductor substrate 700 to the processing circuit 620.
In one embodiment, the electrode absorption layer 116 is attached to the surface of the overhang electrode 111, the electrode absorption layer 116 is also attached to the surface of the vertical electrode 501, and the electrode absorption layer 116 includes a silicon nitride (SiN) thin film layer, a silicon oxynitride (SiON) thin film layer, and a silicon dioxide (SiO) thin film layer sequentially disposed from the outside to the inside2) The thin film layer, infrared light after multiple reflections between the overhanging electrodes 111 is absorbed multiple times by the electrode absorption layer 116, the electrode absorption layer 116 generates heat after absorbing infrared light, and the overhanging electrodes 111 are used for transferring heat to the micro-bridge surface 101.
In the above technical solution, the electrode absorption layer 116 is a laminated film structure for absorbing infrared light and then generating heat, and the suspended electrodes 111 are made of metal material and have good thermal conductivity, so that after infrared light is reflected and absorbed between two suspended electrodes 111 for multiple times, heat can be conducted to the micro bridge deck 101 through the suspended electrodes 111 to enhance the absorption effect. And the electrode absorption layer 116 is a silicon nitride thin film layer, a silicon oxynitride thin film layer and a silicon dioxide thin film layer which are sequentially arranged from the outside to the inside, and by such arrangement, the absorption efficiency of the electrode absorption layer 116 can be improved.
In an embodiment, referring to fig. 8, two third N-type regions 601 are further formed in the previous device region 703, a third gate dielectric layer 603 is formed above the two third N-type regions 601, a third gate electrode 606 is formed on the third gate dielectric layer 603, a third source electrode 605 is formed around one third N-type region 601, a third drain electrode 604 is formed around the other third N-type region 601, and a third substrate end is provided in the semiconductor substrate 700, so that a seventh transistor is formed in the semiconductor substrate 700.
Two fourth N-type regions 611 are formed in the semiconductor substrate 700, a fourth gate dielectric layer 613 is formed above the two fourth N-type regions 611, and a fourth gate electrode 616 is formed on the fourth gate dielectric layer 613; a fourth source electrode 615 is formed around one of the fourth N-type regions 611, a fourth drain electrode 614 is formed around the other fourth N-type region 611, and a fourth substrate end is provided in the semiconductor substrate 700, and by doing so, an eighth transistor is formed in the semiconductor substrate 700.
The seventh transistor is used as a variable filter resistor with adjustable resistance value, and the eighth transistor is used as a filter capacitor with adjustable capacitance. Specifically, the seventh transistor is operated in the linear resistance region by controlling a voltage applied to the third gate electrode 606 of the seventh transistor. The third source electrode 605 of the seventh transistor is used as the second end of the variable filter resistor, the third drain electrode 604 of the seventh transistor is connected to the third substrate end and then used as the first end of the variable filter resistor, the third gate electrode 606 of the seventh transistor is used as the control end of the variable filter resistor, and the control end of the variable filter resistor is connected to the first power supply end with adjustable amplitude.
The fourth drain electrode 614, the fourth source electrode 615, and the fourth substrate end of the eighth transistor are connected to form a filter capacitor. And controlling the filter capacitor according to the capacitance characteristic of the transistor to form the filter capacitor with adjustable capacitance. As shown in fig. 9, the ordinate represents the capacitance C of the transistor, and the abscissa represents the gate electrode voltage vg. Since the gate electrode voltage vg in fig. 9 is a voltage of the substrate terminal of the opposite transistor. The gate voltages described below are all voltages at the opposite substrate end. When the gate voltage is less than the flatband voltage Vfb, the transistor capacitance is in the accumulation region. When the gate voltage is greater than the threshold voltage Vt, the transistor capacitance is in the inversion region. The capacitance of the capacitor transistor is fixed in the accumulation region and the inversion region. When the gate voltage is greater than the flat band voltage Vfb and less than the threshold voltage Vt, the capacitance of the capacitor transistor is changed. In fig. 9, the flat band voltage Vfb is smaller than zero, the threshold voltage Vt is larger than zero, the voltage variation range crosses the zero point, which is not favorable for the application of the gate voltage, and ions are doped in the semiconductor substrate 700, so that the gate voltage variation range corresponding to the capacitance variable region is left at the origin and does not cross the zero point, so as to apply the adjustable voltage to the fourth gate electrode 616. Through the above analysis process, the fourth gate electrode 616 of the eighth transistor is connected to the second power supply terminal with adjustable amplitude, and the voltage of the fourth gate electrode 616 is between the flat band voltage Vfb and the threshold voltage Vt, so as to form a filter capacitor with adjustable capacitance.
The fourth gate electrode 616 of the eighth transistor is used as the second terminal of the filter capacitor, that is, the second terminal of the filter capacitor is connected to the second power supply terminal, and the fourth substrate terminal of the eighth transistor is used as the first terminal of the filter capacitor. And connecting the first end of the filter capacitor with the second end of the variable capacitor, and connecting the first end of the variable filter resistor with the second end of the variable capacitor, so that the filter capacitor and the variable filter resistor form an RC oscillator.
Because the resonant cavity is formed in the micro-bridge structure 100, infrared light is absorbed by the micro-bridge structure 100 after being emitted into the micro-bridge structure 100 through multiple reflections, so that the micro-bridge structure 100 is easy to vibrate, the capacitance variation of the variable capacitor can also shake, a high-frequency alternating current signal is doped in a charging and discharging current signal output by the second end of the variable capacitor, the frequency of the high-frequency alternating current signal is related to the intensity of the infrared light, namely the amplitude of the high-frequency alternating current signal is changed, the seventh transistor works in the linear resistance region to form the variable filter resistor by forming two transistors in the semiconductor substrate 700, and the eighth transistor is used as the filter capacitor with adjustable amplitude, so that the filter capacitor and the variable filter resistor form an RC oscillator to suppress the high-frequency alternating current signal or eliminate the high-frequency alternating current signal. At the moment, the filtering capacitor with adjustable capacitance is used for filtering, so that the high-frequency alternating current filter can adapt to high-frequency alternating current signals with constantly changing frequency, and the high-frequency alternating current signals are filtered to a power supply or the ground, so that filtering of different frequency bands is realized.
In one embodiment, the signal applied to the third gate electrode 606 of the seventh transistor is adjusted according to the magnitude of the current signal output from the upper horizontal electrode 112 to adjust the resistance value of the variable filter resistor; and adjusts the voltage applied to the fourth gate electrode 616 of the eighth transistor according to the magnitude of the current signal output from the upper horizontal electrode 112 to adjust the capacitance of the filter capacitor. The amplitude of the first power supply end connected with the control end of the variable filter resistor and the amplitude of the second power supply end connected with the second end of the filter capacitor are adjusted, so that the resistance value of the variable filter resistor and the capacitance of the filter capacitor can be adjusted to realize matching with the oscillation signal, and the oscillation signal is better eliminated.
The upper electrical connection supporting pillar 400 is a multi-layer hollow structure, the overhanging electrode is a solid column, and generally, when the overhanging electrode 111 and the first portion 401 of the upper electrical connection supporting pillar 400 are manufactured, it is usually necessary to etch the trench of the overhanging electrode first, fill titanium nitride TiN in the trench to form the overhanging electrode 111, then continue to etch the trench of the upper electrical connection supporting pillar 400, and sequentially deposit metal and dielectric in the trench to form the metal conductive layer 423 and the dielectric layer 425 which are arranged at intervals. That is, the overhang electrode 111 and the outermost metal conductive layer 423 of the upper electrical connection supporting pillar 400 are formed by two metallizations, so that the number of metallizations is increased, and the trench of the upper electrical connection supporting pillar 400 needs to be repositioned when etching after the overhang electrode 111 is formed, thereby increasing the process difficulty.
In one embodiment, as shown in fig. 10D, the width D1 of the overhang electrode 111 is twice the thickness D2 of the outermost metal conductive layer 423 of the upper electrical connection support column 400, and the overhang electrode 111 and the outermost metal conductive layer 423 of the upper electrical connection support column 400 are formed by one-time metallization.
In one embodiment, in forming the overhang electrode 111 and the outermost metal conductive layer 423 of the upper electrical connection support column 400, as shown in fig. 10A, the trench 302 of the overhang electrode 111 and the trench 303 of the upper electrical connection support column 400 are etched on the sacrificial layer 301 by forming the sacrificial layer 301 on the semiconductor substrate 700. The size of the trench 303 of the upper electrical connection support column 400 is large and the size of the trench 302 of the overhang electrode 111 is small. As shown in fig. 10B, a metal material is deposited within the trench 302 of the overhang electrode 111 and the trench 303 of the upper electrical connection support column 400 to form a metal thin film layer 304 on both sidewalls and the bottom of the trench of the overhang electrode 111 and both sidewalls and the bottom of the above trench of the electrical connection support column 400. As shown in fig. 10C, since the width of the overhang electrode 111 is twice the thickness of the outermost metal conductive layer 423 of the upper electrical connection support column 400, when the thickness of the metal material deposited in the trench 303 of the upper electrical connection support column 400 is the thickness of the outermost metal conductive layer 423 of the upper electrical connection support column 400, the metal thin film layers 304 of both sidewalls of the trench 302 of the overhang electrode 111 contact to form the overhang electrode 111, as shown in fig. 10D.
After the overhang electrode 111 is formed, a dielectric material is deposited continuously to form a dielectric thin film layer 305, as shown in fig. 10D, since the trench 302 of the overhang electrode 111 is filled with titanium nitride TiN, the dielectric material cannot enter the trench 302 of the overhang electrode 111, the dielectric material is deposited continuously only in the surface of the trench 303 and the metal thin film layer 304 of the upper electrical connection support pillar 400 to form the dielectric thin film layer 305, the metal thin film layer 304 and the dielectric thin film layer 305 on the surface of the sacrificial layer 301 are removed by wet etching or dry etching, then a metal material is deposited continuously, the metal material is deposited only on the surface of the trench 303 and the sacrificial layer 301 of the upper electrical connection support pillar 400, excess metal material is etched continuously to form another metal conductive layer 423 electrically connected to the support pillar 400, and the steps are repeated to form the metal conductive layer 423 and the dielectric layer 425 which are arranged at intervals, as shown in fig. 10D.
In the above technical solution, by setting the width of the overhang electrode 111 to be twice the thickness of the outermost metal conductive layer 423 of the upper electrical connection support column 400, it is not necessary to etch the trench twice, thereby reducing the number of metallization times, reducing the process difficulty, and simplifying the process.
In one embodiment, to form the electrode absorption layer 116 on the overhang electrode 111, after etching the trench 302 of the overhang electrode 111 and the trench 303 of the upper electrical connection support post 400 on the sacrificial layer 301, a multi-layered absorption layer film is deposited in the trench 302 of the overhang electrode 111 and the trench 303 of the upper electrical connection support post 400 in the order of a silicon nitride (SiN) film layer, a silicon oxynitride (SiON) film layer, and a silicon dioxide (SiO) film layer2) A thin film layer to form a multi-layered absorption layer film on the bottom and both sidewalls of the trench 302 of the overhang electrode 111 and the bottom and both sidewalls of the trench 303 of the electrical connection support pillar 400. And the absorption layer film at the bottom of the trench 303 of the upper electrical connection support column 400 and the absorption layer film on the surface of the sacrificial layer 301 are removed by using the anisotropic etching process in the vertical direction, the remaining absorption layer film in the trench 303 of the upper electrical connection support column 400 can be used as the isolation protection layer 424, and the upper electrical connection support column 400 is electrically connected with the next interconnect layer 702 in the semiconductor substrate 700 by removing the absorption layer film at the bottom of the trench 303 of the upper electrical connection support column 400. The multi-layer absorption layer film in the groove of the overhung electrode 111 is used as the electrode absorption layer 116, and then metal materials are deposited in the groove 302 of the overhung electrode 111 and the groove 303 of the upper electrical connection support pillar 400, so as to form a metal thin film layer 304 on the electrode absorption layer 116 in the groove of the overhung electrode 111, and form the metal thin film layer 304 on the two sidewalls and the bottom of the groove of the upper electrical connection support pillar 400, so as to form the overhung electrode 111 with the electrode absorption layer 116 attached to the outside and the metal conductive layer 423 on the outermost layer of the upper electrical connection support pillar 400.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: it is also possible to modify the solutions described in the previous embodiments or to substitute some or all of them with equivalents. And the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A hybrid imaging chip based on semiconductor COMS technology for medical imaging, comprising: the structure comprises a semiconductor substrate, a micro-bridge structure, a serpentine beam structure and an upper electric connection supporting column;
the upper electric connection supporting column is positioned on the semiconductor substrate and is connected with the micro-bridge structure through the serpentine beam structure, so that the micro-bridge structure is suspended above the semiconductor substrate; a variable capacitor is arranged in the micro-bridge structure, and the capacitance of the variable capacitor changes after the micro-bridge structure absorbs infrared light;
the micro-bridge structure comprises a micro-bridge surface, wherein the micro-bridge surface comprises a P-type semiconductor layer, a deformation layer and an infrared absorption layer which are sequentially arranged from the top to the bottom; a transistor pair array is formed in the P-type semiconductor layer; each transistor pair includes: the P-type semiconductor layer comprises two first N-type regions arranged at the top region of the P-type semiconductor layer, two second N-type regions arranged at the bottom region of the P-type semiconductor layer, a first gate dielectric layer arranged above the two first N-type regions, a first gate electrode arranged on the first gate dielectric layer, a first source electrode arranged around one first N-type region, a first drain electrode arranged around the other first N-type region, a second gate dielectric layer arranged below the two second N-type regions, a second gate electrode arranged below the second gate dielectric layer, a second source electrode arranged around one second N-type region, and a second drain electrode arranged around the other second N-type region;
when the infrared absorption layer generates heat after absorbing infrared light to cause the deformation layer to warp, the current of a first channel between the two first N-type areas is reduced, and the current of a second channel between the two second N-type areas is increased; the first channel current and the second channel current are a pair of differential current signals, and the differential current signals are used for determining infrared light intensity.
2. The hybrid imaging chip as claimed in claim 1, wherein the first gate electrode has a U-shaped structure, the second gate electrode has a U-shaped structure, and the first gate electrode and the second gate electrode are connected to form a gate electrode having a ring shape; and the plane of the annular gate electrode is vertical to the plane of the deformation layer.
3. The hybrid imaging chip of claim 1 or 2, wherein the micro bridge deck further comprises an upper horizontal electrode parallel to the infrared absorbing layer and a vertically arranged overhung electrode; the upper electric connection supporting column comprises a plurality of metal conducting layers; the width of the overhang electrode is twice the thickness of the outermost metal conductive layer of the upper electrical connection support column, and the overhang electrode and the outermost metal conductive layer of the upper electrical connection support column are formed by one-time metallization.
4. The hybrid imaging chip as claimed in claim 3, wherein the overhang electrode is formed by forming a sacrificial layer on the semiconductor substrate, etching a trench of the overhang electrode and a trench of the upper electrical connection support post on the sacrificial layer, and depositing a metal material in the trench of the overhang electrode and the trench of the upper electrical connection support post to form a metal thin film layer on a bottom and both sidewalls of the trench of the overhang electrode and a bottom and both sidewalls of the trench of the upper electrical connection support post, and the thickness of the deposited metal material is the thickness of the metal conductive layer on the outermost layer of the upper electrical connection support post so that the metal thin film layers on both sidewalls of the trench of the overhang electrode are in contact with each other.
5. The hybrid imaging chip of claim 3, wherein said micro-bridge deck further comprises a plurality of connecting metals; a portion of the connection metal is located between the first drain electrodes of two adjacent transistor pairs to interconnect the first drain electrodes of the two adjacent transistor pairs, a portion of the connection metal is located between the second drain electrodes of two adjacent transistor pairs to interconnect the second drain electrodes of the two adjacent transistor pairs, a portion of the connection metal is located between the first source electrodes of two adjacent transistor pairs to interconnect the first source electrodes of the two adjacent transistor pairs, and a portion of the connection metal is located between the second source electrodes of two adjacent transistor pairs to interconnect the second source electrodes of the two adjacent transistor pairs.
6. The hybrid imaging chip of claim 5, wherein said micro-bridge deck further comprises a first force-sensitive resistive layer and a second force-sensitive resistive layer; the area of the first force-sensitive resistance layer is the same as that of the second force-sensitive resistance layer, and the area of the first force-sensitive resistance layer is the same as that of the deformation layer;
the resistance value of the first force sensitive resistance layer becomes small after being stressed, and the resistance value of the second force sensitive resistance layer becomes large after being stressed; one end of the first force-sensitive resistance layer is connected with the first drain electrode of each transistor pair; one end of the second force sensitive resistor layer is connected to the second drain electrode of each of the transistor pairs.
7. The hybrid imaging chip of claim 4, wherein an electrode absorption layer is attached to the surface of the suspended electrode, the electrode absorption layer comprises a silicon nitride film layer, a silicon oxynitride film layer and a silicon dioxide film layer which are sequentially arranged from outside to inside, infrared light which is reflected for multiple times between the suspended electrodes is absorbed by the electrode absorption layer for multiple times, the electrode absorption layer generates heat after absorbing the infrared light, and the suspended electrode is used for transferring heat to the micro bridge deck.
8. The hybrid imaging chip as claimed in claim 7, wherein after the trenches of the overhang electrodes and the trenches of the upper electrical connection support posts are etched on the sacrificial layer, a multi-layer absorption layer film is deposited in the trenches of the overhang electrodes and the trenches of the upper electrical connection support posts to form a multi-layer absorption layer film on the bottom and both sidewalls of the trenches of the overhang electrodes and the bottom and both sidewalls of the trenches of the upper electrical connection support posts, and the absorption layer film on the bottom of the trenches of the upper electrical connection support posts and the absorption layer film on the surface of the sacrificial layer are removed using a vertical anisotropic etching process to form electrode absorption layers in the trenches of the overhang electrodes and isolation protection layers in the trenches of the upper electrical connection support posts; and depositing a metal material on the electrode absorption layer and the isolation protection layer to form a metal film layer so as to form the metal conducting layer on the outermost layer of the suspension electrode and the upper electric connection supporting column through once metallization.
9. The hybrid imaging chip of claim 1, wherein a seventh transistor and an eighth transistor are formed within the semiconductor substrate;
wherein the seventh transistor is provided with a third source electrode, a third drain electrode, a third gate electrode and a third substrate end; the eighth transistor is provided with a fourth source electrode, a fourth drain electrode, a fourth gate electrode and a fourth substrate end;
a third substrate end of the seventh transistor is connected to the third drain electrode, the third drain electrode serves as a first end of the variable filter resistor, the third source electrode serves as a second end of the variable filter resistor, and the third gate electrode serves as a control end of the variable filter resistor;
the fourth drain electrode, the fourth source electrode and the fourth substrate end of the eighth transistor are connected to serve as a first end of a filter capacitor, and the fourth gate electrode serves as a second end of the filter capacitor;
the second end of the filter capacitor is connected with the second power supply end with adjustable amplitude, the control end of the variable filter resistor is connected with the first power supply end with adjustable amplitude, the first end of the filter capacitor is connected with the second end of the variable capacitor, and the first end of the variable filter resistor is connected with the second end of the variable capacitor.
10. The hybrid imaging chip of claim 9, wherein the signal applied to the third gate electrode of the seventh transistor is adjusted according to the magnitude of the current signal output from the upper horizontal electrode to adjust the resistance of the variable filter resistor; and adjusting the voltage applied to the fourth gate electrode of the eighth transistor according to the magnitude of the current signal output by the upper horizontal electrode, so as to adjust the capacitance of the eighth transistor.
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