CN113937121B - Infrared imaging chip for medical application and compatible with semiconductor process - Google Patents
Infrared imaging chip for medical application and compatible with semiconductor process Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/0059—Measuring for diagnostic purposes; Identification of persons using light, e.g. diagnosis by transillumination, diascopy, fluorescence
- A61B5/0075—Measuring for diagnostic purposes; Identification of persons using light, e.g. diagnosis by transillumination, diascopy, fluorescence by spectroscopy, i.e. measuring spectra, e.g. Raman spectroscopy, infrared absorption spectroscopy
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/01—Measuring temperature of body parts ; Diagnostic temperature sensing, e.g. for malignant or inflamed tissue
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/34—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using capacitors, e.g. pyroelectric capacitors
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J2005/0077—Imaging
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Abstract
The application provides an infrared imaging chip for medical applications and compatible with semiconductor processes, comprising: the semiconductor device comprises a P-type semiconductor substrate, two first N-type regions are formed in the semiconductor substrate, a first gate dielectric layer is formed above the two first N-type regions, a first gate electrode is formed on the first gate dielectric layer, a first source electrode is formed around one first N-type region, a first drain electrode is formed around the other first N-type region, and a first substrate end is formed in the semiconductor substrate; connecting the first source electrode, the first drain electrode and the first substrate end to form a first end of the fixed capacitor transistor, wherein the first gate electrode is used as a second end of the fixed capacitor transistor; the first gate electrode is connected with a power supply end with a fixed amplitude, the first end of the capacitor transistor is connected with the second end of the variable capacitor and then connected with the input end of a processing circuit in the semiconductor substrate, the capacitance of the fixed capacitor transistor is equal to the initial value of the variable capacitor, and through the arrangement, signal reading is achieved.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an infrared imaging chip which is oriented to medical application and compatible with a semiconductor process.
Background
An infrared imaging chip relates to the technical field of semiconductors, in particular to a thermal detector, which is based on the principle that a microbridge structure is utilized to absorb infrared rays radiated by an external object, changes of signals such as resistance and capacitance are generated, and a reading circuit is utilized to read the signals so as to obtain the intensity degree of infrared signals radiated by the external object. Therefore, it is an important part of the design of the infrared imaging chip how to design the readout circuit.
Disclosure of Invention
An embodiment of the present application provides an infrared imaging chip compatible with a semiconductor process and oriented to medical applications, including: the micro-bridge structure comprises a semiconductor substrate, a micro-bridge structure and an electric connection support column;
the electric connection supporting column is positioned on the semiconductor substrate and connected with the micro-bridge structure, so that the micro-bridge structure is suspended above the semiconductor substrate; the micro-bridge structure is internally provided with a variable capacitor, and the capacitance of the variable capacitor changes after the micro-bridge structure absorbs infrared light;
the semiconductor substrate is a P-type substrate, two first N-type regions are formed in the semiconductor substrate, a first gate dielectric layer is formed above the two first N-type regions, and a first gate electrode is formed on the first gate dielectric layer; forming a first source electrode around one of the first N-type regions, forming a first drain electrode around the other first N-type region, and forming a first substrate end in the semiconductor substrate; connecting the first source electrode, the first drain electrode and the first substrate end to form a first end of the fixed capacitor transistor, wherein the first gate electrode is used as a second end of the fixed capacitor transistor; the first gate electrode is connected with a power supply end with a fixed amplitude, the first end of the capacitor transistor is connected with the second end of the variable capacitor and then connected with the input end of a processing circuit in the semiconductor substrate, and the capacitance of the fixed capacitor transistor is equal to the initial value of the variable capacitor; after the micro-bridge structure absorbs infrared light, the variable capacitor or the fixed capacitor transistor discharges to the input end of the processing circuit, and the infrared light intensity is obtained by monitoring the discharge current.
In the technical scheme, two first N-type regions are formed in a P-type semiconductor substrate, a first gate dielectric layer is formed above the two first N-type regions, and a first gate electrode, a first source electrode, a first drain electrode and a first substrate end are arranged to form the transistor. Connecting a first source electrode, a first drain electrode and a first substrate end of a transistor to form a first end of a fixed capacitor transistor, taking a first gate electrode as a second end of the fixed capacitor transistor, connecting the first end of the fixed capacitor transistor to a second end of a variable capacitor, connecting the first gate electrode to a power supply end with a fixed amplitude, and making an initial value of the variable capacitor equal to a capacitance of the fixed capacitor transistor, wherein the variable capacitor or the fixed capacitor transistor does not discharge before the micro-bridge structure absorbs infrared light, no discharge current exists at an input end of the processing circuit, the capacitance of the variable capacitor changes after the micro-bridge structure absorbs infrared light, the capacitance of the variable capacitor is not equal to the capacitance of the fixed capacitor transistor, so that the variable capacitor or the fixed capacitor transistor discharges to the input end of the processing circuit, and the capacitance change is converted into a discharge current, the infrared light intensity is obtained by monitoring the discharge current, so that the capacitance variation is read.
In one embodiment, two second N-type regions are formed in the semiconductor substrate, a second gate dielectric layer is formed above the two second N-type regions, and a second gate electrode is formed on the second gate dielectric layer; a second source electrode is formed around one of the second N-type regions, a second drain electrode is formed around the other second N-type region to form a variable resistor, the second drain electrode is used as a first end of the variable resistor, the second source electrode is used as a second end of the variable resistor, and the first end of the variable resistor is connected with a second end of the variable capacitor;
forming two third N-type regions in the semiconductor substrate, forming a third gate dielectric layer above the two third N-type regions, and forming a third gate electrode on the third gate dielectric layer; and a third source electrode is formed around one of the third N-type regions, a third drain electrode is formed around the other third N-type region, a third substrate end is formed in the semiconductor substrate, the third drain electrode and the third source electrode are connected with the third substrate end to form a filter capacitor, the third substrate end is a first end of the filter capacitor, the third gate electrode is a second end of the filter capacitor, the first end of the filter capacitor is connected with a second end of the variable capacitor, and the second end of the filter capacitor is connected with a power supply end with adjustable amplitude.
In the above technical solution, two transistors are formed in a semiconductor substrate, one of the transistors operates in a linear resistance region to form a variable resistor, a third source electrode, a third drain electrode and a third substrate terminal of the other transistor are connected, and a third gate electrode is connected to a power supply terminal with adjustable amplitude, so as to form a filter capacitor with adjustable capacitance, so that the filter capacitor and the variable resistor form an RC oscillator, and an oscillation signal output by a second terminal of the variable capacitor due to a resonant cavity in a microbridge structure is suppressed or eliminated. In addition, the resistance value of the variable resistor is variable, the capacitance of the filter capacitor is also variable, and the resistance value of the variable resistor and the capacitance of the filter capacitor can be adjusted by adjusting the voltage of the second gate electrode of the variable resistor and the amplitude of the power supply end connected with the third gate electrode of the filter capacitor, so that the oscillation signal can be better eliminated.
In one embodiment, a microbridge structure includes: the upper micro-bridge structure, the middle micro-bridge structure and the lower micro-bridge structure are sequentially arranged from top to bottom along the direction far away from the semiconductor substrate;
wherein, go up the microbridge structure and include: an upper micro bridge deck, a plurality of first upper suspended electrodes and a plurality of second upper suspended electrodes; the medium and micro bridge structure comprises: the micro-bridge comprises a middle micro-bridge surface, a plurality of first middle suspension electrodes and a plurality of third middle suspension electrodes;
the upper micro bridge deck is opposite to the middle micro bridge deck, one end of each of the first middle suspension electrodes and one end of each of the third middle suspension electrodes are connected with one side of the middle micro bridge deck opposite to the upper micro bridge deck, and one end of each of the first upper suspension electrodes and one end of each of the second upper suspension electrodes are connected with one side of the upper micro bridge deck opposite to the middle micro bridge deck;
the length of the second upper suspended electrode is less than half of the length of the first upper suspended electrode, and the length of the third middle suspended electrode is less than half of the length of the first middle suspended electrode;
the first upper suspended electrode and the second upper suspended electrode are covered with electrode absorption layers, and the first middle suspended electrode and the third middle suspended electrode are covered with electrode absorption layers;
each second upper suspended electrode is positioned between two first upper suspended electrodes, and each third middle suspended electrode is positioned between two first middle suspended electrodes;
each first upper suspended electrode is arranged adjacent to at least one first middle suspended electrode, and each first middle suspended electrode is arranged adjacent to at least one first upper suspended electrode;
the electrode absorption layer comprises a silicon nitride film layer, a silicon oxynitride film layer and a silicon dioxide film layer which are sequentially arranged from outside to inside.
In the above-described embodiment, since the first upper suspended electrode and the first middle suspended electrode are used to form the interdigital capacitor, the distance between the first upper suspended electrode and the first middle suspended electrode is large to avoid the interdigital capacitor from breakdown. However, the larger distance can cause that infrared light cannot enter the first upper suspended electrode and the first middle suspended electrode after entering the suspended electrode area, so that the electrode absorption layers on the first upper suspended electrode and the first middle suspended electrode cannot absorb the infrared light, the second upper suspended electrode with shorter length is arranged between the two first upper suspended electrodes, the third middle suspended electrode with shorter length is arranged between the two first middle suspended electrodes, the second upper suspended electrode and the third middle suspended electrode form reflection in the suspended electrode area, so that the infrared light can enter the electrode absorption layers on the first upper suspended electrode and the first middle suspended electrode, the electrode absorption layers generate heat after absorbing the infrared light, and the electrode absorption layers can absorb more infrared light and generate more heat, so that the upper deformation layer generates more deformation, and the first upper suspended electrode and the upper flat plate electrode are driven to move relative to the middle micro-bridge structure, the capacitance variation of the capacitor formed between the upper micro-bridge structure and the middle micro-bridge structure is larger, and the sensitivity of the infrared imaging chip is improved.
In addition, the electrode absorption layer is of a laminated film structure and is used for absorbing infrared light and then heating, the suspension electrodes are made of metal materials and have good heat conduction performance, and therefore after the infrared light is reflected and absorbed between the two suspension electrodes for multiple times, the heat can be conducted to the micro bridge floor through the suspension electrodes, and the absorption effect is enhanced. And the electrode absorption layer is a silicon nitride film layer, a silicon oxynitride film layer and a silicon dioxide film layer which are arranged from outside to inside in sequence, so that the absorption efficiency of the electrode absorption layer can be improved.
In one embodiment, the lower microbridge structure includes: a lower micro bridge deck, a plurality of first lower overhang electrodes, and a plurality of second lower overhang electrodes; the medium and micro bridge structure comprises: a plurality of second middle suspended electrodes and a plurality of fourth middle suspended electrodes;
the lower micro bridge deck is opposite to the middle micro bridge deck, one end of each of the second middle suspension electrodes and one end of each of the fourth middle suspension electrodes are connected with one side, opposite to the lower micro bridge deck, of the middle micro bridge deck, and one end of each of the first lower suspension electrodes and one end of each of the second lower suspension electrodes are connected with one side, opposite to the middle micro bridge deck, of the lower micro bridge deck;
the length of the second lower overhang electrode is less than half of the length of the first lower overhang electrode, and the length of the fourth middle overhang electrode is less than half of the length of the second middle overhang electrode;
the first lower suspension electrode and the second lower suspension electrode are covered with electrode absorption layers, and the second middle suspension electrode and the fourth middle suspension electrode are covered with electrode absorption layers;
each second lower suspended electrode is positioned between two first lower suspended electrodes, and each fourth middle suspended electrode is positioned between two second middle suspended electrodes;
and each first lower overhang electrode is disposed adjacent to at least one second middle overhang electrode, and each second middle overhang electrode is disposed adjacent to at least one first lower overhang electrode.
In one embodiment, the upper micro bridge deck includes an upper infrared absorbing layer and an upper deformation layer; the upper infrared absorption layer is positioned above the upper deformation layer, the upper deformation layer is contacted with the electrode absorption layer on the first upper suspended electrode, and the upper deformation layer is contacted with the electrode absorption layer on the second upper suspended electrode; the expansion coefficient of the uppermost layer of the upper deformation layer is smaller than that of the lowermost layer of the upper deformation layer;
the middle micro bridge deck comprises a middle infrared absorption layer and a middle deformation layer; the middle infrared absorption layer is positioned above the middle deformation layer, and the middle deformation layer is contacted with the electrode absorption layer of the first middle suspended electrode, the electrode absorption layer of the second middle suspended electrode, the electrode absorption layer of the third middle suspended electrode and the electrode absorption layer of the fourth middle suspended electrode; the expansion coefficient of the uppermost layer of the middle deformation layer is equal to the expansion coefficient of the lowermost layer of the middle deformation layer;
the lower micro bridge surface comprises a lower infrared absorption layer and a lower deformation layer; the lower infrared absorption layer is positioned below the lower deformation layer, the lower deformation layer is contacted with the electrode absorption layer of the first lower suspension electrode, the lower deformation layer is contacted with the electrode absorption layer of the second lower suspension electrode, and the lower flat electrode is positioned above the lower deformation layer; and the expansion coefficient of the uppermost layer of the lower deformation layer is greater than that of the lowermost layer of the lower deformation layer.
In the technical scheme, an upper micro-bridge structure, a middle micro-bridge structure and a lower micro-bridge structure are sequentially arranged from top to bottom, the expansion coefficient of the uppermost layer of a middle deformation layer is equal to the expansion coefficient of the lowermost layer of the middle deformation layer, the middle micro-bridge structure is not warped, the expansion coefficient of the uppermost layer of the upper deformation layer is smaller than the expansion coefficient of the lowermost layer of the upper deformation layer, the upper micro-bridge structure is used for warping upwards relative to the middle micro-bridge structure after absorbing infrared light so as to change the capacitance formed between the upper micro-bridge structure and the middle micro-bridge structure, the expansion coefficient of the uppermost layer of the lower deformation layer is larger than the expansion coefficient of the lowermost layer of the lower deformation layer, the lower micro-bridge structure is used for warping downwards relative to the middle micro-bridge structure after absorbing infrared light so as to change the capacitance formed between the middle micro-bridge structure and the lower micro-bridge structure, and the capacitance change of the infrared imaging chip can be increased by the arrangement, therefore, the sensitivity of the infrared imaging chip is improved, and the three microbridge structures are sequentially arranged from top to bottom without increasing the area of the infrared imaging chip.
In one embodiment, the projection of the second upper suspended electrode on the semiconductor substrate is coincident with the projection of the first middle suspended electrode on the semiconductor substrate; the projection of the first upper suspended electrode on the semiconductor substrate is superposed with the projection of the third middle suspended electrode on the semiconductor substrate;
a projection of the second lower suspended electrode on the semiconductor substrate coincides with a projection of the second middle suspended electrode on the semiconductor substrate; the projection of the first lower suspended electrode on the semiconductor substrate coincides with the projection of the fourth middle suspended electrode on the semiconductor substrate.
In the technical scheme, the area of the suspension electrode area can be fully utilized, the distance between the suspension electrodes for forming the interdigital capacitor is not increased, and infrared light can be reflected in the suspension electrode area, so that the micro-bridge structure absorbs more infrared light, and the sensitivity of the infrared imaging chip is improved.
In one embodiment, a mesomicrobridge structure includes: a first and second overhanging reflective ring;
wherein the first suspended reflective ring is fixed on a side of the middle micro bridge deck opposite to the upper micro bridge deck, and the plurality of first middle suspended electrodes and the plurality of third middle suspended electrodes are located within the first suspended reflective ring; the second suspended reflective ring is fixed on one side of the middle micro bridge surface opposite to the lower micro bridge surface, and the plurality of second middle suspended electrodes and the plurality of fourth middle suspended electrodes are positioned in the second suspended reflective ring;
and a substrate reflecting layer is arranged in the semiconductor substrate and is positioned above the subsequent interconnection layer.
In the above technical solution, by arranging the first overhanging reflection ring and the substrate reflection layer, infrared light can be reflected by the first overhanging reflection ring when being incident to the edge of the overhanging electrode region, and the substrate reflection layer can also reflect infrared light input to the substrate, so as to form multiple absorption in the overhanging electrode region, increase the capacitance variation of the variable capacitance, and thereby improve the sensitivity of the infrared imaging chip. And the substrate reflecting layer positioned on the semiconductor substrate can prevent devices in the semiconductor substrate from being influenced by illumination, so that the working reliability of the infrared imaging chip is improved.
In one embodiment, the electrical connection support columns include an upper electrical connection support column and a lower electrical connection support column;
the upper electric connection supporting column and the lower electric connection supporting column are both positioned on the semiconductor substrate; one end of the middle micro-bridge structure is connected with the upper electric connection supporting column, and the other end of the middle micro-bridge structure is connected with the lower electric connection supporting column so as to fix the middle micro-bridge structure;
in one embodiment, the infrared imaging chip further comprises: an upper serpentine beam structure and a lower serpentine beam structure;
one end of the upper micro-bridge structure is connected with the upper electric connection supporting column through the upper serpentine beam structure, so that the upper serpentine beam structure, the upper micro-bridge structure and the upper electric connection supporting column form a cantilever beam; one end of the lower micro-bridge structure is connected with the lower electric connection supporting column through the lower serpentine beam structure, so that the lower serpentine beam structure, the lower micro-bridge structure and the lower electric connection supporting column form a cantilever beam; or
One end of the upper micro-bridge structure is connected with the upper electric connection supporting column through the upper serpentine beam structure, so that the upper serpentine beam structure, the upper micro-bridge structure and the upper electric connection supporting column form a cantilever beam; one end of the lower micro-bridge structure is connected with the upper electric connection supporting column through the lower serpentine beam structure, so that the lower serpentine beam structure, the lower micro-bridge structure and the upper electric connection supporting column form a cantilever beam.
In one embodiment, the upper microbridge surface further comprises a force-sensitive resistor; the area of the force sensitive resistor is the same as that of the upper deformation layer; the resistance value of the force sensitive resistor is increased after the force sensitive resistor is stressed, and one end of the force sensitive resistor is connected with the input end of the processing circuit.
In the technical scheme, the force sensitive resistor with the resistance value becoming larger along with the increase of the pressure value is arranged on the surface of the upper micro-bridge, the force sensitive resistor is connected with the second end of the variable capacitor, after the variable capacitor changes and outputs the discharge current at the second end of the variable capacitor, the discharge current can be further converted into a voltage signal, and when the deformation of the upper deformation layer is larger, the capacitance change is larger, the discharge current is larger, the resistance value of the force sensitive resistor is larger, the obtained voltage signal is larger, and therefore the sensitivity of the infrared imaging chip can be improved.
In one embodiment, a back-end interconnection layer is arranged in the semiconductor substrate, and the first source electrode, the first drain electrode and the first substrate end are connected through the back-end interconnection layer; the upper electric connection support column is internally provided with a plurality of metal layers, and the variable capacitor is connected with a subsequent interconnection layer through the plurality of metal layers so as to be connected with the fixed capacitor transistor.
Drawings
In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a front view of an infrared imaging chip according to an embodiment of the present disclosure;
FIG. 2 is a front view of a semiconductor substrate in an infrared imaging chip according to an embodiment of the present application;
FIG. 3 is a graph illustrating capacitance characteristics of a capacitor transistor according to an embodiment of the present disclosure;
FIG. 4 is a front view of a power-on connection support column provided in the embodiment of FIG. 1 of the present application;
FIG. 5 is a top view of an infrared imaging chip provided in the embodiment of FIG. 1 of the present application;
FIG. 6 is a front view of an infrared imaging chip according to another embodiment of the present application;
FIG. 7 is a diagram of the optical path within an overhang electrode region in an infrared imaging chip provided herein;
fig. 8 is a top view of a first overhung reflective loop on a medium bridge plane according to an embodiment of the disclosure.
Detailed Description
To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The infrared imaging chip that this application provided is mainly applied to the medical field, for example: the infrared imaging chip is used for monitoring the human body temperature, namely, infrared light emitted by human body heat radiation is monitored by using the infrared imaging chip, so that the non-contact monitoring of the human body temperature is realized, and the efficiency of monitoring the human body temperature can be improved.
As shown in fig. 1, an embodiment of the present application provides an infrared imaging chip for medical applications and compatible with semiconductor processes, which includes a semiconductor substrate 700, a micro-bridge structure, and electrical connection support pillars. Wherein the micro-bridge structure includes an upper micro-bridge structure 100, a middle micro-bridge structure 200, and a lower micro-bridge structure 300. The electrical connection support columns include an upper electrical connection support column 400 and a lower electrical connection support column 500.
The upper electrical connection support posts 400 and the lower electrical connection support posts 500 are located on the semiconductor substrate 700, and the two electrical connection support posts are connected with the three micro-bridge structures so that the two micro-bridge structures are suspended above the semiconductor substrate 700. The three micro-bridge structures are provided with variable capacitors therein, after the three micro-bridge structures absorb infrared light, the two micro-bridge structures suspended above the semiconductor substrate 700 are deformed to cause capacitance variation of the internal variable capacitors, and the capacitance variation is read by a reading circuit (not shown) in the semiconductor substrate 700 to obtain infrared light intensity according to the capacitance variation.
As shown in fig. 2, a front device region 703 and a back interconnection layer 702 are provided in a semiconductor substrate 700. The semiconductor substrate 700 is a P-type substrate, two first N-type regions 601 are formed in a front channel device region 703 in the semiconductor substrate 700, a first gate dielectric layer 603 is formed above the two first N-type regions 601, and a first gate electrode 604 is formed on the first gate dielectric layer 603. A first source electrode 605 is formed around one first N-type region 601, a first drain electrode 606 is formed around the other first N-type region 601, and a first substrate end (not shown) is formed in the semiconductor substrate 700. By so doing, one transistor is formed in the semiconductor substrate 700. The first source electrode 605, the first drain electrode 606, and the first substrate terminal are connected, and the first gate electrode 604 is connected to a power supply terminal whose amplitude is not adjustable.
Fig. 3 is a capacitance characteristic diagram of a capacitor transistor according to an embodiment of the present application, as shown in fig. 3, where the ordinate represents the capacitance C of the transistor, the abscissa represents the gate electrode voltage vg, and the gate electrode voltage is the voltage at the opposite end. When the gate voltage is smaller than the flat band voltage Vfb, the transistor capacitance is in an accumulation region, and when the gate voltage is larger than the threshold voltage Vt, the transistor capacitance is in an inversion region. The capacitance of the capacitor transistor is fixed in the accumulation region and the inversion region. The fixed capacitor transistor is formed by doping ions in the semiconductor substrate 700 such that a gate voltage corresponding to the capacitance variable region is left at an origin, connecting the first gate electrode 604 to a power source terminal having a fixed magnitude, and making the voltage of the first gate electrode 604 smaller than a flat band voltage Vfb or larger than a threshold voltage Vt. The capacitance of the fixed capacitor transistor is constant with respect to the variable capacitance inside the microbridge structure. The first source electrode 605, the first drain electrode 606, and the first substrate terminal are connected to form a first terminal of the fixed capacitor transistor, and the first gate electrode 604 serves as a second terminal of the fixed capacitor transistor.
To enable the readout of the capacitance variation of the variable capacitance, the read circuitry within the semiconductor substrate 700 includes fixed capacitance transistors and processing circuitry 620. The first terminal of the fixed capacitor transistor is connected to the second terminal of the variable capacitor and then to the input of the processing circuit 620 in the semiconductor substrate 700.
In one embodiment, a back-end interconnect layer 702 is provided within the semiconductor substrate 700, and the first source electrode 605, the first drain electrode 606, and the first substrate terminal are connected through the back-end interconnect layer 702 to form a fixed capacitance transistor. A plurality of metal layers are arranged in the two electric connection support columns, and the variable capacitor is connected with the subsequent interconnection layer 702 through the plurality of metal layers in the two electric connection support columns, so that the second end of the variable capacitor is connected with the first end of the fixed capacitor transistor. Wherein the capacitance of the fixed capacitor is equal to the initial amount of the variable capacitor. Capacitance variation detection is achieved by detecting the input current of processing circuit 620 by providing a voltage of non-adjustable magnitude to the first terminal of the variable capacitance and the second terminal of the fixed capacitance transistor.
When the micro-bridge structure does not absorb infrared light, the initial value of the variable capacitor in the micro-bridge structure is equal to the capacitance of the fixed capacitor transistor, the initial charge amount stored on the variable capacitor is the same as the charge amount on the fixed capacitor transistor, and the charges on the variable capacitor or the fixed capacitor transistor are not transferred and are used as a reference state. When the micro-bridge structure absorbs infrared light, the capacitance of the variable capacitor changes, the charge amount stored on the variable capacitor is different from the charge amount stored on the fixed capacitor transistor, the variable capacitor or the fixed capacitor transistor discharges to the input end of the processing circuit 620, and the infrared light intensity is obtained by monitoring the discharge current.
In the above technical solution, two first N-type regions are formed in the front channel device region 703 of the P-type semiconductor substrate 700, a first gate dielectric layer 603 is formed above the two first N-type regions, and a first gate electrode 604, a first source electrode 605, a first drain electrode 606, and a first substrate end are arranged to form a transistor. The first source electrode 605, the first drain electrode 606 and the first substrate end of the transistor are short-circuited to form a first end of a fixed capacitor transistor, the first gate electrode 604 is used as a second end of the fixed capacitor transistor, the first end of the fixed capacitor transistor is connected with a second end of a variable capacitor, the initial value of the variable capacitor is equal to the capacitance of the fixed capacitor transistor, so that after the micro-bridge structure absorbs infrared light, the variable capacitor or the fixed capacitor transistor discharges to the input end of the processing circuit 620, and the infrared light intensity is obtained by monitoring the discharge current.
With continued reference to fig. 2, two second N-type regions 611 are formed in the semiconductor substrate 700, a second gate dielectric layer 613 is formed over the two second N-type regions 611, a second gate electrode 614 is formed on the second gate dielectric layer 613, a second source electrode 615 is formed around one of the second N-type regions 611, and a second drain electrode 616 is formed around the other of the second N-type regions 611, by which another transistor is formed in the semiconductor substrate 700. The transistor is operated in the linear resistance area, so that the transistor is used as a variable resistor. The second drain electrode 616 serves as a first terminal of the variable resistor, and the second source electrode 615 serves as a second terminal of the variable resistor.
Two third N-type regions (not shown) are formed in the semiconductor substrate 700, a third gate dielectric layer is formed over the two third N-type regions, and a third gate electrode is formed on the third gate dielectric layer. A third source electrode is formed around one of the third N-type regions, a third drain electrode is formed around the other third N-type region, and a third pad terminal is formed in the semiconductor substrate 700 to connect the third drain electrode, the third source electrode, and the third pad terminal. And connecting the third gate electrode with the power supply end with adjustable amplitude, and continuing to refer to fig. 3, when the voltage of the third gate electrode is greater than the flat band voltage Vfb and less than the threshold voltage Vt, the capacitance of the capacitor transistor changes. The capacitance-adjustable filter capacitor is formed by doping ions in the semiconductor substrate 700 such that a gate voltage corresponding to the capacitance-variable region is left of an origin, and by applying a negative voltage between a flat band voltage Vfb and a threshold voltage Vt to the third gate electrode. The third substrate end is used as the first end of the filter capacitor, the first end of the filter capacitor is connected with the second end of the variable capacitor, the first end of the variable resistor is connected with the second end of the variable capacitor, and the filter capacitor and the variable resistor form an RC oscillator.
Because the resonant cavity is formed in the micro-bridge structure, infrared light can be absorbed by the micro-bridge structure after being reflected for many times after being emitted into the micro-bridge structure, thus, the micro-bridge structure is easy to vibrate, the capacitance variation of the variable capacitor is also shaken, the high-frequency alternating current signal is mixed in the charge and discharge current signal output by the second end of the variable capacitor, and the frequency of the high-frequency alternating current signal is related to the intensity of the infrared light, namely the amplitude of the high-frequency alternating current signal is changed, by forming two transistors in the semiconductor substrate 700, one of which operates in the linear resistance region, forming a variable resistor, and the source and drain of the other transistor are shorted to the substrate, the gate is connected to a power supply terminal with variable amplitude, to form a filter capacitor with adjustable capacitance, so that the filter capacitor and the variable resistance tube form an RC oscillator to suppress the high frequency alternating current signal or eliminate the high frequency alternating current signal. At the moment, the filtering capacitor with adjustable capacitance is used for filtering, so that the high-frequency alternating current filter can adapt to high-frequency alternating current signals with constantly changing frequency, and the high-frequency alternating current signals are filtered to a power supply or the ground, so that filtering of different frequency bands is realized.
With continued reference to fig. 1, another embodiment of the present application provides an infrared imaging chip for medical applications and compatible with semiconductor processes, the infrared imaging chip comprising: a semiconductor substrate 700, an upper electrical connection support column 400, a lower electrical connection support column 500, an upper serpentine beam structure 800, a lower serpentine beam structure 900, an upper microbridge structure 100, a middle microbridge structure 200, a lower microbridge structure 300, and a read circuit.
The upper and lower electrical connection support pillars 400 and 500 are respectively provided at both sides of the semiconductor substrate 700. Referring to fig. 1 and 4, a first portion 401 of the upper electrical connection support column 400 is located above the semiconductor substrate 700 and a second portion 402 of the upper electrical connection support column 400 is located within the semiconductor substrate 700. The first portion 401 of the upper electrical connection support posts above the semiconductor substrate 700 is a multi-layered hollow structure, and includes a metal layer 423, a dielectric layer 425 and an isolation protection layer 424, the isolation protection layer 424 is used for buffering the dielectric layer and blocking etching, the dielectric layer 425 is used for isolating the metal layer 423, and the metal layer 423 is used for leading out electrical signals on the upper micro-bridge structure 100.
The second portion 402 of the upper electrical connection supporting column 400 located in the semiconductor substrate 700 includes a metal via 421 and a metal block 422, the metal via 421 is formed on the semiconductor substrate 700 by a through silicon via process, the metal layer 423 in the upper electrical connection supporting column 400 is connected to the metal via 421 through the metal block 422 in the semiconductor substrate 700, and the metal via 421 is connected to a read circuit, so that an electrical signal on the upper micro-bridge structure 100 is introduced into the read circuit. The reading circuit is used for converting the electric signal into infrared light intensity.
The structure of the upper electrical connection supporting column 400 is similar to that of the lower electrical connection supporting column 500, the first portion 501 of the lower electrical connection supporting column 500 is located above the semiconductor substrate 700, the second portion 502 of the lower electrical connection supporting column 500 is located in the semiconductor substrate 700, and the detailed structure of the lower electrical connection supporting column 500 is not repeated.
The upper micro-bridge structure 100, the middle micro-bridge structure 200 and the lower micro-bridge structure 300 are sequentially arranged from top to bottom along the direction far away from the semiconductor substrate 700, and the upper micro-bridge structure 100, the middle micro-bridge structure 200 and the lower micro-bridge structure 300 are all provided with electrodes so as to form capacitance between the upper micro-bridge structure 100 and the middle micro-bridge structure 200 and form capacitance between the middle micro-bridge structure 200 and the lower micro-bridge structure 300.
One end of the middle micro-bridge structure 200 is connected to the upper electrical connection support column 400, and the other end of the middle micro-bridge structure 200 is connected to the lower electrical connection support column 500, so as to fix the middle micro-bridge structure 200. One end of the upper micro-bridge structure 100 is connected to the upper electrical connection support column 400 through the upper serpentine beam structure 800, so that the upper micro-bridge structure 100, the upper serpentine beam structure 800 and the upper electrical connection support column form a cantilever beam, and thus the upper micro-bridge structure 100 moves relative to the middle micro-bridge structure 200 after absorbing infrared light, so as to change the capacitance of the capacitor formed between the upper micro-bridge structure 100 and the middle micro-bridge structure 200. One end of the lower micro-bridge structure 300 is connected to the lower electrical connection support 500 through the lower serpentine beam structure 900, so that the lower micro-bridge structure 300, the lower serpentine beam structure 900 and the lower electrical connection support constitute a cantilever beam, and thus the lower micro-bridge structure 300 moves relative to the middle micro-bridge structure 200 after absorbing infrared light, so as to change the capacitance of the capacitor formed between the lower micro-bridge structure 300 and the middle micro-bridge structure 200.
As shown in fig. 5, the upper serpentine beam structure 800 has a serpentine shape for achieving mechanical and electrical connection between the upper micro-bridge structure 100 and the upper electrical connection support column 400, and for achieving thermal isolation between the upper micro-bridge structure 100 and the upper electrical connection support column 400.
When infrared light is incident from above the infrared imaging chip, the upper micro-bridge structure 100 absorbs the infrared light, and the upper micro-bridge structure 100 moves relative to the middle micro-bridge structure 200 after absorbing the infrared light, so that the capacitance between the upper micro-bridge structure 100 and the middle micro-bridge structure 200 changes. Part of infrared light irradiates the lower micro-bridge structure 300 through the upper micro-bridge structure 100 and the middle micro-bridge structure 200, the lower micro-bridge structure 300 absorbs part of the infrared light, the lower micro-bridge structure 300 also moves relative to the middle micro-bridge structure 200 after absorbing the infrared light, so that the capacitance between the lower micro-bridge structure 300 and the middle micro-bridge structure 200 changes, and the infrared light intensity can be obtained by detecting the capacitance change of the capacitance between the upper micro-bridge structure 100 and the middle micro-bridge structure 200 and the capacitance change of the capacitance between the lower micro-bridge structure 300 and the middle micro-bridge structure 200, so as to realize the detection of the infrared light. Through so setting up, the infrared light absorbs through last microbridge structure 100 and lower microbridge structure 300, arouses the electric capacity between last microbridge structure 100 and the well microbridge structure 200 and the electric capacity change between lower microbridge structure 300 and the well microbridge structure 200, realizes that the electric capacity change volume grow of infrared imaging chip under the same infrared light intensity shines, improves infrared imaging chip's sensitivity, and can not increase infrared imaging chip's image area.
In an embodiment, referring to fig. 6, the upper and lower micro-bridge structures 100 and 300 may also connect the same electrical connection support posts. One end of the upper micro-bridge structure 100 is connected to the upper electrical connection support column 400 through the upper serpentine beam structure 800, so that the upper serpentine beam structure 800, the upper micro-bridge structure 100 and the upper electrical connection support column 400 form a cantilever. One end of the lower micro-bridge structure 300 is connected to the upper electrical connection support column 400 through the lower serpentine beam structure 900, so that the lower serpentine beam structure 900, the lower micro-bridge structure 300 and the upper electrical connection support column 400 form a cantilever.
In the above technical scheme, by setting the upper micro-bridge structure 100, the middle micro-bridge structure 200 and the lower micro-bridge structure 300 in the infrared imaging chip, a capacitor is formed between the upper micro-bridge structure 100 and the middle micro-bridge structure 200, a capacitor is formed between the middle micro-bridge structure 200 and the lower micro-bridge structure 300, when infrared light is incident from the top of the infrared imaging chip, the capacitance of the capacitor formed between the upper micro-bridge structure 100 and the middle micro-bridge structure 200 and the capacitance of the capacitor formed between the middle micro-bridge structure 200 and the lower micro-bridge structure 300 are changed, so that the capacitance change amount is increased, and the sensitivity of the infrared imaging chip is improved.
With continued reference to fig. 1, in one embodiment, the upper micro-bridge structure 100 includes an upper micro-bridge deck 101, a plurality of first upper suspended electrodes 111, and a plurality of second upper suspended electrodes 115, and the middle micro-bridge structure 200 includes a middle micro-bridge deck 201, a plurality of first middle suspended electrodes 211, and a plurality of third middle suspended electrodes 217.
The upper micro bridge deck 101 is arranged opposite to the middle micro bridge deck 201, the first upper hanging electrodes 111, the second upper hanging electrodes 115, the first middle hanging electrodes 211 and the third middle hanging electrodes 217 are located in a hanging electrode area between the upper micro bridge deck 101 and the middle micro bridge deck 201, namely, one ends of the first middle hanging electrodes 211 are connected with one side, opposite to the upper micro bridge deck 101, of the middle micro bridge deck 201, one ends of the third middle hanging electrodes 217 are connected with one side, opposite to the upper micro bridge deck 101, of the middle micro bridge deck 201, one ends of the first upper hanging electrodes 111 are connected with one side, opposite to the middle micro bridge deck 201, of the upper micro bridge deck 101, and one ends of the second upper hanging electrodes 115 are connected with one side, opposite to the middle micro bridge deck 201, of the upper micro bridge deck 101.
The plurality of first upper suspended electrodes 111 and the plurality of first middle suspended electrodes 211 are disposed at intervals, that is, each first upper suspended electrode 111 is disposed adjacent to at least one first middle suspended electrode 211, and each first middle suspended electrode 211 is disposed adjacent to at least one first upper suspended electrode 111, so that an interdigital capacitor is formed between the first upper suspended electrode 111 and the first middle suspended electrode 211.
The length of the second upper suspended electrode 115 is less than half of the length of the first upper suspended electrode 111, the length of the third middle suspended electrode 217 is less than half of the length of the first middle suspended electrode 211, the first upper suspended electrode 111 and the second upper suspended electrode 115 are both covered with electrode absorption layers, and the first middle suspended electrode 211 and the third middle suspended electrode 217 are both covered with electrode absorption layers. Each of the second upper suspended electrodes 115 is positioned between two of the first upper suspended electrodes 111, and each of the third middle suspended electrodes 217 is positioned between two of the first middle suspended electrodes 211.
In one embodiment, the upper micro-bridge plane 101 includes an upper infrared absorbing layer 114, an upper deformation layer 113, and an upper plate electrode 112. The upper infrared absorption layer 114 is located above the upper deformation layer 113, the upper deformation layer 113 is located above the upper flat electrode 112, the upper flat electrode 112 is electrically connected with the plurality of first upper suspended electrodes 111 and the plurality of second upper suspended electrodes 115, the upper deformation layer 113 is in contact with an electrode absorption layer on the first upper suspended electrodes 111, and the upper deformation layer 113 is in contact with an electrode absorption layer on the second upper suspended electrodes 115.
The middle micro-bridge surface 201 comprises a first middle plate electrode 216, a middle infrared absorption layer 212 and a middle deformation layer 213, wherein the middle infrared absorption layer 212 is located above the middle deformation layer 213, the first middle plate electrode 216 is located above the middle infrared absorption layer 212, the first middle plate electrode 216 is electrically connected with a plurality of first middle suspension electrodes 211 and a plurality of third middle suspension electrodes 217, the middle deformation layer 213 is in contact with an electrode absorption layer on the first middle suspension electrodes 211, and the middle deformation layer 213 is in contact with an electrode absorption layer on the third middle suspension electrodes 217.
The upper plate electrode 112 and the first middle plate electrode 216 form a plate capacitor, and the first middle suspended electrode 211 and the adjacent first upper suspended electrode 111 form an interdigital capacitor. The upper infrared absorption layer 114 is used to absorb infrared light and generate heat, and the electrode absorption layers on the first upper suspended electrode 111, the second upper suspended electrode 115, the first middle suspended electrode 211, and the third middle suspended electrode 217 are also used to absorb infrared light and generate heat. The upper deformation layer 113 is configured to deform after absorbing heat, so as to drive the upper plate electrode 112 and the first upper suspended electrode 111 to move, so that capacitance of a plate capacitor formed between the upper plate electrode 112 and the first middle plate electrode 216 changes, and capacitance of an interdigital capacitor formed between the first middle suspended electrode 211 and the adjacent first upper suspended electrode 111 changes.
In the above embodiment, infrared light enters from the top of the infrared imaging chip, and enters the overhanging electrode region after being absorbed by the upper infrared absorption layer 114 on the upper micro-bridge plane 101. The first upper suspended electrode 111 and the first middle suspended electrode 211 are used to form an interdigital capacitor, and the distance between the first upper suspended electrode 111 and the first middle suspended electrode 211 is large to avoid the interdigital capacitor from breakdown. As shown by the light path S2 in fig. 7, the larger distance results in that the infrared light cannot be incident on the first upper and middle suspension electrodes 111 and 211 after being incident on the suspension electrode area, and the electrode absorption layers on the first upper and middle suspension electrodes 111 and 211 cannot absorb the infrared light. As shown by the optical path S1 in fig. 7, by disposing the second upper suspended electrode 115 with a shorter length between the two first upper suspended electrodes 111 and disposing the third middle suspended electrode 217 with a shorter length between the two first middle suspended electrodes 211, reflection is formed in the suspended electrode region by the second upper suspended electrode 115 and the third middle suspended electrode 217, so that infrared light can be incident on the electrode absorption layers on the first upper suspended electrode 111 and the first middle suspended electrode 211, the electrode absorption layers generate heat after absorbing the infrared light, and the upper deformation layer 113 is deformed due to the heat generated by the electrode absorption layers and the heat generated by the upper infrared absorption layer 114, so as to move the upper flat plate electrode 112 and the first upper suspended electrode 111 relative to the middle micro-bridge structure 200, thereby causing a change in capacitance between the upper micro-bridge structure 100 and the middle micro-bridge structure 200.
Wherein, the electrode absorption layer comprises a silicon nitride (SiN) film layer, a silicon oxynitride (SiON) film layer and silicon dioxide (SiO) which are arranged in sequence from outside to inside2) A thin film layer. The electrode absorption layer is of a laminated film structure and is used for absorbing infrared light and then heating, the first upper hanging electrodes 111 are made of metal materials and have good heat conduction performance, and therefore after the infrared light is reflected and absorbed between the two first upper hanging electrodes 111 for multiple times, heat can be conducted to the upper micro-bridge surface 101 through the first upper hanging electrodes 111, and the absorption effect is enhanced. And the electrode absorption layer is a silicon nitride film layer, a silicon oxide film layer and a silicon dioxide film layer which are arranged from outside to inside in sequence, so that the absorption efficiency of the electrode absorption layer can be improved.
With continued reference to fig. 1, lower microbridge structure 300 includes a lower microbridge surface 301, a plurality of first lower overhang electrodes 311, and a plurality of second lower overhang electrodes 315, and medium microbridge structure 200 further includes a plurality of second middle overhang electrodes 215 and a plurality of fourth middle overhang electrodes 218.
The lower micro bridge deck 301 is arranged opposite to the middle micro bridge deck 201, and the first lower suspension electrode 311, the second lower suspension electrode 315, the second middle suspension electrode 215 and the fourth middle suspension electrode 218 are located in a suspension electrode area between the lower micro bridge deck 301 and the middle micro bridge deck 201, that is, one end of the plurality of second middle suspension electrodes 215 is connected with one side of the middle micro bridge deck 201 opposite to the lower micro bridge deck 301, one end of the plurality of fourth middle suspension electrodes 218 is connected with one side of the middle micro bridge deck 201 opposite to the lower micro bridge deck 301, one end of the plurality of first lower suspension electrodes 311 is connected with one side of the lower micro bridge deck 301 opposite to the middle micro bridge deck 201, and one end of the plurality of second lower suspension electrodes 315 is connected with one side of the lower micro bridge deck 301 opposite to the middle micro bridge deck 201.
Wherein the plurality of first lower overhang electrodes 311 are spaced apart from the plurality of second middle overhang electrodes 215, that is, each first lower overhang electrode 311 is disposed adjacent to at least one second middle overhang electrode 215, and each second middle overhang electrode 215 is disposed adjacent to at least one first lower overhang electrode 311, such that an interdigital capacitance is formed between the first lower overhang electrode 311 and the second middle overhang electrode 215.
The length of the second lower suspended electrode 315 is less than half of the length of the first lower suspended electrode 311, the length of the fourth middle suspended electrode 218 is less than half of the length of the second middle suspended electrode 215, the first lower suspended electrode 311 and the second lower suspended electrode 315 are both covered with an electrode absorption layer, and the second middle suspended electrode 215 and the fourth middle suspended electrode 218 are both covered with an electrode absorption layer. Each second lower suspended electrode 315 is located between two first lower suspended electrodes 311, and each fourth middle suspended electrode 218 is located between two second middle suspended electrodes 215.
In one embodiment, the lower micro bridge deck 301 includes a lower infrared absorbing layer 314, a lower deforming layer 313, and a lower plate electrode 312. The lower infrared absorption layer 314 is located below the lower deformation layer 313, the lower deformation layer 313 is in contact with the absorption layer on the first lower suspended electrode 311, the lower deformation layer 313 is also in contact with the absorption layer on the second lower suspended electrode 315, the lower deformation layer 313 is located below the lower flat electrode 312, the lower flat electrode 312 is electrically connected with the plurality of first lower suspended electrodes 311, and the lower flat electrode 312 is electrically connected with the plurality of second lower suspended electrodes 315. The middle micro-bridge surface 201 comprises a second middle plate electrode 214, the second middle plate electrode 214 is located below the middle deformation layer 213, the middle deformation layer 213 is in contact with an electrode absorption layer on the second middle suspended electrode 215, and the middle deformation layer 213 is in contact with an electrode absorption layer on the fourth middle suspended electrode 218. The second middle plate electrode 214 is electrically connected to a plurality of second middle suspension electrodes 215, and the second middle plate electrode 214 is electrically connected to a plurality of fourth middle suspension electrodes 218.
The lower plate electrode 312 and the second middle plate electrode 214 form a plate capacitor, and the second middle suspended electrode 215 and the adjacent first lower suspended electrode 311 form an interdigital capacitor. The lower infrared absorption layer 314 is used for absorbing infrared light and generating heat, the electrode absorption layer on the first lower suspension electrode 311 and the electrode absorption layer on the second lower suspension electrode 315 are also used for absorbing infrared light and generating heat, the lower deformation layer 313 is used for absorbing heat and deforming so as to drive the lower plate electrode 312 and the first lower suspension electrode 311 to move, so that capacitance of a plate capacitor formed between the lower plate electrode 312 and the second middle plate electrode 214 changes, and capacitance of an interdigital capacitor formed between the second middle suspension electrode 215 and the adjacent first lower suspension electrode 311 changes.
In the above embodiment, when the infrared light is incident into the lower suspended electrode region through the middle micro-bridge 201, the first lower suspended electrode 311 and the second middle suspended electrode 215 are used to form an interdigital capacitor, and the distance between the first lower suspended electrode 311 and the second middle suspended electrode 215 is larger to avoid the interdigital capacitor from breaking down. The larger separation distance, as shown by the optical path S4 in fig. 7, in turn, results in that the infrared light cannot be incident on the first and second suspended electrodes 311 and 215 after being incident on the suspended electrode region, and the electrode absorption layers on the first and second suspended electrodes 311 and 215 cannot absorb the infrared light. As shown by the optical path S3 in fig. 7, by disposing the second lower suspended electrode 315 with a shorter length between the two first lower suspended electrodes 311, disposing the second middle suspended electrode 215 and the fourth middle suspended electrode 218 at an interval to form reflection in the suspended electrode region through the second lower suspended electrode 315 and the fourth middle suspended electrode 218, infrared light can be incident on the electrode absorption layers on the first lower suspended electrode 311 and the second middle suspended electrode 215, the electrode absorption layers generate heat after absorbing the infrared light, and the lower deformation layer 313 is deformed due to the heat generated by the electrode absorption layers and the heat generated by the lower infrared absorption layer 314, so as to move the lower plate electrode 312 and the first lower suspended electrode 311 relative to the middle micro-bridge structure 200, thereby causing the capacitance of the capacitance between the lower micro-bridge structure 300 and the middle micro-bridge structure 200 to change.
In one embodiment, the projection of the second upper suspended electrode 115 on the semiconductor substrate 700 coincides with the projection of the first middle suspended electrode 211 on the semiconductor substrate 700, and the projection of the first upper suspended electrode 111 on the semiconductor substrate 700 coincides with the projection of the third middle suspended electrode 217 on the semiconductor substrate 700. The projection of the second lower suspended electrode 315 on the semiconductor substrate 700 coincides with the projection of the second middle suspended electrode 215 on the semiconductor substrate 700; the projection of the first lower suspended electrode 311 on the semiconductor substrate coincides with the projection of the fourth middle suspended electrode 218 on the semiconductor substrate 700. By the arrangement, the area of the suspension electrode area can be fully utilized, the distance between the suspension electrodes for forming the interdigital capacitor is not increased, and infrared light can be reflected in the suspension electrode area, so that the micro-bridge structure absorbs more infrared light, and the sensitivity of the infrared imaging chip is improved.
In one embodiment, as shown in fig. 1 and 8, the mid-microbridge structure 200 includes a first overhanging reflective loop 202, the first overhanging reflective loop 202 being secured to a side of the mid-microbridge surface 201 opposite the upper microbridge surface 101. The plurality of first middle suspended electrodes 211 and the plurality of third middle suspended electrodes 217 are located at the first suspended reflective ring 202. The first overhanging reflective ring 202 is used to prevent infrared light from exiting sideways due to multiple reflections at the overhanging electrode region. That is, when infrared light incides the electrode zone that hangs, through reflection or refraction to the electrode zone edge that hangs, infrared light is reflected to first dangling reflection ring, is favorable to absorbing many times, improves sensitivity. The area surrounded by the first overhanging reflective ring 202 is larger than the area of the overhanging electrode on the upper microbridge structure 100 so that the first overhanging reflective ring 202 does not work as an obstacle when the upper microbridge structure 100 is deformed.
In one embodiment, as shown in fig. 1 and 6, the medium micro-bridge structure 200 includes a second overhanging reflective ring 203, and the second overhanging reflective ring 203 is fixed on a side of the medium micro-bridge deck 201 opposite to the lower micro-bridge deck 301. A plurality of second middle suspended electrodes 215 and a plurality of fourth middle suspended electrodes 218 are located at the second suspended reflective ring 203. The second overhanging reflective ring 203 is used to prevent infrared light from exiting sideways due to multiple reflections at the overhanging electrode region. That is, when infrared light is incident to the suspended electrode region and is reflected or refracted to the edge of the suspended electrode region, the second suspended reflective ring 203 reflects the infrared light, which is beneficial to multiple absorption and improves the sensitivity. The area surrounded by the second overhanging reflective ring 203 is larger than the area of the overhanging electrode on the lower micro-bridge structure 300, so that the second overhanging reflective ring 203 does not work as an obstacle when the lower micro-bridge structure 300 is deformed.
In an embodiment, a substrate reflection layer 701 is disposed in the semiconductor substrate 700, the substrate reflection layer is located above the next interconnection layer 702, and the next interconnection layer 702 is located above the previous device region 703, so that on one hand, the previous device region 703 can be shielded from external optical signals to avoid the influence of the external optical signals on devices in the previous device region 703, and on the other hand, infrared light can be reflected to the lower micro-bridge structure 300, the middle micro-bridge structure 200, and the upper micro-bridge structure 100 to form multiple absorption in the overhanging electrode region, thereby increasing the absorption amount of the infrared light, so that the deformation amount of the upper micro-bridge structure 100 and the lower micro-bridge structure 300 is larger, and the detected capacitance variation amount is larger, thereby improving the sensitivity of the infrared imaging chip.
In one embodiment, the expansion coefficient of the uppermost layer of the upper deformation layer 113 is smaller than that of the lowermost layer of the upper deformation layer 113, so that after the upper infrared absorption layer 114 absorbs the infrared light to generate heat, the expansion amount of the uppermost layer of the upper deformation layer 113 is smaller than that of the lowermost layer of the upper deformation layer 113, thereby causing the upper micro deck 101 to warp upward.
In one embodiment, the uppermost layer of the lower deformation layer 313 has a higher expansion coefficient than the lowermost layer of the lower deformation layer 313, so that after the lower infrared absorption layer 314 absorbs infrared light to generate heat, the uppermost layer of the lower deformation layer 313 expands more than the lowermost layer of the lower deformation layer 313, thereby causing the lower micro deck 301 to warp downward.
In one embodiment, the expansion coefficient of the uppermost layer of the middle deformation layer 213 is equal to the expansion coefficient of the lowermost layer of the middle deformation layer 213, so that after the middle infrared absorption layer 212 absorbs the infrared light to generate heat, the expansion amount of the uppermost layer of the middle deformation layer 213 is equal to the expansion amount of the lowermost layer of the middle deformation layer 213, and the middle micro bridge deck 201 is not deformed.
In the above technical solution, the upper micro-bridge structure 100 is warped upwards after receiving infrared light by making the deformation coefficient of the uppermost layer in the upper deformation layer 113 smaller than the deformation coefficient of the lowermost layer, the lower micro-bridge structure 300 is warped downwards after receiving infrared light by making the deformation coefficient of the uppermost layer in the lower deformation layer 313 larger than the deformation coefficient of the lowermost layer, the deformation coefficient of the uppermost layer in the middle deformation layer 213 is equal to the deformation coefficient of the lowermost layer, so that the middle micro-bridge structure 200 is not deformed after receiving infrared light, after the infrared light is irradiated, the capacitance between the upper micro-bridge structure 100 and the middle micro-bridge structure 200 and the capacitance between the lower micro-bridge structure 300 and the middle micro-bridge structure 200 are both increased or decreased, and the changes of the capacitances monitored by the infrared imaging chip are superimposed, so that the sensitivity of the infrared imaging chip is higher. One end of the middle micro-bridge structure 200 is connected to the upper electrical connection support column 400, and the other end of the middle micro-bridge structure 200 is connected to the lower electrical connection support column 500, so as to further fix the middle micro-bridge structure 200.
In one embodiment, upper microbridge 101 further comprises a force-sensitive resistor (not shown). The area of the force sensitive resistor is the same as the area of the upper deformable layer 113. The resistance value of the force sensitive resistor is increased after the force sensitive resistor is stressed, and one end of the force sensitive resistor is connected with the input end of the processing circuit.
In the above technical solution, the force sensitive resistor with the resistance value increasing with the increase of the pressure value is arranged on the upper micro-bridge deck 101, the force sensitive resistor is connected with the second end of the variable capacitor, after the variable capacitor changes and outputs the discharge current at the second end, the discharge current can be further converted into a voltage signal, and when the deformation amount of the upper deformation layer 113 is larger, the capacitance change is larger, the discharge current is larger, and the resistance value of the force sensitive resistor is also larger, the obtained voltage signal is larger, so that the sensitivity of the infrared imaging chip can be improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: it is also possible to modify the solutions described in the previous embodiments or to substitute some or all of them with equivalents. And the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. An infrared imaging chip for medical applications and compatible with semiconductor processing, comprising: the micro-bridge structure comprises a semiconductor substrate, a micro-bridge structure and an electric connection support column;
the electric connection supporting column is positioned on the semiconductor substrate and is connected with the micro-bridge structure, so that the micro-bridge structure is suspended above the semiconductor substrate; a variable capacitor is arranged in the micro-bridge structure, and the capacitance of the variable capacitor changes after the micro-bridge structure absorbs infrared light;
the semiconductor substrate is a P-type substrate, two first N-type regions are formed in the semiconductor substrate, a first gate dielectric layer is formed above the two first N-type regions, and a first gate electrode is formed on the first gate dielectric layer; forming a first source electrode around one of the first N-type regions, forming a first drain electrode around the other first N-type region, and forming a first substrate end in the semiconductor substrate; connecting the first source electrode, the first drain electrode and the first substrate terminal to form a first terminal of a fixed-capacitance transistor, wherein the first gate electrode serves as a second terminal of the fixed-capacitance transistor; the first gate electrode is connected with a power supply end with a fixed amplitude, a first end of the capacitor transistor is connected with a second end of the variable capacitor and then connected with an input end of a processing circuit in the semiconductor substrate, and the capacitance of the fixed capacitor transistor is equal to the initial amount of the variable capacitor; and after the micro-bridge structure absorbs infrared light, the variable capacitor or the fixed capacitor transistor discharges to the input end of the processing circuit, and the infrared light intensity is obtained by monitoring the discharge current.
2. The infrared imaging chip of claim 1, wherein two second N-type regions are formed in the semiconductor substrate, a second gate dielectric layer is formed over the two second N-type regions, and a second gate electrode is formed on the second gate dielectric layer; a second source electrode is formed around one of the second N-type regions, a second drain electrode is formed around the other second N-type region to form a variable resistor, the second drain electrode serves as a first end of the variable resistor, the second source electrode serves as a second end of the variable resistor, and the first end of the variable resistor is connected with the second end of the variable capacitor;
forming two third N-type regions in the semiconductor substrate, forming a third gate dielectric layer above the two third N-type regions, and forming a third gate electrode on the third gate dielectric layer; a third source electrode is formed around one of the third N-type regions, a third drain electrode is formed around the other third N-type region, a third substrate end is formed in the semiconductor substrate, the third drain electrode, the third source electrode and the third substrate end are connected to form a filter capacitor, the third substrate end is a first end of the filter capacitor, the third gate electrode is a second end of the filter capacitor, the first end of the filter capacitor is connected with the second end of the variable capacitor, and the second end of the filter capacitor is connected with a power supply end with adjustable amplitude.
3. The infrared imaging chip of claim 1 or 2, wherein the microbridge structure comprises: the upper micro-bridge structure, the middle micro-bridge structure and the lower micro-bridge structure are sequentially arranged from top to bottom along the direction far away from the semiconductor substrate;
wherein the upper microbridge structure includes: an upper micro bridge deck, a plurality of first upper suspended electrodes and a plurality of second upper suspended electrodes; the medium and micro bridge structure comprises: the micro-bridge comprises a middle micro-bridge surface, a plurality of first middle suspension electrodes and a plurality of third middle suspension electrodes;
the upper micro bridge deck is opposite to the middle micro bridge deck, one end of each of the first middle suspension electrodes and one end of each of the third middle suspension electrodes are connected with one side, opposite to the upper micro bridge deck, of the middle micro bridge deck, and one end of each of the first upper suspension electrodes and one end of each of the second upper suspension electrodes are connected with one side, opposite to the middle micro bridge deck, of the upper micro bridge deck;
the length of the second upper suspended electrode is less than half of the length of the first upper suspended electrode, and the length of the third middle suspended electrode is less than half of the length of the first middle suspended electrode;
the first upper suspended electrode and the second upper suspended electrode are covered with electrode absorption layers, and the first middle suspended electrode and the third middle suspended electrode are covered with electrode absorption layers;
each of the second upper suspended electrodes is located between two of the first upper suspended electrodes, and each of the third middle suspended electrodes is located between two of the first middle suspended electrodes;
each first upper suspended electrode is arranged adjacent to at least one first middle suspended electrode, and each first middle suspended electrode is arranged adjacent to at least one first upper suspended electrode;
the electrode absorption layer comprises a silicon nitride film layer, a silicon oxynitride film layer and a silicon dioxide film layer which are sequentially arranged from outside to inside.
4. The infrared imaging chip of claim 3, wherein the lower microbridge structure comprises: a lower micro bridge deck, a plurality of first lower overhang electrodes, and a plurality of second lower overhang electrodes; the medium and micro bridge structure comprises: a plurality of second middle suspended electrodes and a plurality of fourth middle suspended electrodes;
the lower micro bridge deck is arranged opposite to the middle micro bridge deck, one end of each of the second middle suspension electrodes and one end of each of the fourth middle suspension electrodes are connected with one side of the middle micro bridge deck opposite to the lower micro bridge deck, and one end of each of the first lower suspension electrodes and one end of each of the second lower suspension electrodes are connected with one side of the lower micro bridge deck opposite to the middle micro bridge deck;
the length of the second lower suspended electrode is less than half the length of the first lower suspended electrode, and the length of the fourth middle suspended electrode is less than half the length of the second middle suspended electrode;
the first lower suspended electrode and the second lower suspended electrode are covered with electrode absorption layers, and the second middle suspended electrode and the fourth middle suspended electrode are covered with electrode absorption layers;
each of the second lower overhang electrodes is positioned between two of the first lower overhang electrodes, and each of the fourth middle overhang electrodes is positioned between two of the second middle overhang electrodes;
and each first lower overhang electrode is disposed adjacent to at least one of the second middle overhang electrodes, and each of the second middle overhang electrodes is disposed adjacent to at least one of the first lower overhang electrodes.
5. The infrared imaging chip of claim 4, wherein;
the upper micro bridge deck comprises an upper infrared absorption layer and an upper deformation layer; wherein the upper infrared absorbing layer is located above the upper deformation layer, the upper deformation layer is in contact with the electrode absorbing layer on the first upper suspended electrode, and the upper deformation layer is in contact with the electrode absorbing layer on the second upper suspended electrode; the expansion coefficient of the uppermost layer of the upper deformation layer is smaller than that of the lowermost layer of the upper deformation layer;
the middle micro bridge deck comprises a middle infrared absorption layer and a middle deformation layer; wherein the mid-infrared absorption layer is located above the mid-deformation layer, and the mid-deformation layer is in contact with the electrode absorption layer of the first mid-suspended electrode, the electrode absorption layer of the second mid-suspended electrode, the electrode absorption layer of the third mid-suspended electrode, and the electrode absorption layer of the fourth mid-suspended electrode; the expansion coefficient of the uppermost layer of the middle deformation layer is equal to the expansion coefficient of the lowermost layer of the middle deformation layer;
the lower micro bridge surface comprises a lower infrared absorption layer and a lower deformation layer; wherein the lower infrared absorbing layer is located below the lower deformation layer, the lower deformation layer is in contact with the electrode absorbing layer of the first lower suspended electrode, the lower deformation layer is in contact with the electrode absorbing layer of the second lower suspended electrode, and the lower flat electrode is located above the lower deformation layer; and the expansion coefficient of the uppermost layer of the lower deformation layer is greater than that of the lowermost layer of the lower deformation layer.
6. The infrared imaging chip of claim 5, wherein;
the projection of the second upper suspended electrode on the semiconductor substrate is coincident with the projection of the first middle suspended electrode on the semiconductor substrate; the projection of the first upper suspended electrode on the semiconductor substrate is coincident with the projection of the third middle suspended electrode on the semiconductor substrate;
a projection of the second lower suspended electrode on the semiconductor substrate coincides with a projection of the second middle suspended electrode on the semiconductor substrate; the projection of the first lower suspended electrode on the semiconductor substrate coincides with the projection of the fourth middle suspended electrode on the semiconductor substrate.
7. The infrared imaging chip of claim 4, wherein the microbridge structure comprises: a first and second overhanging reflective ring;
wherein the first suspended reflective ring is fixed on a side of the middle micro bridge deck opposite to the upper micro bridge deck, and the plurality of first middle suspended electrodes and the plurality of third middle suspended electrodes are located within the first suspended reflective ring; the second suspended reflective ring is fixed on one side of the middle micro bridge surface opposite to the lower micro bridge surface, and the plurality of second middle suspended electrodes and the plurality of fourth middle suspended electrodes are positioned in the second suspended reflective ring;
and a substrate reflecting layer is arranged in the semiconductor substrate and is positioned above the subsequent interconnection layer.
8. The infrared imaging chip of claim 3, wherein the electrical connection support posts comprise upper electrical connection support posts and lower electrical connection support posts;
wherein the upper electrical connection support column and the lower electrical connection support column are both located on the semiconductor substrate; one end of the middle micro-bridge structure is connected with the upper electric connection supporting column, and the other end of the middle micro-bridge structure is connected with the lower electric connection supporting column so as to fix the middle micro-bridge structure;
the infrared imaging chip further comprises: an upper serpentine beam structure and a lower serpentine beam structure;
one end of the upper micro-bridge structure is connected with the upper electric connection supporting column through the upper serpentine beam structure, so that the upper serpentine beam structure, the upper micro-bridge structure and the upper electric connection supporting column form a cantilever beam; one end of the lower micro-bridge structure is connected with the lower electric connection supporting column through the lower serpentine beam structure, so that the lower serpentine beam structure, the lower micro-bridge structure and the lower electric connection supporting column form a cantilever beam; or
One end of the upper micro-bridge structure is connected with the upper electric connection supporting column through the upper serpentine beam structure, so that the upper serpentine beam structure, the upper micro-bridge structure and the upper electric connection supporting column form a cantilever beam; one end of the lower micro-bridge structure is connected with the upper electric connection supporting column through the lower serpentine beam structure, so that the lower serpentine beam structure, the lower micro-bridge structure and the upper electric connection supporting column form a cantilever beam.
9. The infrared imaging chip of claim 5, wherein said upper microbridge surface further comprises a force-sensitive resistor; the area of the force sensitive resistor is the same as that of the upper deformation layer;
the resistance value of the force sensitive resistor is increased after the force sensitive resistor is stressed, and one end of the force sensitive resistor is connected with the input end of the processing circuit.
10. The infrared imaging chip according to claim 1 or 2, wherein a back-end interconnection layer is provided in the semiconductor substrate, and the first source electrode, the first drain electrode, and the first substrate end are connected by the back-end interconnection layer; and a plurality of metal layers are arranged in the upper electric connection support column, and the variable capacitor is connected with the subsequent interconnection layer through the plurality of metal layers so as to be connected with the fixed capacitor transistor.
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| KR20040071909A (en) * | 2003-02-07 | 2004-08-16 | 삼성전자주식회사 | Thin film transistor array panel |
| CN113551780A (en) * | 2021-09-18 | 2021-10-26 | 西安中科立德红外科技有限公司 | Infrared sensor chip based on semiconductor integrated circuit process and manufacturing method thereof |
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| WO2018014438A1 (en) * | 2016-07-18 | 2018-01-25 | 上海集成电路研发中心有限公司 | Infrared detector image element structure and fabrication method therefor |
| US10468448B2 (en) * | 2017-11-30 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor image sensor and method for forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20040071909A (en) * | 2003-02-07 | 2004-08-16 | 삼성전자주식회사 | Thin film transistor array panel |
| CN113551780A (en) * | 2021-09-18 | 2021-10-26 | 西安中科立德红外科技有限公司 | Infrared sensor chip based on semiconductor integrated circuit process and manufacturing method thereof |
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