CN114050159A

CN114050159A - Memory device and manufacturing method thereof

Info

Publication number: CN114050159A
Application number: CN202111342580.9A
Authority: CN
Inventors: 涂志康
Original assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Current assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-02-15

Abstract

The invention provides a memory device and a manufacturing method thereof.A thermal treatment process is adopted to convert the material of a semi-floating gate material layer with partial thickness above a contact window from polycrystalline silicon to monocrystalline silicon; the transformed region is defined as a convex-like body. The invention develops a new method, and the convex body is formed by adopting a heat treatment method, so that the problem that the semi-floating gate transistor fails because the etching selection ratio of the polycrystalline silicon layer to the substrate is very small and the etching process precision is difficult to control in the conventional process of forming the convex body by etching is avoided. The semi-floating gate material layer and the drain region are connected only through the convex-like body, and the area of a leakage current path is only the physical width of the convex-like body which can be accurately controlled; the built-in potential barrier in the convex-like body can prevent carriers between the semi-floating gate material layer and the drain region from diffusing in a non-working state. Therefore, the leakage of the stored charges in the semi-floating gate is greatly reduced, and the stability of the stored information is improved.

Description

Memory device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a memory device and a manufacturing method thereof.

Background

Semiconductor memories are used in various electronic fields. Among other things, nonvolatile memory can hold data for long periods of time in the event of a power outage. A semi-floating gate transistor is a mainstream nonvolatile memory. The semi-floating gate Transistor replaces the traditional silicon oxide erasing window by using the quantum Tunneling Effect of a Tunneling Field-Effect Transistor (TFET) and a pn junction diode, realizes the charging and discharging of the floating gate, can greatly reduce the working voltage of the Transistor, improves the working speed of the Transistor, realizes the faster data writing and erasing under low voltage, and is convenient to meet the requirement of low power consumption of a chip.

Fig. 1a and 1b are schematic cross-sectional views of a conventional semi-floating gate transistor. Referring to fig. 1a, a doped region N is formed in the upper portion of the substrate 11, a U-shaped trench is formed in the substrate 11, and the doped regions N on both sides of the U-shaped trench are respectively configured as a source region 12 and a drain region 13. An insulating layer 14 is formed on the surface of the U-shaped trench, a polysilicon layer 15 fills the U-shaped trench and covers the upper surface of the substrate 11, and a patterned photoresist 16 is formed on the upper surface of the polysilicon layer 15. Referring to fig. 1b, in the process of forming the semi-floating gate, the polysilicon layer 15 and the contact window of the substrate 11 are etched together, and the polysilicon layer 15 and the substrate 11 with a partial thickness are etched together to form a protrusion T. Specifically, the patterned photoresist 16 is used as a mask to etch the polysilicon layer 15 and the substrate 11 with a partial thickness, the remaining polysilicon layer is used as a semi-floating gate 15 ', and one side of the semi-floating gate 15' close to the drain region 13 is partially contacted with the substrate 11 which is not etched and forms a pn junction contact with the drain region 13. The portion of the substrate 11 not etched above the etch stop surface is referred to as a bump T (dashed frame portion).

A semi-floating gate transistor with a protrusion T is a preferred structure; however, in the process of etching the polysilicon layer 15 and the substrate 11 with a partial thickness to form the convex body T, since the etching selection ratio of the polysilicon layer 15 to the substrate 11 is very small, the process precision is difficult to control in practical application, and if the etching is insufficient, the polysilicon layer 15 remains on the substrate 11 at two sides uncovered by the patterned photoresist 16; excessive etching results in an etching stop surface (the upper surface of the substrate) lower than the lower surface of the doped region N, and both insufficient etching and excessive etching can cause the semi-floating gate transistor to fail.

Disclosure of Invention

The invention provides a memory device and a manufacturing method thereof.A convex body is formed by adopting a heat treatment method, so that the problem that a semi-floating gate transistor fails because the etching selection ratio of a polycrystalline silicon layer to a substrate is very small and the etching process precision is difficult to control in the conventional process of forming the convex body by etching is avoided.

The invention provides a manufacturing method of a memory device, which comprises the following steps:

providing a substrate which comprises a storage unit area, wherein a common source area, a first drain area and a second drain area are preset on one side of the upper surface of the storage unit area, and the first drain area and the second drain area are positioned on two sides of the common source area;

forming a gate insulating layer on the substrate of the memory cell region, wherein a first contact window and a second contact window exposing the substrate are formed in the gate insulating layer, the first contact window is located between the common source region and the first drain region, and the second contact window is located between the common source region and the second drain region;

forming a semi-floating gate material layer which covers the substrate exposed by the first contact window and the second contact window and also covers the gate insulating layer between the first contact window and the second contact window; the semi-floating gate material layer is made of polycrystalline silicon;

performing a heat treatment process to convert the material of the semi-floating gate material layer with partial thickness above the first contact window and the second contact window from the polycrystalline silicon into monocrystalline silicon; the transformed region is defined as a convex-like body.

Further, the temperature range of the heat treatment is 1000 ℃ to 1200 ℃.

Further, the substrate further comprises a peripheral area, and an active area is distributed in the peripheral area; the heat treatment process comprises a thermal oxidation process, and a gate oxide layer grows on the surface of the substrate of the active region of the peripheral region.

Further, after the performing of the thermal oxidation process, the method further includes:

doping nitrogen into the gate oxide layer by adopting a plasma nitridation process; and

and stabilizing the nitrogen doping and repairing plasma damage in the gate oxide layer by adopting a high-temperature annealing process.

Further, providing the substrate comprises: doping ions of a second doping type in the substrate to form a well region; doping ions of a first doping type in the well region to form a doped region, wherein the doped region extends from the inside of the well region to the upper surface of the substrate, and the common source region and the first and second drain regions are formed on the top of the doped region;

forming the layer of semi-floating gate material includes doping the layer of semi-floating gate material with ions of the second doping type.

Further, before forming the gate insulating layer, forming a first trench in the substrate between the common source region and the first drain region, and forming a second trench in the substrate between the common source region and the second drain region; the first contact window is located between the first drain region and the first trench, and the second contact window is located between the second drain region and the second trench.

Further, after the gate insulating layer and the floating gate material layer are formed, the gate insulating layer also covers inner surfaces of the first trench and the second trench, and the floating gate material layer covers the gate insulating layer and fills the first trench and the second trench.

Further, after the forming the semi-floating gate material layer and before the performing the heat treatment process, the method further includes:

and forming an inter-gate dielectric layer which at least covers the upper surface and the side surface of the floating gate material layer.

Further, after the heat treatment process is performed, the method further includes:

forming a control gate material layer, wherein the control gate material layer covers the inter-gate dielectric layer;

etching the control gate material layer, the inter-gate dielectric layer and the floating gate material layer of the common source region, and etching the control gate material layers of the first drain region and the second drain region; the rest control gate material layer, the rest inter-gate dielectric layer and the rest floating gate material layer form a first gate stack at the part between the first drain region and the common source region, and form a second gate stack at the part between the second drain region and the common source region; and the number of the first and second groups,

and forming side walls on the side walls of the first grid laminated layer and the second grid laminated layer, carrying out ion implantation, forming a common source electrode in the substrate corresponding to the common source region, forming a first drain electrode in the substrate corresponding to the first drain region, and forming a second drain electrode in the substrate corresponding to the second drain region.

The invention also provides another manufacturing method of the memory device, which is characterized by comprising the following steps:

providing a substrate, wherein the substrate comprises a memory cell area, and a source area and a drain area are preset on one side of the upper surface of the substrate of the memory cell area;

forming a gate insulating layer on the substrate of the memory cell region, wherein a contact window exposing the substrate is formed in the gate insulating layer, and the contact window is close to one side of the drain region;

forming a semi-floating gate material layer which covers the substrate exposed by the contact window and also covers the gate insulating layer between the contact window and the source region; the semi-floating gate material layer is made of polycrystalline silicon;

performing a heat treatment process to convert the material of the semi-floating gate material layer with partial thickness above the contact window from the polycrystalline silicon into monocrystalline silicon; the transformed region is defined as a convex-like body.

forming a control gate material layer, wherein the control gate material layer covers the inter-gate dielectric layer and the gate insulating layers positioned at two sides of the inter-gate dielectric layer;

etching the control gate material layer of the source region and the drain region; the rest control gate material layer, the inter-gate dielectric layer and the floating gate material layer form a gate stack; and the number of the first and second groups,

and forming a side wall on the side wall of the grid laminated layer, carrying out ion implantation, forming a source electrode in the substrate corresponding to the source region, and forming a drain electrode in the substrate corresponding to the drain region.

The present invention provides a memory device, characterized by comprising:

the substrate comprises a storage unit area, and a source area and a drain area are preset on one side of the upper surface of the substrate of the storage unit area;

a gate insulating layer is formed on the substrate of the memory cell region, a contact window which exposes the substrate is formed in the gate insulating layer, and the contact window is close to one side of the drain region;

a semi-floating gate material layer covering the substrate exposed by the contact window and also covering the gate insulating layer between the contact window and the source region; the semi-floating gate material layer is made of polycrystalline silicon;

and the convex-like body is positioned in the semi-floating gate material layer with partial thickness above the contact window, and the material of the convex-like body is monocrystalline silicon converted from the polycrystalline silicon.

Further, the memory device includes a semi-floating gate transistor; the semi-floating gate transistor includes: the source region, the drain region, the convex-like body positioned above the contact window, the semi-floating gate, the dielectric layer between the gates and the control gate.

Further, two adjacent semi-floating gate transistors share a source region.

Furthermore, the substrate also comprises a peripheral area, active areas are distributed in the peripheral area, and gate oxide layers grow on the surface of the substrate in the active areas.

Compared with the prior art, the invention has the following beneficial effects:

1. the memory device and the manufacturing method thereof provided by the invention adopt a heat treatment process to convert the material of the semi-floating gate material layer with partial thickness above the contact window from the polycrystalline silicon into the monocrystalline silicon; the transformed region is defined as a convex-like body. In the existing memory device, the convex body is a part of the substrate, and the semi-floating gate (polysilicon layer) and the convex body are overlapped together in different units. The invention adopts a heat treatment method to form the convex-like body on the self body of the semi-floating gate material layer, and the convex-like body is used as a part of the self body of the semi-floating gate material layer, namely, the semi-floating gate material layer and the convex-like body are in an integral structure, which is different from the structure that the semi-floating gate and the convex body of the existing memory device are stacked together in different units. The etching step of etching the polysilicon layer and the substrate with partial thickness together to form the convex body in the step (shown in figure 1a and figure 1b) is omitted, and the failure of the semi-floating gate transistor caused by the difficulty in controlling the etching process precision due to the small etching selection ratio of the polysilicon layer and the substrate is avoided.

The invention develops a new method, a heat treatment method is adopted to form a convex body, the semi-floating gate material layer and the drain region are only connected through the convex body, and the area of a leakage path is only the physical width of the convex body which can be accurately controlled; the built-in potential barrier in the convex-like body can prevent carriers between the semi-floating gate material layer and the drain region from diffusing in a non-working state. Therefore, the leakage of the stored charges in the semi-floating gate is greatly reduced, and the stability of the stored information is improved. The failure of the semi-floating gate transistor caused by the difficulty in controlling the precision of the etching process due to the small etching selection ratio of the polycrystalline silicon layer to the substrate is avoided.

2. The convex-like body positioned above the first contact window is used as a channel of the vertical tunneling field effect transistor to be connected with the semi-floating gate material layer and the drain region, so that the occupied area of the semiconductor substrate is small, and the improvement of the integration density of a chip is facilitated; in the process of manufacturing, the width of the convex-like body can be further reduced, the requirement of the device on the area of the semiconductor substrate is reduced, and an optimized space is provided for improving the integration density of the device chip.

Drawings

FIG. 1a is a schematic cross-sectional view of a conventional semi-floating gate transistor.

FIG. 1b is a schematic cross-sectional view of a conventional semi-floating gate transistor after forming a bump.

Fig. 2 is a flowchart of a method for manufacturing a memory device according to the present embodiment.

Fig. 3a is a schematic cross-sectional view of the memory device of the present embodiment after forming the first trench and the second trench.

Fig. 3b is a top view of the memory device of the present embodiment after the first trench and the second trench are formed.

Fig. 4 is a cross-sectional view of the memory device of the present embodiment after forming a second insulating layer.

FIG. 5 is a cross-sectional view of the method for fabricating a memory device according to the present embodiment after forming a bottom anti-reflective layer and a patterned photoresist.

Fig. 6 is a cross-sectional view of the memory device of the present embodiment after forming the first contact opening and the second contact opening.

Fig. 7 is a cross-sectional view of the floating gate material original layer formed by the method of manufacturing the memory device of the present embodiment.

Fig. 8 is a cross-sectional view of the method for fabricating a memory device according to the present embodiment after forming a layer of semi-floating gate material.

Fig. 9 is a cross-sectional view of the inter-gate dielectric layer after being formed in the method for manufacturing the memory device of the present embodiment.

Fig. 10 is a cross-sectional view of the memory device of the present embodiment after the stud bump is formed.

Fig. 11 is a cross-sectional view of the peripheral region without gate oxide layer formed in the method for manufacturing the memory device of the present embodiment.

Fig. 12 is a cross-sectional view of the periphery region after forming a gate oxide layer in the method for manufacturing the memory device of the present embodiment.

Fig. 13 is a cross-sectional view of the control gate material layer after being formed in the method of manufacturing the memory device of the present embodiment.

Fig. 14 is a cross-sectional view of the memory device of the present embodiment after forming the individual separated semi-floating gate transistors.

Fig. 15 is a cross-sectional view of a U-channel device formed by the method of fabricating the memory device of the present embodiment.

Fig. 16 is a cross-sectional view of a planar channel device formed by the method of manufacturing the memory device of the present embodiment.

FIG. 17 is a schematic diagram of another method of fabricating a memory device according to the present embodiment after forming an original layer of floating gate material;

fig. 18 is a schematic view after forming a floating gate material layer in another manufacturing method of the memory device of the present embodiment;

fig. 19 is a schematic view after forming a convex-like body in another manufacturing method of the memory device of the present embodiment;

fig. 20 is a cross-sectional view of a U-channel device formed by another method of fabricating a memory device of the present embodiment.

Fig. 21 is a cross-sectional view of another memory device of the present embodiment formed by a method of forming a planar channel device.

Description of reference numerals:

20-a semi-floating gate transistor; 200-a substrate; 200 a-a first contact window; 200 b-a second contact window; 201-common source; 203-a first drain; 204-a second drain; 205-doped region; 211 a-a first insulating layer; 211 b-a second insulating layer; 211-gate insulation layer; 213-bottom anti-reflection layer; 215-photoresist;

220-first floating gate; 221 a-original layer of floating gate material; 221 b-a layer of floating gate material; 230-an inter-gate dielectric layer; 231-a silicon oxide layer; 232-a silicon nitride layer; 235-gate oxide layer; 240-first control gate; 241-a control gate material layer; 30-a first trench; 40-a second trench; 300-a first gate stack; 400-a second gate stack; SP-side wall; i-common source region; II, a first drain region; III-a second drain region;

a V-source region; IV-a drain region; 200 c-contact window; 271-original layer of floating gate material; 260-an inter-gate dielectric layer; 261-a silicon oxide layer; 262-a silicon nitride layer; 263-source electrode; 264-drain electrode; 270-a layer of floating gate material; 281-a control gate material layer; 280-control gate.

Detailed Description

The method for fabricating the memory device of the present invention is further described in detail with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be understood that the drawings in the specification are in simplified form and are not to be taken in a precise scale, for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

It is noted that the terms "first," "second," and the like, hereinafter are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "at … …" can also include "at … …" and other orientational relationships.

The method for manufacturing the memory device of the embodiment, as shown in fig. 2, includes the following steps:

s1, providing a substrate which comprises a storage unit area, wherein a common source area, a first drain area and a second drain area are preset on one side of the upper surface of the storage unit area, and the first drain area and the second drain area are positioned on two sides of the common source area;

s2, forming a gate insulating layer on the substrate of the memory cell region, wherein a first contact window and a second contact window exposing the substrate are formed in the gate insulating layer, the first contact window is located between the common source region and the first drain region, and the second contact window is located between the common source region and the second drain region;

s3, forming a semi-floating gate material layer, wherein the semi-floating gate material layer covers the substrate exposed by the first contact window and the second contact window and also covers the gate insulating layer between the first contact window and the second contact window; the semi-floating gate material layer is made of polycrystalline silicon;

s4, performing a heat treatment process to convert the material of the semi-floating gate material layer with partial thickness above the first contact window and the second contact window from the polycrystalline silicon to monocrystalline silicon; the transformed region is defined as a convex-like body.

The memory device and the method for fabricating the same according to the present embodiment are described in detail below with reference to fig. 3a to 16.

Fig. 15 is a schematic cross-sectional view of a memory device having a U-shaped channel manufactured by the manufacturing method of the present embodiment. Fig. 16 is a schematic cross-sectional view of a memory device having a planar channel manufactured by the manufacturing method of the present embodiment. Referring to fig. 15 and 16, the memory device may include at least one semi-floating gate transistor, and the memory device may further include other types of memory elements, logic elements, and the like. In one embodiment, the storage device comprises two adjacent semi-floating gate transistors, the two adjacent semi-floating gate transistors have different drain regions and share the same source region, and the arrangement helps to reduce the occupied area of all the semi-floating gate transistors on the substrate and improve the integration density of the storage device. In this embodiment, two adjacent semi-floating gate transistors have symmetrical structures.

The present embodiment is specifically described by taking as an example the fabrication of a memory device including two semi-floating gate transistors sharing a source region. The two semi-floating gate transistors sharing the source region are respectively called a first semi-floating gate transistor and a second semi-floating gate transistor, and the first semi-floating gate transistor and the second semi-floating gate transistor are formed through the same process.

As shown in fig. 3a and 3b, a substrate 200 is provided, and a common source region i, a first drain region ii and a second drain region iii are preset on one side of the substrate close to the upper surface of the substrate and located on two sides of the common source region. The position of a common source region for forming a first semi-floating gate transistor and a second semi-floating gate transistor is called a common source region I, a first drain region II is used for forming a drain region of the first semi-floating gate transistor, a second drain region III is used for forming a drain region of the second semi-floating gate transistor, a semi-floating gate in the subsequently formed first semi-floating gate transistor is called a first semi-floating gate, and a semi-floating gate in the subsequently formed second semi-floating gate transistor is called a second semi-floating gate. The substrate 200 is, for example, monocrystalline silicon, polycrystalline silicon, or silicon-on-insulator. The substrate 200 may be entirely of the second doping type or formed with a well region of the second doping type. Optionally, the substrate 200 has a well region (e.g., P-well) with a second doping type, the well region further has a doped region 205 formed therein with the first doping type and extending from the inside to the upper surface of the substrate 200, and the source region and the drain region of the semi-floating gate transistor are formed on top of the doped region 205. A first insulating layer 211a is formed on the upper surface of the substrate 200.

The memory device of this embodiment is possible with both trenches corresponding to a U-channel memory device and without trenches corresponding to a planar channel memory device. Figure 3a shows the case of a trench. A first trench 30 is formed in the substrate between the common source region i and the first drain region ii and a second trench 40 is formed in the substrate between the common source region i and the second drain region iii. The first trench 30 and the second trench 40 may be formed by depositing a hard mask on the surface of the substrate 200 and by photolithography and etching processes. The insulating layer 211a and a portion of the thickness of the substrate 200 are etched to form the first trench 30 and the second trench 40. The first trench 30 and the second trench 40 have a depth of about

In this embodiment, the depth of the first trench 30 and the depth of the second trench 40 are both greater than the depth of the doped region 205, that is, the bottom surface of the first trench 30 and the bottom surface of the second trench 40 are farther away from the upper surface f1 of the substrate than the bottom of the doped region 205 with reference to the upper surface f1 of the substrate 200.

With continued reference to fig. 3a and 3b, a first direction (e.g., X-direction) and a second direction (e.g., Y-direction) are defined perpendicular to each other in a plane parallel to the substrate 200, and a direction perpendicular to the plane of the substrate 200 is defined as a Z-direction (device thickness direction). The substrate 200 may have an isolation structure (e.g., shallow trench isolation, STI) and an active area AA formed thereon. The shallow trench isolation STI and the active area AA may be alternately arranged in a first direction (e.g., X direction). The first drain region ii, the first trench 30, the common source region i, the second trench 40, and the second drain region iii are sequentially distributed along a second direction (e.g., Y direction). In addition, it can be considered that the steps of well implantation, other ion implantation, annealing, etc. are completed in the substrate, and a well region (for example, a P-well in the present embodiment) of the second doping type and a doped region 205 extending from the inside of the well region to the upper surface of the substrate 200 are formed in the substrate 200.

As shown in fig. 4 and 5, a second insulating layer 211b is formed to cover at least the first trench 30 and the second trench 40. The first insulating layer 211a can be removed before the second insulating layer 211b is deposited. Illustratively, the second insulating layer 211b may also cover the first insulating layer 211a on the upper surface of the substrate. The first insulating layer 211a and/or the second insulating layer 211b on the upper surface of the substrate serve as the gate insulating layer 211. The gate insulating layer 211 is used for isolating the substrate 200 from the floating gate material layer 221 formed subsequently, and the gate insulating layer 211 covering the upper surface of the substrate can also play an etching blocking role when the floating gate material layer 221 is patterned. The material of the gate insulating layer 211 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be fabricated by thermal oxidation, Chemical Vapor Deposition (CVD), atomic layer deposition, or the like.

And etching the gate insulating layer to form a first contact window and a second contact window. As shown in fig. 5, a bottom anti-reflective layer (BARC)213 and a patterned photoresist 215 are formed. A bottom anti-reflective layer (BARC)213 fills the first and

second trenches

30 and 40 and forms a thickness over the substrate covering the gate insulating layer 211. The patterned photoresist 215 is located on the top surface of the bottom anti-reflective layer (BARC) 213. The patterned photoresist 215 has openings corresponding to the first contact opening and the second contact opening.

As shown in fig. 5 and 6, the bottom anti-reflection layer 213 and the lower gate insulating layer 211 are sequentially dry-etched using the patterned photoresist 215 as a mask to expose the substrate 200, thereby forming a first contact window 200a and a second contact window 200 b. Dry etching, the process is controllable, and the first contact window 200a and the second contact window 200b can be precisely formed. Specifically, the first contact window 200a is located between the first drain region ii and the first trench 30, and the second contact window 200b is located between the second drain region iii and the second trench 40. Finally, the patterned photoresist 215 and the bottom anti-reflection layer (BARC)213 are removed. The photolithography and etching process can prevent the mask material composed of the bottom anti-reflection layer (BARC)213 and the photoresist 215 from collapsing while ensuring protection of the pattern that needs to be preserved.

As shown in fig. 7, a floating gate material original layer 221a is formed on the substrate 200 (original state), and the floating gate material original layer 221a covers the gate insulating layer 211 and the upper surface of the substrate 200 exposed by the first contact window 200a and the second contact window 200 b. The floating gate material original layer 221a of the present embodiment fills the first trench 30 and the second trench 40, for example. In some embodiments, the first trench and the second trench are not formed on the substrate, and the original layer 221a of floating gate material is located above the substrate. The original layer 221a of floating gate material is used to form the semi-floating gates of the first and second semi-floating gate transistors. The floating gate material original layer 221a has a second doping type. In this embodiment, the material of the floating gate material original layer 221a is, for example, p-type doped polysilicon, wherein the p-type dopant can be introduced by a doping gas during a deposition process or by ion implantation after the polysilicon is deposited. Illustratively, polysilicon may be deposited to a thickness by a CVD process, followed by p-type ion implantation and annealing followed by Chemical Mechanical Polishing (CMP) to planarize the upper surface of the polysilicon to a desired thickness, e.g., about the thickness of the original layer 221a of floating gate material above the upper surface of the substrate 200

As shown in fig. 8, the original layer 221a of floating gate material is etched to remove the region of the original layer 221a of floating gate material between the first contact window 200a and the first drain region ii and the region of the original layer 200a of floating gate material between the second contact window 200b and the second drain region iii. The remaining original layer of gate material is referred to as a semi-floating gate material layer 221b (intermediate state), the semi-floating gate material layer 221b covers the substrate 200 exposed by the first contact window 200a and the second contact window 200b, and also covers the gate insulating layer 211 located between the first contact window 200a and the second contact window 200 b; the material of the semi-floating gate material layer 221b is polysilicon. The boundary of the semi-floating gate material layer 221b close to the first drain region II falls within the range of the first contact window 200a, and the boundary of the semi-floating gate material layer 221 close to the second drain region III falls within the range of the second contact window 200 b. Preferably, the sides of the semi-floating gate material layer 221b and the second contact window 200b close to the second drain region iii tend to be close to or aligned with each other, and the sides of the semi-floating gate material layer 221 and the first contact window 200a close to the first drain region ii tend to be close to or aligned with each other. The floating gate material original layer 221a may be etched by dry or wet etching to form the semi-floating gate material layer 221 b.

It should be understood that if the gate insulating layer 211 between the contact window and the drain region is not preserved when forming the contact window, there will be no etching stop layer when etching the original layer 221a of floating gate material, and the etching selectivity between the original layer 221a of floating gate material (for example, made of polysilicon) and the substrate 200 (for example, made of silicon) is low, which may cause serious substrate damage, and thus affect the performance of the semi-floating gate transistor. In this embodiment, when the original layer 221a of the floating gate material is etched, the gate insulating layer 211 located between the first drain region ii and the first contact window 200a and between the second drain region iii and the second contact window 200b may be used as an etching blocking layer, so as to prevent the surface of the substrate 200 from being damaged in the etching process. Preferably, the floating gate material original layer 221a may be etched using a dry etching mode of "End point detection (End PT) + Over etching (Over Etch)" to ensure that the semi-floating gate material within the removal range is removed completely.

As shown in fig. 9, an intergate dielectric layer 230 is formed, and the intergate dielectric layer 230 covers at least the upper surface and the side surfaces of the semi-floating gate material layer 221 b. Optionally, the upper surface of the gate insulating layer 211 between the first contact window 200a and the first drain region ii may be further covered, and the upper surface of the gate insulating layer 211 between the second contact window 200b and the second drain region iii may be further covered. The material of the intergate dielectric layer 230 may be silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials, and the intergate dielectric layer 230 may have a single-layer structure or a multi-layer structure (e.g., an ONO structure) with more than two layers. Illustratively, the intergate dielectric layer 230 includes a silicon oxide layer 231 and a silicon nitride layer 232 stacked (i.e., ON structure).

As shown in fig. 9 and 10, a heat treatment process is performed to convert the material of the partial thickness of the semi-floating gate material layer 221b located above the first contact window 200a and the second contact window 200b from polysilicon to single crystal silicon; the transformed region is defined as the convex-like body T2. Under the action of the high temperature of the thermal treatment, ions (for example, N type) of the first doping type in the doped region 205 in the substrate 200 diffuse into the polysilicon of the semi-floating gate material layer 221b, and ions (for example, P type) of the second doping type in the polysilicon of the semi-floating gate material layer 221b diffuse to form a PN junction. The temperature range of the heat treatment is 1000-1200 ℃.

The thermal treatment process may include a thermal oxidation process such as a thermal oxidation process used in a gate oxide formation process of the peripheral region. The heat treatment process is not limited to the thermal oxidation process, or may include a high temperature anneal or other high temperature treatment process. The thermal oxidation process during the formation of the gate oxide layer of the peripheral region is used in detail below to convert the material of the partial thickness of the semi-floating gate material layer 221b located above the first contact window 200a and the second contact window 200b from polysilicon to single crystal silicon.

Referring to fig. 3b, fig. 10 and fig. 11, the memory device of the present embodiment includes a memory cell region c (cell) and a peripheral region p (peripheral). The memory cell region c (cell) has shallow trench isolations STI and active regions AA alternately distributed along a first direction (e.g., X direction). The peripheral region P is also alternately distributed with shallow trench isolation STI and active regions AA along the first direction (e.g., X direction). The peripheral region P includes, for example, various circuits that provide voltage sources, current sources, and read and write operations.

In the process of forming the inter-gate dielectric layer 230 in the memory cell region C, the inter-gate dielectric layer 230 also covers the peripheral region P. In the memory cell region C, the intergate dielectric layer 230 covers at least the upper surface and the side surface of the semi-floating gate material layer 221b, and the intergate dielectric layer 230 includes a silicon oxide layer 231 and a silicon nitride layer 232 (i.e., an ON structure) which are stacked. As shown in fig. 11, during the etching process to remove the inter-gate dielectric layer (not shown) in the peripheral region P, a small thickness of the top of the STI is also consumed in the peripheral region P. In the peripheral region P, the substrate surface of the active region AA between adjacent shallow trench isolation STI is exposed.

As shown in fig. 12, the gate oxide layer 235 is formed on the substrate surface of the active area AA of the peripheral area P by thermal oxidation, and in particular, the gate oxide layer 235 may be formed on the substrate surface of the active area AA of the Low Voltage (LV) area and/or the High Voltage (HV) area of the peripheral area P.

Specifically, the gate oxide layer 235 is formed using a thermal oxidation process, which may use an In-Situ Steam oxidation (ISSG) method or a Rapid Thermal Oxidation (RTO) method. An In-Situ Steam oxidation (ISSG) process may be used to grow a gate oxide layer, such as silicon oxide, on the substrate surface In the active area AA. The in situ steam oxidation (ISSG) step comprises N₂O in-situ steam oxidation step with N as reaction gas₂O and H₂Or O₂In-situ steam oxidation step with O as the reaction gas₂And H₂(ii) a The temperature range of the in-situ steam oxidation method is 1000-1200 ℃. The reaction temperature of the Rapid Thermal Oxidation (RTO) ranges, for example, from 1000 c to 1200 c, and oxygen and hydrogen are introduced to form the gate oxide layer 235. The gate oxide layer 235 is grown by a Rapid Thermal Oxidation (RTO) process, which reduces the growth time and the required thermal budget.

Preferably, after the thermal oxidation process is performed, nitrogen can be doped into the gate oxide layer by using a plasma nitridation process, so that part of oxygen atoms in the gate oxide layer are replaced by nitrogen atoms to form Si-N bonds, and thus the gate oxide layer is adjusted to be a gate oxide layer with a certain nitrogen concentration, such as silicon oxynitride, and thus the dielectric constant of the gate oxide layer can be improved.

Plasma Nitridation processes include Decoupled Plasma Nitridation (DPN), Remote Plasma Nitridation (RPN), or N of a vertical diffusion device₂Any one of the nitriding treatments of (1). N is a radical of₂Under high temperature, N ions are dissociated, thereby nitridizing the oxide layer. Decoupling process conditions of plasma nitrogen treatment process such asComprises the following steps: the plasma processing power is 300W-600W; the plasma processing pressure is 10 mTorr-30 mTorr, and the plasma processing gas is N₂And He, wherein N₂The flow rate is 50sccm to 120sccm, and the He flow rate is 80sccm to 150 sccm.

A high temperature annealing Process (PNA) is used to stabilize the N-doping and repair the plasma damage in the dielectric to form the gate oxide layer 235 with an improved gate oxide film interface state. Si-H bonds and S-O-H bonds generated in the process of growing the gate oxide layer by an ISSG thermal oxidation method and broken bonds generated near an Si-SiO interface are repaired mainly through a high-temperature annealing process of PNA. The temperature range of the high temperature annealing process is, for example, 1000 ℃ to 1100 ℃, and the reaction time range is 5sec to 120 sec.

In the process of forming the gate oxide layer 235 in this embodiment, a real-time high-temperature nitridation process is introduced after a SiO gate oxide layer is formed by thermal oxidation to reduce the number of Si-H bonds and S-O-H bonds generated at the Si-SiO interface, promote the stress release of the internal structure of the oxide film to reduce the possibility of broken bonds near the interface, and simultaneously, introduce a proper amount of oxidizing gas to eliminate the damage defect caused by pure nitridation to the gate dielectric layer, effectively reduce the total interface state charge of the gate oxide film by one order of magnitude or more, and effectively eliminate the gate oxide damage defect.

Under the action of high temperature of thermal oxidation in the process of forming the gate oxide layer of the peripheral region P, the memory cell region C is also in the high temperature atmosphere of thermal oxidation, heat is transferred from the contact window, which is where the polysilicon contacts the monocrystalline silicon, the polycrystal is recrystallized at high temperature along the crystal direction of the monocrystalline silicon, and the polycrystal is transformed into monocrystalline at high temperature, and the recrystallization is extended upward by a certain thickness under the action of continuous high temperature of thermal oxidation, so that the polysilicon of the semi-floating gate material layer 221b with partial thickness above the first contact window 200a and the second contact window 200b is melted into a molten state, and the polycrystalline silicon is transformed into small crystal grains and recrystallized in the molten state, and the small crystal grains (crystal nuclei) grow into crystal grains with the same crystal face orientation to form monocrystalline silicon.

In this embodiment, there is no specific requirement for the region where the polycrystal is converted into the single crystal, as long as the single crystal silicon is ensured at the contact window, and it is not necessary that the shape of the convex T1 formed by etching the substrate is regular. The transformed region is defined as a convex-like body T2, i.e., the material of the convex-like body T2 region is transformed from polysilicon to monocrystalline silicon, and PN junction is formed in the convex-like body T2 region.

The thermal oxidation process in the embodiment comprises the steps of growing a gate oxide layer on the surface of the substrate of the active area of the peripheral area, and converting the material of the semi-floating gate material layer with partial thickness above the contact window into monocrystalline silicon from polycrystalline silicon by utilizing the thermal oxidation of the gate oxide layer grown in the peripheral area; and an additional thermal oxidation step is not added, so that the two purposes are achieved, and the process cost is saved.

As shown in fig. 13, a control gate material layer 241 is formed, the control gate material layer 241 covering the inter-gate dielectric layer 230. The control gate material layer 241 is used to form the control gates of the first and second semi-floating gate transistors. Polysilicon with a certain thickness can be deposited by CVD and other methods, and the polysilicon is planarized to reach the required thickness, so as to obtain the control gate material layer 241. The control gate material layer 241 may be polysilicon of a first doping type, and in this embodiment, the control gate material layer 241 is doped n-type, for example.

As shown in fig. 13 and 14, the control gate material layer 241, the intergate dielectric layer 230 and the semi-floating gate material layer 221b are etched to form the independent and separate semi-floating gate transistors.

Specifically, the control gate material layer 241, the inter-gate dielectric layer 230 and the semi-floating gate material layer 221b of the common source region i are etched, and the control gate material layers 241 of the first drain region ii and the second drain region iii are etched; the remaining control gate material layer 241, the inter-gate dielectric layer 230 and the semi-floating gate material layer 221b form a first gate stack 300 in a portion between the first drain region ii and the common source region i, and form a second gate stack 400 in a portion between the second drain region iii and the common source region i.

The first gate stack 300 is located between the first drain region ii and the common source region i for forming a first semi-floating gate transistor. The first gate stack 300 includes a first floating gate 220 obtained by etching the semi-floating gate material layer 221b, a first control gate 240 obtained by etching the control gate material layer 241, and a first inter-gate dielectric layer obtained by etching the inter-gate dielectric layer 230. The second gate stack 400 is located between the second drain region iii and the common source region i, and is used for forming a second semi-floating gate transistor, and the second gate stack 400 includes a second semi-floating gate obtained by etching the semi-floating gate material layer 221b, a second control gate obtained by etching the control gate material layer 241, and a second inter-gate dielectric layer obtained by etching the inter-gate dielectric layer 230. Photolithography and an anisotropic dry etching process may be used to form the first gate stack 300 and the second gate stack 400. In the dry etching process, in order to avoid damage to the substrate 200 of the first drain region ii and the second drain region iii, the gate insulating layer 211 in the region may not be completely removed by adjusting the etching conditions. The gate insulating layer 211 of the common source region i is exposed.

As shown in fig. 15, a sidewall SP of the semi-floating gate is formed; specifically, side walls SP are formed on the sidewalls of the first gate stack 300 and the second gate stack 400, and ion implantation and annealing are performed to form a common source 201 in the substrate 200 corresponding to the common source region i, a first drain 203 in the substrate 200 corresponding to the first drain region ii, and a second drain 204 in the substrate 200 corresponding to the second drain region iii.

Specifically, a dielectric material may be conformally deposited, and then anisotropic dry etching is performed to remove the dielectric material covering the upper surfaces of the first control gate and the second control gate and the upper surface of the semiconductor, and the dielectric material covering the side surfaces of the first gate stack 300 and the second gate stack 400 is retained as a sidewall. The side wall covering one side of the drain region of the first gate stack 300 covers the side surface of the first control gate, and the side wall covering one side of the common source region of the first gate stack 300 covers the side surfaces of the first control gate, the first inter-gate dielectric layer and the first half floating gate, that is, in the first half floating gate transistor, the side surface of the first half floating gate facing the source region is covered by the side wall to be isolated from the outside at one side facing the source region, and in the second half floating gate transistor, the second half floating gate is the same. In this embodiment, when performing ion implantation and annealing to form the common source, the first drain, and the second drain, the ion implantation is, for example, n-type implantation.

Through the above steps, the first and second half floating gate transistors are formed on the substrate 200.

Fig. 16 is a schematic cross-sectional view showing a memory device without trenches manufactured by the manufacturing method of the present embodiment. Fig. 16 is different from fig. 15 in that the first floating gate half 220 is formed only on the upper surface of the substrate 220 and is not formed in the trench; the corresponding gate insulating layer 211 is formed only on the upper surface of the substrate 220 and does not cover the surface of the trench.

The steps of another method for fabricating a memory device are described in detail below with reference to fig. 17-21. The present embodiment is specifically described by taking the fabrication of a single semi-floating gate transistor memory device as an example.

A method of fabricating a memory device, comprising:

Specifically, as shown in fig. 17, a substrate 200 is provided, and an active region V and a drain region IV are formed on the upper surface side. The memory device of this embodiment is possible with both trenches corresponding to a U-channel memory device and without trenches corresponding to a planar channel memory device. Figure 17 illustrates a trenched U-channel memory device. A gate insulating layer 211 is formed on the substrate 200, and a contact window 200c exposing the substrate 200 is formed in the gate insulating layer 211, and the contact window 200c is close to one side of the drain region IV.

A floating gate material original layer 271 covering the substrate 200 and the gate insulating layer 211 is formed between the source region V and the drain region IV.

As shown in fig. 18, etching the original layer 271 of floating gate material to remove a portion of the original layer 271 of floating gate material on one side of the source region V and a region between the contact window 200c and the drain region IV; the remaining original layer of floating gate material after etching is used as the semi-floating gate material layer 270 of the semi-floating gate transistor, which is also the final semi-floating gate. A semi-floating gate material layer 270 covers the substrate 200 exposed by the contact window 200c and also covers the gate insulating layer 211 located between the contact window 200c and the source region V; the material of the semi-floating gate material layer 270 is polysilicon.

As shown in fig. 19, a thermal treatment process is performed to convert the material of the partial-thickness semi-floating gate material layer 270 above the contact window from polysilicon to single crystal silicon; the transformed region is defined as the convex-like body T3. The heat treatment forming process of the convex-like body T3 is the same as that of the convex-like body T2, and the appearance is the same, which is not described again.

An intergate dielectric layer 260 and a control gate material layer 281 are formed, the intergate dielectric layer 260 covers the upper surface of the semi-floating gate material layer 270 and the side surface facing the drain region, and the control gate material layer 281 covers the intergate dielectric layer 260. The control gate material layer 281 is used for the control gate of the semi-floating gate transistor. The intergate dielectric layer 260 may have a single-layer structure or a multi-layer structure (e.g., an ONO structure) having two or more layers. Illustratively, the intergate dielectric layer 260 includes a silicon oxide layer 261 and a silicon nitride layer 262 (i.e., an ON structure) stacked together.

As shown in fig. 19 and 20, the control gate material layer 281 and the intergate dielectric layer 260 are etched. Etching the control gate material layer 281 of the source region V and the drain region IV, and also etching and removing the inter-gate dielectric layer 260 on the side wall of the semi-floating gate material layer 270 close to one side of the source region V; the remaining control gate material layer 281 serves as the control gate 280 for the semi-floating gate transistor. In the dry etching process, in order to avoid damage to the substrate 200 of the source region V and the drain region IV, the gate insulating layer 211 in the region may not be completely removed by adjusting the etching conditions, that is, after the etching is completed, the gate insulating layer 211 with a certain thickness may remain on the substrate 200 of the source region V and the drain region IV.

Forming a semi-floating gate side wall SP; specifically, the semi-floating gate, the inter-gate dielectric layer 260 and the control gate 280 form a gate stack, a sidewall SP is formed on a sidewall of the gate stack, and ion implantation and annealing are performed to form a source 263 in the substrate 200 corresponding to the source region V and a drain 264 in the substrate 200 corresponding to the drain region IV.

Fig. 21 is a schematic cross-sectional view showing a memory device without trenches fabricated by the fabrication method of the present embodiment. Fig. 21 differs from fig. 20 in that the semi-floating gate 270 is formed only on the upper surface of the substrate 220 and is not formed in the trench; the corresponding gate insulating layer 211 is formed only on the upper surface of the substrate 220 and does not cover the surface of the trench.

The invention also provides a memory device manufactured by the manufacturing method, as shown in fig. 15-16 and 20-21, the memory device comprises:

Specifically, the memory device comprises a semi-floating gate transistor; the semi-floating gate transistor includes: the drain region, the source region, the convex-like body positioned above the contact window, the semi-floating gate, the inter-gate dielectric layer and the control gate.

The substrate includes:

a well region doped with ions of a second doping type; and

a doped region extending from inside the well region to an upper surface of the substrate, the doped region being doped with ions of a first doping type; the source region and the drain region are both formed on top of the doped region.

The substrate further comprises a peripheral area, active areas are distributed in the peripheral area, and gate oxide layers grow on the surface of the substrate in the active areas.

A memory of the present embodiment (as shown in fig. 15 and 16) includes two adjacent semi-floating gate transistors having different drain regions and sharing the same source region; the two adjacent semi-floating gate transistors in the common source region are used as first repeating units, and a wafer for manufacturing the memory comprises a plurality of first repeating units in a duplicate arrangement. The arrangement is beneficial to reducing the occupied area of all the semi-floating gate transistors on the substrate and improving the integration density of the memory device. In this embodiment, two adjacent semi-floating gate transistors have symmetrical structures.

Another memory (as shown in fig. 20 and 21) of this embodiment uses a single semi-floating gate transistor as a second repeating unit, and a wafer on which the memory is fabricated includes a plurality of second repeating units in a duplicate arrangement.

A memory of the present embodiment will be described in detail below with reference to fig. 10 to 16.

As shown in fig. 10 and 11, a memory of the present embodiment includes:

the substrate 200 comprises a memory cell region C, wherein a common source region I, a first drain region II and a second drain region III are preset on one side of the upper surface of the memory cell region C, and are positioned on two sides of the common source region I;

a gate insulating layer 211 is formed on the substrate of the memory cell region C, a first contact window and a second contact window are formed in the gate insulating layer 211, the first contact window and the second contact window exposing the substrate 200, the first contact window is located between the common source region i and the first drain region ii, and the second contact window is located between the common source region i and the second drain region iii;

a semi-floating gate material layer 211b, the semi-floating gate material layer 211b covering the substrate 200 exposed by the first contact window and the second contact window, and further covering the gate insulating layer 211 located between the first contact window and the second contact window; the material of the semi-floating gate material layer 211b is polysilicon;

a bump T2, the bump T2 being located in a partial thickness of the layer 221b of semi-floating gate material above the first contact window and the second contact window, the bump T2 being formed of single crystal silicon converted from the polysilicon.

Specifically, the substrate includes: a well region doped with ions of a second doping type; and a doped region 205, the doped region 205 extending from the inside of the well region to the upper surface of the substrate 200, the doped region 205 being doped with ions of the first doping type; the common source region I and the first and second drain regions II and III are formed on top of the doped region 205.

The memory device further comprises a first trench 30 and a second trench 40, the first trench 30 being located in the substrate between the common source region I and the first drain region II; the second trench 40 is located in the substrate between the common source region I and the second drain region III; the first contact window is located between the first drain region II and the first trench 30, and the second contact window is located between the second drain region III and the second trench 40. The gate insulating layer 211 also covers the inner surfaces of the first trench 30 and the second trench 40, and the floating gate material layer 211b covers the gate insulating layer 211 and fills the first trench 30 and the second trench 40.

As shown in fig. 12, the substrate further includes a peripheral region P, an active region AA is distributed in the peripheral region P, and a gate oxide layer 235 is grown on the surface of the substrate in the active region AA.

As shown in fig. 14 and 15, the memory device includes a first half floating gate transistor and a second half floating gate transistor which are adjacent; the first half floating gate transistor includes: the first drain region II, the bump-like body T2 located above the first contact window, the first floating gate half 220, the first inter-gate dielectric layer 230, and the first control gate 240. The second semi-floating gate transistor is structurally symmetrical to the first semi-floating gate transistor. The second semi-floating gate transistor includes: the second drain region, the convex-like body located above the second contact window, the second semi-floating gate, the second inter-gate dielectric layer and the second control gate. As shown in fig. 13, the semi-floating gate material layer 221b is removed from a portion above the common source region I, and the remaining portions at two sides of the common source region I are the first semi-floating gate 220 and the second semi-floating gate respectively.

In the semi-floating gate transistor 20 according to the embodiment of the present invention, the first semi-floating gate 220 is used as a charge storage layer, and the ions of the first doping type in the doped region 205 in the region of the convex-like body T2 are diffused into the first semi-floating gate 220 from the first contact window to form a PN junction. In the first half-floating gate transistor, the first half-floating gate 220, the convex-like body T2 located above the first contact window, the first drain region II, the first inter-gate dielectric layer 230, and the first control gate 240 form a vertical tunneling field effect transistor using a control gate as a gate, the convex-like body T2 located above the first contact window is used as a channel of the vertical tunneling field effect transistor to connect the first half-floating gate 220 and the first drain region II, and the first control gate 240 regulates on and off of current in the vertical tunneling field effect transistor through an electric field. The second semi-floating gate transistor has the same working principle as the first semi-floating gate transistor.

Referring to fig. 15, the memory device includes a semi-floating gate transistor 20, the semi-floating gate transistor 20 includes a substrate 200, a common source 201 and a first drain 203 of a first doping type are formed on a top of the substrate 200, and a surface of the substrate 200 between the common source 201 and the first drain 203 is provided with a first contact window of the semi-floating gate. The semi-floating gate transistor 20 further includes a bump-like body T2 formed on the substrate 200 between the common source 201 and the first drain 203, a first semi-floating gate 220, an intergate dielectric layer 230, and a control gate 240. The first half floating gate 220 has a second doping type opposite to the first doping type; the convex-like body T2 is located in the first floating gate half 220 with a partial thickness above the first contact window, and the intergate dielectric layer 230 covers the upper surface of the first floating gate half 220 and the side surface of the floating gate 220 near the first drain 203 side. A control gate 240 is located on the intergate dielectric layer 230.

The semi-floating gate transistor can be an n-type device or a p-type device according to different migration charge types. In this embodiment, for example, the semi-floating gate transistor is an n-type device, the first doping type is an n-type, and the second doping type is a p-type. It will be appreciated that interchanging the doping conductivity types of the device between n-type and p-type will result in a p-type device. The n-type dopant is, for example, phosphorus or arsenic, and the p-type dopant is, for example, boron or indium.

In the semi-floating gate transistor (SFGT) of the embodiment of the invention, TFET is used as a channel for injecting or releasing charges for connecting the first semi-floating gate and the drain region in the semi-floating gate device. The SFGT controls the switching state of the TFET by a control gate 240 that overlies the sidewalls of the asperities T2 (the sidewalls that face the drain region). Taking an N-type SFGT as an example, a source region and a drain region of the SFGT are both doped in an N-type manner, polysilicon of the semi-floating gate is doped in a p-type manner, and a convex-like body T2 between the source region and the drain region serves as a channel of the TFET. When the control gate applies negative bias and the drain region applies positive bias, the convex-like body T2 and the surface of the gate dielectric layer enter an accumulation state, a large number of holes are gathered on the surface to form a PN junction conforming to band-to-band tunneling with high-concentration electrons of the drain region, therefore, the vertical TFET is started, the electrons tunnel from the convex-like body T2 to the drain region, the positive charge quantity in the semi-floating gate is increased, and logic '1' is written; when the control gate is forward biased and the drain region is reverse biased, the diode formed by the convex body T2 and the drain region enters a forward biased state, the carriers in the semi-floating gate are released through the convex body T2, and the amount of stored charges is reduced, namely, logic '0' is written.

The floating gate is charged or discharged through the vertical tunneling field effect transistor, and the semiconductor integrated circuit has the advantages of higher chip integration density, stronger data retention capability and higher data reading speed.

Another memory of the present embodiment is described in detail below with reference to fig. 20 and 21.

As shown in fig. 20 and 21, another memory includes:

the substrate 200 comprises a memory cell region, wherein an active region V and a drain region IV are preset on one side of the upper surface of the substrate of the memory cell region;

a gate insulating layer 211 is formed on the substrate of the memory cell region, a contact window 200c exposing the substrate is formed in the gate insulating layer 211, and the contact window 200c is close to one side of the drain region IV;

a semi-floating gate material layer 270, wherein the semi-floating gate material layer 270 covers the substrate 200 exposed by the contact window 200c and also covers the gate insulating layer 211 between the contact window 200c and the source region V; the material of the semi-floating gate material layer 270 is polysilicon;

a convex-like body T3, the convex-like body T3 being located right above the contact window 200c

In the upper partial thickness of the semi-floating gate material layer 270, the material of the convex-like body T3 is single crystal silicon converted from polysilicon.

The memory device includes a semi-floating gate transistor; the semi-floating gate transistor includes: the drain region, the convex-like body T3 positioned above the contact window, the semi-floating gate, the inter-gate dielectric layer 260 and the control gate 280.

The memory device obtained by dicing (dividing) from the common source 201 in fig. 15 has the same structure as the memory device shown in fig. 20, so the structure and operation principle of the device shown in fig. 20 refer to the description of the device in fig. 15, and are not described again here.

In the prior memory device (e.g., fig. 1a and 1b), the bump T1 is part of the substrate 11, and the semi-floating gate (polysilicon layer 15) and the bump T1 are stacked together in different units. The memory of the embodiment forms the convex-like body on the self body of the semi-floating gate material layer, and the convex-like body is used as a part of the self body of the semi-floating gate material layer, namely the semi-floating gate material layer and the convex-like body are in an integral structure; the structure is different from the structure that the semi-floating gate and the convex body of the prior memory device are stacked together in different units. The etching step (fig. 1a and fig. 1b) for etching the polysilicon layer and the substrate with a partial thickness together to form the convex body is omitted. The failure of the semi-floating gate transistor caused by the difficulty in controlling the precision of the etching process due to the small etching selection ratio of the polycrystalline silicon layer to the substrate is avoided.

In summary, the present invention provides a memory device and a method for fabricating the same, wherein a thermal process is used to convert the material of the semi-floating gate material layer located above the contact window with a partial thickness from polysilicon to single crystal silicon; the transformed region is defined as a convex-like body. The invention develops a new method, and the convex body is formed by adopting a heat treatment method, so that the problem that the semi-floating gate transistor fails because the etching selection ratio of the polycrystalline silicon layer to the substrate is very small and the etching process precision is difficult to control in the conventional process of forming the convex body by etching is avoided. The semi-floating gate material layer and the drain region are connected only through the convex-like body, and the area of a leakage current path is only the physical width of the convex-like body which can be accurately controlled; the built-in potential barrier in the convex-like body can prevent carriers between the semi-floating gate material layer and the drain region from diffusing in a non-working state. Therefore, the leakage of the stored charges in the semi-floating gate is greatly reduced, and the stability of the stored information is improved.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the device disclosed by the embodiment, the description is relatively simple because the device corresponds to the method disclosed by the embodiment, and the relevant part can be referred to the method part for description.

The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims

1. A method of fabricating a memory device, comprising:

2. The method of fabricating a memory device according to claim 1, wherein the heat treatment is performed at a temperature ranging from 1000 ℃ to 1200 ℃.

3. The method of fabricating a memory device according to claim 1, wherein the substrate further comprises a peripheral region, the peripheral region being distributed with an active region; the heat treatment process comprises a thermal oxidation process, and a gate oxide layer grows on the surface of the substrate of the active region of the peripheral region.

4. The method of fabricating a memory device of claim 3, wherein performing said thermal oxidation process further comprises:

5. The method of manufacturing a memory device of claim 1,

providing the substrate includes: doping ions of a second doping type in the substrate to form a well region; doping ions of a first doping type in the well region to form a doped region, wherein the doped region extends from the inside of the well region to the upper surface of the substrate, and the common source region and the first and second drain regions are formed on the top of the doped region;

6. The method of fabricating a memory device according to claim 1, further comprising forming a first trench in the substrate between the common source region and the first drain region and a second trench in the substrate between the common source region and the second drain region before forming the gate insulating layer; the first contact window is located between the first drain region and the first trench, and the second contact window is located between the second drain region and the second trench.

7. The method of manufacturing a memory device according to claim 6, wherein after the gate insulating layer and the floating gate material layer are formed, the gate insulating layer further covers inner surfaces of the first trench and the second trench, and the floating gate material layer covers the gate insulating layer and fills the first trench and the second trench.

8. The method for fabricating a memory device according to any one of claims 1 to 7, wherein after forming the semi-floating gate material layer and before performing the thermal treatment process, further comprising:

9. The method of fabricating a memory device of claim 8, wherein after performing the thermal process, further comprising:

10. A method of fabricating a memory device, comprising:

11. The method of fabricating a memory device according to claim 10, wherein the substrate further comprises a peripheral region, the peripheral region being distributed with an active region; the heat treatment process comprises a thermal oxidation process, and a gate oxide layer grows on the surface of the substrate of the active region of the peripheral region.

12. The method of fabricating a memory device of any of claims 10-11, wherein after forming the layer of semi-floating gate material and before performing the thermal process, further comprising:

13. The method of fabricating a memory device of claim 12, wherein after performing the thermal process, further comprising:

14. A memory device, comprising:

15. The memory device of claim 14, wherein the memory device comprises a semi-floating gate transistor; the semi-floating gate transistor includes: the source region, the drain region, the convex-like body positioned above the contact window, the semi-floating gate, the dielectric layer between the gates and the control gate.

16. The memory device of claim 15, wherein adjacent two of said semi-floating gate transistors share a source region.

17. The memory device of claim 14, wherein the substrate further comprises a peripheral region, the peripheral region having an active region disposed thereon, the substrate surface of the active region having a gate oxide layer grown thereon.