CN114039692B - Hard clock synchronization method - Google Patents
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- CN114039692B CN114039692B CN202111300392.XA CN202111300392A CN114039692B CN 114039692 B CN114039692 B CN 114039692B CN 202111300392 A CN202111300392 A CN 202111300392A CN 114039692 B CN114039692 B CN 114039692B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
Abstract
The invention discloses a hard clock synchronization method, which is applied to a tree network constructed by a distributed system and comprises the following steps: the root node issues a clock synchronization signal; when receiving a clock synchronization signal sent by a directly connected father node, the branch node forwards the clock synchronization signal to a directly connected child node, simultaneously starts timing, and feeds back a response signal to the father node when timing is finished; when a child node receives a response signal fed back by any directly connected child node, calculating and recording actual measurement link delay between the child node and the child node according to the time of receiving the response signal, the time of sending a clock synchronization signal to the child node and the timing duration, so as to perform data transceiving with the child node based on the actual measurement link delay; wherein any of the child nodes is a branch node or the root node. The invention realizes the distributed clock synchronization with ultra-high precision and can meet the requirement of an industrial application network system on strong real-time property.
Description
Technical Field
The invention belongs to the technical field of clock synchronization, and particularly relates to a hard clock synchronization method.
Background
In a centralized system, any two events in the system have a definite precedence relationship, since all processes or modules can obtain time from the system's unique global clock. In a distributed system, due to physical dispersion, the system cannot provide a uniform global clock for the modules independent of each other, but each process or module maintains its local clock. Due to inconsistency of the timing rate and the operating environment of the local clocks, even if all the local clocks are calibrated at a certain time, the local clocks are inconsistent after a period of time. Therefore, in order for these local clocks to maintain the same time value, clock synchronization must be performed.
In the prior art, IEEE1588 standard is mainly used for realizing distributed clock synchronization. IEEE1588 is a Precision clock synchronization Protocol standard of a network measurement and control system, which is referred to as clock synchronization Protocol (PTP) for short. IEEE1588 proposes a clock protocol that synchronizes clocks running independently at separate nodes dispersed in a measurement and control system to a high precision and a high accuracy, which protocol standard enables a delicate level of clock synchronization in a local area network-based distributed data acquisition or data transmission system. At present, the IEEE1588 standard has developed two versions of IEEE1588V1 and IEEE1588V2, the latter proposes a concept of a transparent clock model on the basis of the former, and solves the problem of accumulative errors in a cascaded network by calculating the delay of a message in a network switching device, so that the precision of clock synchronization is improved.
However, although the clock synchronization accuracy of the IEEE1588v2 standard can reach 100 ns, it is still difficult to meet the requirement of strong real-time performance of the industrial application network system. Therefore, how to implement ultra-high precision distributed clock synchronization so as to meet the requirement of an industrial application network system on strong real-time performance is a technical problem to be solved urgently in the prior art.
Disclosure of Invention
In order to solve the above technical problems in the prior art, the present invention provides a hard clock synchronization method.
The technical problem to be solved by the invention is realized by the following technical scheme:
a hard clock synchronization method is applied to a tree network constructed by distributed systems, and the method comprises the following steps:
the root node issues a clock synchronization signal;
when receiving a clock synchronization signal sent by a directly connected father node, the branch node forwards the clock synchronization signal to a directly connected child node, simultaneously starts timing and timing, and feeds a response signal back to the father node when timing is finished;
when a sub-node receives a response signal fed back by any directly connected sub-node, calculating and recording the actually measured link delay between the sub-node and the sub-node according to the time of receiving the response signal, the time of sending a clock synchronization signal to the sub-node and the timing duration, so as to receive and transmit data with the sub-node based on the actually measured link delay;
wherein any of the child nodes is a branch node or the root node.
Optionally, the duration of the timing is not less than 1024 nanoseconds.
Optionally, the duration of the timing is 2 microseconds.
Optionally, the calculation method of the measured link delay includes:
wherein, t 2 For the time when the child node receives the response signal sent by the child node, t 1 For a moment in time, T, at which a child node forwards a clock synchronization signal to the child node cal Duration of said timing, t delay Is the calculated measured link delay.
Optionally, the clock synchronization signal and the response signal are both data with a frame length of 64 bytes.
Optionally, the clock synchronization precision of the hard clock synchronization method is 8 nanoseconds.
The invention also provides another hard clock synchronization method, which is applied to a tree network constructed by distributed systems, and comprises the following steps:
a root node continuously transmits a plurality of clock synchronization signals according to a preset time interval;
when receiving any clock synchronization signal sent by a directly connected father node, the branch node forwards the clock synchronization signal to a directly connected child node, starts timing and timing at the same time, and feeds a response signal corresponding to the clock synchronization signal back to the father node when timing is finished;
when a child node receives a response signal fed back by any directly connected child node, calculating the actually measured link delay between the child node and the child node according to the time of receiving the response signal, the time of sending a corresponding clock synchronization signal to the child node and the time length of the timing;
after the root node stops sending the clock synchronization signal, determining and recording reference link delay between the sub node and the child node by the child node according to multiple times of actual measurement link delay between the child node and each directly connected child node, so as to perform data transceiving with the child node based on the reference link delay;
wherein any of the child nodes is a branch node or the root node.
Optionally, the duration interval is equal to or greater than the duration of the timing.
Optionally, determining, by a child node, a reference link delay between the child node and the child node according to multiple measured link delays between the child node and the child node, where the determining includes:
and aiming at each child node, the child node calculates the average value of multiple times of actually measured link delay between the child node and the child node, and the average value is used as the reference link delay between the child node and the child node.
Optionally, the determining, by a child node, a reference link delay between the child node and the child node according to multiple measured link delays between the child node and each child node includes:
and aiming at each sub node, the sub node screens actual measurement link delay meeting the requirement from multiple actual measurement link delays between the sub node and the sub node by using a preset screening rule, and then calculates the average value of the screened actual measurement link delays to be used as reference link delay between the sub node and the sub node.
The invention has the beneficial effects that:
in the hard clock synchronization method provided by the invention, a root node issues a clock synchronization signal to trigger branch nodes of the lower layers to sequentially forward the clock synchronization signal, and start timing and timing at the same time of forwarding, and when the timing is finished, the branch nodes feed back response signals to respective father nodes. In the process, for a child node (root node or branch node), the time when the child node sends a clock synchronization signal downwards and the time when a response signal fed back by the child node is received are known, and the time length of timing is also known, so that the actually measured link delay between the child node and the child node directly connected with the child node can be calculated according to the two times and the time length; therefore, the actually measured link delay can be taken into account when data is transmitted and received between the father node and the child node, and therefore the global single clock is realized in the whole network. Therefore, the link delay among the nodes is obtained by a hardware actual measurement mode, so that the clock synchronization precision is only determined by the working frequency of a hardware physical chip, for example, a high-speed chip with the working frequency of 133MHz can achieve the ultrahigh clock synchronization precision of about 8 nanoseconds, and the requirement of an industrial application network system on strong real-time performance can be met.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram illustrating a tree network constructed by a distribution system;
FIG. 2 is a flowchart illustrating a method for synchronizing a hard clock according to an embodiment of the present invention;
FIG. 3(a) is a schematic diagram illustrating the operation timing of a branch node, its parent node and its child nodes in the method shown in FIG. 2;
FIG. 3(b) is a schematic diagram illustrating a principle that a sub-node calculates a measured link delay in the method shown in FIG. 2;
fig. 4 is a flowchart illustrating another hard clock synchronization method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
In order to realize the ultra-high precision distributed clock synchronization and meet the requirement of an industrial application network system on strong real-time property, the embodiment of the invention provides a hard clock synchronization method, which is applied to a tree network constructed by distributed systems. FIG. 1 is a schematic diagram illustrating a tree network constructed by a distribution system; referring to fig. 1, the topmost node of the tree network is the root node, represented by root in fig. 1, which is the parent node of nodes 2, 3 and 4. Under the root node, all nodes with directly connected child nodes are branch nodes; as in fig. 1, node 2, node 3, node 4 and node 7 are all branch nodes; wherein the child node of the branch node 7 is the node 10, i.e. the branch node 7 is the parent node of the node 10. The nodes without child nodes at the tail end of the tree network are leaf nodes; nodes 5, 6, 8, 9 and 10 in fig. 1 are leaf nodes. It is understood that the root node and the branch node have directly connected children, and thus they are collectively referred to as having children. That is, any child node in the tree network may be a branch node or a root node.
In practical applications, there are various methods for building a tree network by distributed systems. For example, the Tree network may be constructed based on STP (Spanning Tree Protocol), RSTP (Rapid Spanning Tree Protocol), or other protocols/methods for shaping a network structure based on a Spanning Tree concept. In the finally constructed tree network, each branch node and each leaf node are provided with only one directly connected father node.
For example, for a system with any network topology, a tree network can be established between adjacent nodes in the system through data/message transmission and reception. Each node sends a message/data to the outside, where the message/data carries an identifier (denoted as a BsetID) of a root node considered by the node and a level (denoted as a level) of the node relative to the root node. In practical applications, the ID of the node itself may be the MAC address of the node, but is not limited thereto. Wherein, each node initially considers itself as a root node; that is, in the data/packet initially sent by each node to the neighboring node, the BsetID is its own ID, and the level is the level of the root node, which may be 0 or 1. In the formal networking stage, each node circularly executes arbitration actions: the node compares the size of the BsetID identified by the node with the size of the BsetID carried in the received data/message so as to arbitrate the node with the smaller ID as a root node; then, the node updates the BsetID and level in the data/message according to the arbitrated root node, and continuously sends the updated data/message to the adjacent node. The arbitration action and the data/message receiving and sending mechanism are continuously carried out until all the nodes consider the root nodes to be the same; at the moment, the root node is determined, the hierarchical division of the tree network is also clear based on the physical connection relation among the nodes, and each node can know which nodes connected with the upper layer and the lower layer of the node per se are; if two or more nodes are directly connected to the upper layer of a node, the node can select one of the nodes on the upper layer as a unique parent node, and the selection standard can be realized by comparing the sizes of the node IDs, but is not limited to the mode; after a father node is selected, the node disconnects the communication links among other nodes directly connected with the upper layer, and disconnects the communication barriers among the nodes on the same layer, so as to avoid forming a loop in the network, and thus, the networking of the tree network can be completed. In practical application, a certain networking time duration can be set in the node for the node to execute the above process, and the time duration is usually positively correlated with the maximum possible level in the network topology of the system; that is, the more maximum possible tiers, the longer the networking time required.
After the tree network is built, the hard clock synchronization method provided by the embodiment of the invention can be applied to the network to perform distributed clock synchronization. Referring to fig. 2, a hard clock synchronization method provided in an embodiment of the present invention includes the following steps:
s201: and the root node issues a clock synchronization signal.
Here, the root node issues the clock synchronization signal, that is, the root node sends the clock synchronization signal to the child node directly connected to the root node. For example, in FIG. 1, the root node sends a clock synchronization signal to node 2, node 3, and node 4.
In practical application, the clock synchronization signal is a frame of well-defined data; for example, the clock synchronization signal may be the shortest communication frame that is allowed to flow over the network. For example, the clock synchronization signal may be a frame of 64 bytes in length of data.
S202: when receiving a clock synchronization signal sent by a directly connected father node, the branch node forwards the clock synchronization signal to a directly connected child node, simultaneously starts timing and timing, and feeds a response signal back to the father node when timing is finished.
The specific implementation process can be seen in fig. 3(a), and the link delay between a branch node and its parent node is assumed to be t delay1 The link delay between a branch node and its child nodes is t delay2 . The father node sends a clock synchronization signal to the branch node; has passed through t delay1 The branch node receives the clock synchronization signal, at which point the branch node immediately forwards the clock synchronization signal down to the child node,and simultaneously starting timing; when the timing is over, the branch node feeds back a response signal 1 to the father node, and the response signal 1 also passes through t delay1 The link of (2) reaches the parent node after a delay. Similarly, the clock synchronization signal sent by the branch node to the child node passes through t delay2 When the link delay reaches the child node, the child node immediately forwards the clock synchronization signal downwards to the child node (not shown in the figure) of the next layer, and simultaneously starts timing; when the timing is finished, the child node feeds a response signal 2 back to the branch node; the response signal 2 likewise passes through t delay After a delay, reaches the branch node.
For example, referring to fig. 1, when receiving a clock synchronization signal sent by a directly connected parent node (i.e., a root node), nodes 2, 3, and 4 each forward the received clock synchronization signal to a directly connected child node; wherein, the node 2 forwards the clock synchronization signal received by itself to the node 5; the node 3 forwards the clock synchronization signals received by the node to the nodes 6, 7 and 8 in parallel; the node 4 forwards the clock synchronization signal received by itself to the child node 9. In addition, since the node 7 is also a branch node, the node 7 immediately forwards the clock synchronization signal to the node 10 when receiving the clock synchronization signal from the node 3.
It is understood that, in step S202, the forwarding action performed by the branch node for the clock synchronization signal is not limited to data forwarding in a strict sense, and the branch node may also generate an identical clock synchronization signal immediately in response to the received clock synchronization signal and send the clock synchronization signal to the child node.
In an alternative implementation, the response signal and the clock synchronization signal may have the same length and the same content.
S203: when a child node receives a response signal fed back by any directly connected child node, the actually measured link delay between the child node and the child node is calculated and recorded according to the time of receiving the response signal, the time of sending a clock synchronization signal to the child node and the timing duration, so that data receiving and sending are carried out on the child node based on the actually measured link delay.
Referring to fig. 3(b), the measured link delay in a child node is calculated as follows:
in the formula, t 1 For a moment, t, at which a child node forwards a clock synchronization signal Sync to the child node 2 T is the time when the child node receives the child node feedback to respond to the signal Ack cal For timing the duration of the time, t delay Is the calculated measured link delay.
For example, in conjunction with FIG. 1; the root node receives response signals fed back by the nodes 2, 3 and 4; the root node calculates the actually measured link delay a between the root node and the node 2 according to the time of receiving the response signal fed back by the node 2, the time of sending the clock synchronization signal to the node 2 and the timing duration, and then records the actually measured link delay a; according to the above process, the root node performs the same action for the nodes 3 and 4, so that the measured link delay b between the root node and the node 3 and the measured link delay c between the node 4 are both recorded.
The node 2 receives a response signal fed back by the node 5; therefore, the node 2 calculates the measured link delay d between the node 2 and the node 5 according to the time of receiving the response signal fed back by the node 5, the time of sending the clock synchronization signal to the node 5 and the timing duration, and records the measured link delay d.
The node 3 receives response signals fed back by the nodes 6, 7 and 8; the node 3 calculates an actually measured link delay e between the node 3 and the node 6 according to the time of receiving a response signal fed back by the node 6, the time of sending a clock synchronization signal to the node 6 and the timing duration, and then records the actually measured link delay e; following the above procedure, node 3 performs the same actions for nodes 7, 8, thereby recording the measured link delay f between node 3 and node 7, and the measured link delay g between node 8.
The node 4 receives a response signal fed back by the node 9; therefore, the node 4 calculates the actually measured link delay h between the node 4 and the node 9 according to the time of receiving the response signal fed back by the node 9, the time of sending the clock synchronization signal to the node 9 and the timing duration, and records the actually measured link delay h.
The node 7 receives a response signal fed back by the node 10; therefore, the node 7 calculates the measured link delay i between the node 7 and the node 10 according to the time of receiving the response signal fed back by the node 10, the time of sending the clock synchronization signal to the node 10 and the timing duration, and records the measured link delay i.
Thus, the measured link delay between each two neighboring nodes in fig. 1 is known. Therefore, link delay can be taken into account when data is transmitted and received between subsequent nodes, so that timeliness of the data in the transmission process can be accurately and effectively guaranteed.
In practical applications, the manner of performing data transceiving between nodes based on measured link delay may include: when the father node sends data to the child node, the father node sends the actually measured link delay and the data to be sent to the child node, so that the child node can acquire the real generation time or the real updating time of the data at the father node according to the carried actually measured link delay after receiving the data. When the child node sends data to the parent node, the parent node can directly determine the real generation time or update time of the data at the child node according to the time of receiving the data and the recorded measured link delay. It should be noted that the manner of performing data transceiving based on the measured link delay shown here is merely an example, and does not limit the embodiment of the present invention; any mode of acquiring the actually measured link delay based on the hardware actually measured mode and transmitting data between nodes based on the actually measured link delay to realize clock synchronization provided by the embodiment of the invention belongs to the protection scope of the embodiment of the invention.
In the hard clock synchronization method provided by the embodiment of the invention, the root node issues the clock synchronization signal to trigger the branch nodes of each layer to sequentially forward the clock synchronization signal, and start timing at the same time of forwarding, and when the timing is finished, the root node feeds back a response signal to each father node. In the process, for the subnode (root node or branch node), the time for sending the clock synchronization signal downwards and the time for receiving the response signal fed back by the subnode are known, and the timing duration is also known, so that the actual measurement link delay between the subnode and the directly connected subnode can be calculated according to the two times and the time duration; therefore, the actually measured link delay can be taken into account when data is transmitted and received between the father node and the child node, and therefore the global single clock is realized in the whole network. Therefore, the link delay in the embodiment of the present invention is obtained by hardware measurement, and is therefore referred to as a hard clock synchronization method. Therefore, the clock synchronization precision of the hard clock synchronization method is determined only by the working frequency of the hardware physical chip, for example, a high-speed chip with the working frequency of 133MHz can achieve the ultrahigh clock synchronization precision of about 8 nanoseconds, and can completely meet the requirement of an industrial application network system on strong real-time property.
In one implementation, in order to meet the limitation on the shortest communication frame length (64 bytes) in the current ethernet protocol, the branch node starts the timing at step S202, and the duration of the timing is not less than 1024 ns.
Specifically, after the branch node starts to send the clock synchronization signal to the child node, transmission of the signal takes a certain time, so that the branch node starts timing to ensure that the clock synchronization signal can be completely transmitted to the child node, and then feeds back a response signal to the parent node in the upper layer. Because the clock synchronization signal is also a communication frame, if the clock synchronization signal is required to meet the limit of the shortest communication frame length, the length of the clock synchronization signal is at least 64 bytes, and the Ethernet protocol specifies that the shortest communication frame length also has a delay of 64 bytes; therefore, in the context that it takes 8 ns for transmission of a single byte, the timing of the branch node is only not less than (64+64) × 8 ═ 1024 ns, so as to ensure that the response signal is fed back to the parent node of the upper layer after the clock synchronization signal is completely transmitted to the child node. On this basis, the timing duration in the branch node is preferably 2 microseconds.
Of course, since the shortest communication frame length is only the specification of the existing ethernet protocol, the limit of 1024 ns is only to enable the hard clock synchronization method provided by the embodiment of the present invention to better adapt and match the existing ethernet. Therefore, the timing duration of 1024 ns is only one choice for adapting the current ethernet, and this choice does not affect the application of the hard clock synchronization method provided by the embodiment of the present invention in future networks. That is, in future networks, if there is no limitation on the length of the lowest communication frame or the length of the lowest communication frame is smaller than 64 bytes, the timing duration of the branch node in the embodiment of the present invention may be lower than 1024 nanoseconds.
Based on the same inventive concept, the embodiment of the invention also provides another hard clock synchronization method, and the method is also applied to a tree network constructed by a distributed system. Referring to fig. 4, the method comprises the steps of:
s401: and the root node continuously transmits a plurality of clock synchronization signals according to a preset time interval.
It can be understood that, the root node continuously sends each clock synchronization signal in sequence to the child nodes directly connected with the root node according to a predetermined time interval; under the condition that the communication between the nodes is smooth, each child node directly connected with the root node receives a plurality of clock synchronization signals.
In the embodiment of the present invention, the number of clock synchronization signals continuously issued by the root node may be determined based on the number of layers of the tree network. In general, the number of layers of the tree network constructed by the distributed system does not exceed 10, so that the root node may continuously issue 10 clock synchronization signals in step S401. Therefore, even if one or two clock synchronization signals are missed due to factors such as burst interference and the like in the communication condition between the nodes, the synchronous operation of the nodes at the lower layer cannot be influenced due to the fact that the number of the clock synchronization signals issued by the root node is large. Of course, the value 10 is given here only as an example, and may be specifically determined based on the number of layers of the actual tree network, and may be equal to or slightly larger than the number of layers of the actual tree network.
S402: when receiving any clock synchronization signal sent by a directly connected father node, the branch node forwards the clock synchronization signal to a directly connected child node, starts timing and timing at the same time, and feeds a response signal corresponding to the clock synchronization signal back to the father node when timing is finished.
It can be understood that, since the parent node of the branch node continuously sends a plurality of clock synchronization signals to the branch node, the branch node sequentially responds and processes each received clock synchronization signal, and each time a clock synchronization signal is received, a response signal is correspondingly fed back to the parent node, and then a response and processing are performed on the next clock synchronization signal. The response and processing manner of the branch node for a single clock synchronization signal are the same as those in step S202, and are not described here again.
Preferably, the time interval used by the root node in step S401 is equal to or greater than the time interval timed by the branch node in step S402. Therefore, the branch nodes do not need to start a plurality of timers, and can sequentially respond to and process each received clock synchronization response signal by starting one timer.
S403: when a sub-node receives a response signal fed back by any directly connected sub-node, the actual measurement link delay between the sub-node and the sub-node is calculated according to the time of receiving the response signal, the time of sending a corresponding clock synchronization signal to the sub-node and the time length of timing.
Wherein any child node is a branch node or a root node.
In this step, the manner of calculating the measured contact delay by the child node in response to the single response signal is the same as that in step S203, and details thereof are not repeated here. When the child nodes receive response signals fed back by different child nodes at the same time, the actually measured link delay with each child node can be calculated in sequence, and the actually measured link delay with each child node can also be calculated in parallel at the same time; it will be appreciated that parallel computing is also easy to implement for children nodes as electronic devices.
S404: after the root node stops sending the clock synchronization signal, the child nodes determine and record the reference link delay between the child nodes and the child nodes according to the multiple actual measurement link delay between the child nodes and each directly connected child node, so as to perform data transceiving with the child nodes based on the reference link delay.
It can be understood that, after the root node stops transmitting the clock synchronization signal, some child nodes will not receive a new clock synchronization signal in a future period of time, so that some child nodes can determine that the root node has stopped transmitting the clock synchronization signal. And then, the sub-node determines the reference link delay between the sub-node and the self-node according to the multiple measured link delays between the sub-node and each directly connected sub-node, records the determined reference link delay, and then receives and transmits data with the sub-node based on the reference link delay. The specific data transceiving method has been described above by way of example, and is not described herein again.
The specific implementation modes of determining the reference link delay between the subnode and the subnode by the subnode are various according to the multiple measured link delays between the subnode and each directly connected subnode.
For example, in one implementation, for each child node, there is a child node that may find an average of multiple measured link delays between itself and the child node as a reference link delay between itself and the child node.
The realization mode is more suitable for being applied to a system in a network environment, and the multiple times of actually measured link delay in the system is relatively real and effective link delay and is not easy to generate abnormal values.
In another implementation manner, for each child node, a child node may screen, by using a preset screening rule, an actual measurement link delay meeting a requirement from multiple actual measurement link delays between itself and the child node, and then obtain a mean value of the screened actual measurement link delays, which is used as a reference link delay between itself and the child node.
For example, for each sub-node, the largest measured link delay and the smallest measured link delay are removed from the multiple measured link delays between the sub-node and the sub-node. Or, for each child node, screening out the actual measured link delay within a preset range from multiple actual measured link delays between the child node and the child node. The preset range can be set according to the real link delay tested in advance, and the main function is to eliminate the obviously abnormal link delay data.
It can be understood that the latter implementation manner is more suitable for being applied to a system in which a network environment may have a sudden situation (e.g., occurrence of sudden interference), and by removing abnormal link delay data, the finally determined reference link delay can be made to be closer to the actual link delay between nodes.
In one embodiment, in order to meet the limitation of the shortest communication frame length (64 bytes) in the current ethernet protocol, the branch node starts the timing at step S402, and the timing duration is not less than 1024 ns, and is preferably set to 2 μ S.
It should be noted that, for the latter embodiment of the hard clock synchronization method, since it is substantially similar to the former embodiment of the hard clock synchronization method, the description is relatively simple, and the relevant points can be referred to the partial description of the method embodiment.
In the hard clock synchronization method provided by the embodiment of the invention, the root node issues the clock synchronization signal to trigger the branch nodes of the lower layers to sequentially forward the clock synchronization signal, and start timing at the same time of forwarding, and when the timing is finished, the branch nodes feed back response signals to respective father nodes. In the process, for a child node (root node or branch node), the time when the child node sends the clock synchronization signal downwards and the time when the child node receives the response signal fed back by the child node are both known, and the time length of timing is also known, so that the actually measured link delay between the child node and the child node directly connected with the child node can be calculated according to the two times and the time length. Moreover, the root node continuously sends a plurality of clock synchronous signals to trigger the branch node to test the link delay between the branch node and the child node for a plurality of times; determining a more accurate reference link delay based on the measured link delays of the multiple tests; therefore, when data is transmitted and received between the parent node and the child node, the reference link delay can be taken into account, and therefore a global single clock is achieved in the whole network. Because the reference link delay is determined based on the link delay actually measured by hardware, the clock synchronization precision of the embodiment of the invention is only determined by the working frequency of a hardware physical chip, for example, a high-speed chip with the working frequency of 133MHz can achieve the ultrahigh clock synchronization precision of about 8 nanoseconds, and can completely meet the requirement of an industrial application network system on strong real-time property.
In the description of the specification, references to descriptions of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like are intended to mean that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.
Claims (10)
1. A hard clock synchronization method applied to a tree network constructed by distributed systems, the method comprising:
the root node issues a clock synchronization signal;
when receiving a clock synchronization signal sent by a directly connected father node, the branch node forwards the clock synchronization signal to a directly connected child node, simultaneously starts timing and timing, and feeds a response signal back to the father node when timing is finished;
when a sub-node receives a response signal fed back by any directly connected sub-node, calculating and recording the actually measured link delay between the sub-node and the sub-node according to the time of receiving the response signal, the time of sending a clock synchronization signal to the sub-node and the timing duration, so as to receive and transmit data with the sub-node based on the actually measured link delay;
wherein any child node is a branch node or the root node;
the tree network is a tree network constructed from a system with any network topology, and the networking mode of the tree network comprises the following steps:
each node sends out a message/data which carries an identifier BsetID of a root node considered by the node and a level of the node relative to the root node; in the data/message sent by each node to the adjacent node initially, the BsetID is the ID of the node, and the level is the level of the root node;
each node circularly executes arbitration actions: the node compares the size of the BsetID identified by the node with the size of the BsetID carried in the received data/message so as to arbitrate the node with the smaller ID as a root node; then, the node updates the BsetID and level in the data/message according to the arbitrated root node, and continuously sends the updated data/message to the adjacent node;
the arbitration action and the message/data receiving and sending mechanism are continuously carried out until all the nodes consider the root nodes to be the same; after the root node is determined, forming hierarchical division of the tree network based on the physical connection relation among the nodes; if two or more nodes are directly connected to the upper layer of a node, the node is selected from the nodes on the upper layer as a unique father node, and after one father node is selected, the node disconnects communication links among other nodes directly connected to the upper layer and disconnects communication barriers among the nodes on the same layer;
the networking time set in the node is positively correlated with the maximum possible level in the network topology of the system.
2. The method of claim 1, wherein the timing is not less than 1024 nanoseconds in duration.
3. The method of claim 2, wherein the timing is 2 microseconds in duration.
4. The hard clock synchronization method of claim 1, wherein the measured link delay is calculated in a manner comprising:
wherein, t 2 For the time when the child node receives the response signal sent by the child node, t 1 For a moment in time, T, at which a child node forwards a clock synchronization signal to the child node cal Time length, t, of said timing delay Is the calculated measured link delay.
5. The method of claim 1, wherein the clock synchronization signal and the response signal are each a frame of 64 bytes long of data.
6. The hard clock synchronization method of claim 1, wherein the clock synchronization accuracy of the hard clock synchronization method is 8 nanoseconds.
7. A hard clock synchronization method is applied to a tree network constructed by distributed systems, and the method comprises the following steps:
the root node continuously transmits a plurality of clock synchronization signals according to a preset time interval;
when receiving any clock synchronization signal sent by a directly connected father node, the branch node forwards the clock synchronization signal to a directly connected child node, starts timing and timing at the same time, and feeds a response signal corresponding to the clock synchronization signal back to the father node when timing is finished;
when a sub-node receives a response signal fed back by any directly connected sub-node, calculating the actually measured link delay between the sub-node and the sub-node according to the time of receiving the response signal, the time of sending a corresponding clock synchronization signal to the sub-node and the time length of the timing;
after the root node stops sending the clock synchronization signal, determining and recording reference link delay between the root node and each directly connected sub-node by the sub-node according to multiple actual measurement link delay between the root node and each directly connected sub-node, so as to receive and transmit data with the sub-node based on the reference link delay;
wherein any child node is a branch node or the root node;
the tree network is a tree network constructed from a system with any network topology, and the networking mode of the tree network comprises the following steps:
each node sends out a message/data which carries an identifier BsetID of a root node considered by the node and a level of the node relative to the root node; in the data/message sent by each node to the adjacent node initially, the BsetID is the ID of the node, and the level is the level of the root node;
each node performs arbitration actions in a cycle: the node compares the size of the BsetID identified by the node with the size of the BsetID carried in the received data/message so as to arbitrate the node with the smaller ID as a root node; then, the node updates the BsetID and level in the data/message according to the arbitrated root node, and continuously sends the updated data/message to the adjacent node;
the arbitration action and the message/data receiving and sending mechanism are continuously carried out until all the nodes consider the root nodes to be the same; after the root node is determined, forming hierarchical division of the tree network based on the physical connection relation among the nodes; if two or more nodes are directly connected to the upper layer of a node, the node is selected from the nodes on the upper layer as a unique father node, and after one father node is selected, the node disconnects communication links among other nodes directly connected to the upper layer and disconnects communication barriers among the nodes on the same layer;
the networking time length set in the node is positively correlated with the maximum possible level in the network topology of the system.
8. The method of hard clock synchronization of claim 7, wherein the duration interval is equal to or greater than the duration of the timing tick.
9. The method of claim 7, wherein determining, by a child node, a reference link delay between itself and each child node based on a plurality of measured link delays between itself and the child node comprises:
and aiming at each child node, the child node calculates the average value of multiple times of actually-measured link delay between the child node and the child node, and the average value is used as the reference link delay between the child node and the child node.
10. The method of claim 7, wherein determining, by a child node, a reference link delay between itself and each child node based on a plurality of measured link delays between itself and the child node comprises:
and aiming at each sub node, the sub node screens the actual measurement link delay meeting the requirement from the multiple actual measurement link delays between the sub node and the sub node by using a preset screening rule, and then the mean value of the screened actual measurement link delays is obtained and used as the reference link delay between the sub node and the sub node.
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| CN101588628A (en) * | 2009-06-19 | 2009-11-25 | 山东省计算中心 | Clock synchronizing method for wireless sensor network |
| CN103188064A (en) * | 2011-12-28 | 2013-07-03 | 中兴通讯股份有限公司 | Clock synchronization method and clock synchronization device |
| CN108599888A (en) * | 2018-05-09 | 2018-09-28 | 西安电子科技大学 | A kind of distributed network clock synchronizing system |
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