CN114039581A - Clock switching circuit - Google Patents

Clock switching circuit Download PDF

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Publication number
CN114039581A
CN114039581A CN202111320632.2A CN202111320632A CN114039581A CN 114039581 A CN114039581 A CN 114039581A CN 202111320632 A CN202111320632 A CN 202111320632A CN 114039581 A CN114039581 A CN 114039581A
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clock
signal
gate
input end
feedback unit
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宗霄
侯卫华
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Alchip Technologies Shanghai Ltd
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Alchip Technologies Shanghai Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electronic Switches (AREA)

Abstract

The invention relates to the technical field of clock switching, and discloses a clock switching circuit, which comprises a first clock input end, a second clock input end, a switching signal input end, a control unit, a first feedback unit, a second feedback unit and a clock selection unit, wherein the first clock input end is connected with the second clock input end through a first switching signal input end; the first clock input end is electrically connected with the first feedback unit and the clock selection unit respectively, and the second clock input end is electrically connected with the second feedback unit and the clock selection unit respectively; the switching signal input end is electrically connected with the control unit, when the clock is required to be switched, the first feedback unit or the second feedback unit can stop sending the current clock signal and enable the clock signal to be switched to be ready to be sent at two continuous level switching moments in the current period of the clock signal, and when the clock signal to be switched is required to be sent, the level switching moment of the clock signal to be switched is taken as a sending starting point, so that the integrity of the currently sent clock signal is ensured, and no burr exists when the clock is switched.

Description

Clock switching circuit
Technical Field
The invention relates to the technical field of clock switching, in particular to a clock switching circuit.
Background
With the progress of the integrated circuit manufacturing process, the technology node has been deepened to 5-3nm, and the chip power consumption becomes an important factor influencing the tape-out success. At present, when a chip is designed, a plurality of clock sources with different frequencies are configured in the chip, so that when the chip is actually used, the chip can select corresponding clock sources according to different task loads so as to control the power consumption of the chip.
The existing clock switching circuit in the chip usually adopts a multiplexer to select a proper clock from clock sources with different frequencies. However, as shown in fig. 1, the use of the multiplexer to select the clock signal may cause the current clock signal to be incomplete and the next clock signal to be glitched, the cycle integrity of the clock signal cannot be guaranteed, and these problems may cause serious circuit function errors.
Disclosure of Invention
In view of the defects of the background art, the invention provides a clock switching circuit, and aims to solve the technical problem that due to the fact that a multiplexer is adopted in the clock switching circuit in the existing chip, the conditions of incomplete clock switching and burrs occur, and the normal use of the chip is influenced.
In order to solve the technical problems, the invention provides the following technical scheme: a clock switching circuit comprises a first clock input end, a second clock input end, a switching signal input end, a control unit, a first feedback unit, a second feedback unit and a clock selection unit;
the first clock input end is electrically connected with the first feedback unit and the clock selection unit respectively, and the second clock input end is electrically connected with the second feedback unit and the clock selection unit respectively; the switching signal input end is electrically connected with the control unit;
the control unit sends a first stop signal to the first feedback unit when the signal at the switching signal input end is changed from a first state to a second state; after the signal at the switching signal input end is changed from the first state to the second state, the first feedback unit sends a first clock stop signal to the clock selection unit at the first level transition moment of the clock signal at the first clock input end, and the first feedback unit sends a first start signal to the control unit at the second level transition moment of the clock signal at the first clock input end; the clock selection unit stops outputting clock signals after receiving the first clock stop signal; the control unit sends a second starting signal to the second feedback unit after receiving the first starting signal; after the second feedback unit receives the second start signal, the second feedback unit sends a second clock start signal to the clock selection unit at a first level transition moment of the clock signal at the second clock input end, and the clock selection unit starts to output the clock signal at the second clock input end after receiving the second clock start signal;
the control unit sends a second stop signal to the second feedback unit when the signal at the switching signal input end is changed from the second state to the first state; after the signal at the switching signal input end is changed from the second state to the first state, the second feedback unit sends a second clock stop signal to the clock selection unit at the first level transition moment of the clock signal at the second clock input end, and the second feedback unit sends a third start signal to the control unit at the second level transition moment of the clock signal at the second clock input end; the clock selection unit stops outputting the clock signal after receiving the second clock stop signal; the control unit sends a fourth start signal to the first feedback unit after receiving the third start signal, after the first feedback unit receives the fourth start signal, the first feedback unit sends a clock start signal to the clock selection unit at a first level transition moment of a clock signal at the first clock input end, and the clock selection unit starts to output the clock signal at the first clock input end after receiving the clock start signal.
In one embodiment, the first state is a low state and the second state is a high state.
In one embodiment, after the signal at the switching signal input end changes from the first state to the second state, the first level transition time of the clock signal at the first clock input end of the first feedback unit refers to the time when the clock signal at the first clock input end changes from the high level to the low level, and the second level transition time of the clock signal at the first clock input end of the first feedback unit refers to the time when the clock signal at the first clock input end changes from the low level to the high level; after the second feedback unit receives the second start signal, the first level transition time of the clock signal at the second clock input end of the second feedback unit is the time when the clock signal at the second clock input end is transitioned from the high level to the low level;
after the signal at the switching signal input end is changed from the second state to the first state, the first level transition time of the clock signal at the second clock input end of the second feedback unit refers to the time when the clock signal at the second clock input end is changed from the high level to the low level, and the second level transition time of the clock signal at the second clock input end of the second feedback unit refers to the time when the clock signal at the second clock input end is changed from the low level to the high level; after the first feedback unit receives the fourth start signal, the first level transition time of the clock signal at the first clock input end of the first feedback unit refers to the time when the clock signal at the first clock input end transitions from a high level to a low level.
In a certain embodiment, the control unit includes a first and gate, a second and gate, and a first inverter, the switching signal input end is electrically connected to the input end of the first inverter and the first input end of the second and gate, respectively, the output end of the first inverter is electrically connected to the first input end of the first and gate, the second input end of the first and gate is electrically connected to the clock first start signal output end of the second feedback unit, the second input end of the second and gate is electrically connected to the clock second start signal output end of the first feedback unit, the output end of the first and gate is electrically connected to the first feedback unit, and the output end of the second and gate is electrically connected to the second feedback unit.
In one embodiment, the first feedback unit includes a first negative edge flip-flop, a first positive edge flip-flop, and a first NOR gate, the clock end of the first negative edge trigger and the clock end of the first positive edge trigger are respectively electrically connected with the first clock input end, the input end of the first negative edge trigger is electrically connected with the control unit and receives a first stop signal and a clock-start signal sent by the control unit, the output end of the first negative edge trigger is respectively and electrically connected with the input end of the first positive edge trigger, the first input end of the first NOR gate and the clock selection unit, the output terminal of the first positive edge flip-flop is electrically connected with the second input terminal of the first nor gate, and the output end of the first NOR gate is electrically connected with the control unit and sends a clock two starting signal to the control unit.
In one embodiment, the second feedback unit includes a second negative edge flip-flop, a second positive edge flip-flop, and a second NOR gate, the clock end of the second negative edge trigger and the clock end of the second positive edge trigger are respectively electrically connected with the second clock input end, the input end of the second negative edge trigger is electrically connected with the control unit and receives a second stop signal and a second clock start signal sent by the control unit, the output end of the second negative edge trigger is respectively and electrically connected with the input end of the second positive edge trigger, the first input end of the second NOR gate and the clock selection unit, the output terminal of the second positive edge flip-flop is electrically connected with the second input terminal of the second nor gate, and the output end of the second NOR gate is electrically connected with the control unit and sends a clock starting signal to the control unit.
In one embodiment, the clock selection unit comprises a third and gate, a fourth and gate and a first or gate, the first input end of the third AND gate is electrically connected with the first clock input end, the second input end of the third AND gate is electrically connected with the first feedback unit, and receives the first clock stop signal and the clock first start signal sent by the first feedback unit, the output end of the third AND gate is electrically connected with the first input end of the first OR gate, the first input end of the fourth AND gate is electrically connected with the second clock input end, the second input end of the fourth and gate is electrically connected with the second feedback unit and receives a second clock stop signal and a second clock start signal sent by the second feedback unit, the output end of the fourth and gate is electrically connected with the second input end of the first or gate, and the output end of the second or gate outputs a clock signal.
Compared with the prior art, the invention has the beneficial effects that: in practical use, when the clock needs to be switched, the first feedback unit or the second feedback unit can stop sending the current clock signal and enable the clock signal to be switched to be ready to be sent at two continuous level switching moments in the current period of the clock signal, and when the clock signal to be switched needs to be sent, the level switching moment of the clock signal to be switched is taken as a sending starting point, so that the integrity of the current sent clock signal is ensured without burrs when the clock is switched, and the clock can be switched in one clock period.
Drawings
FIG. 1 is a schematic diagram of a switching waveform of a conventional clock switching circuit;
FIG. 2 is a block diagram of the present invention in an embodiment;
FIG. 3 is a circuit diagram of the present invention in an embodiment;
FIG. 4 is a waveform diagram of the present invention during clock switching.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
As shown in fig. 2, a clock switching circuit includes a first clock input terminal CLK1, a second clock input terminal CLK2, a switching signal input terminal SEL, a control unit 1, a first feedback unit 2, a second feedback unit 3, and a clock selection unit 4;
the first clock input end is electrically connected with the first feedback unit and the clock selection unit respectively, and the second clock input end is electrically connected with the second feedback unit and the clock selection unit respectively; the switching signal input end is electrically connected with the control unit; wherein the first clock input terminal CLK1 is configured to input the first clock signal, the second clock input terminal CLK2 is configured to input the second clock signal, and the switching signal input terminal SEL is configured to input the switching control signal
The control unit 1 sends a first stop signal to the first feedback unit 2 when the signal at the switching signal input terminal SEL changes from a first state to a second state, wherein the first state changing to the second state means changing from a low level state to a high level state; after the signal at the switching signal input SEL changes from the first state to the second state, the first feedback unit 2 sends a first clock stop signal to the clock selection unit 4 at a first level transition timing of the clock signal at the first clock input CLK1, and the first feedback unit 2 sends a first start signal to the control unit 1 at a second level transition timing of the clock signal at the first clock input CLK 1; the clock selection unit 4 stops outputting the clock signal after receiving the first clock stop signal; the control unit 1 sends a second starting signal to the second feedback unit 3 after receiving the first starting signal; after the second feedback unit 3 receives the second start signal, the second feedback unit 3 sends a second clock start signal to the clock selection unit 4 at a first level transition time of the clock signal at the second clock input terminal CLK2, and the clock selection unit 4 starts to output the clock signal at the second clock input terminal after receiving the second clock start signal; in practical use, the present invention may be realized by the above in this paragraph by switching the output clock signal from the first clock signal at the first clock input terminal CLK1 to the second clock signal at the second clock input terminal CLK 2.
The control unit 1 sends a second stop signal to the second feedback unit 3 when the signal at the switching signal input terminal SEL changes from a second state to a first state, wherein the second state changes to the first state means that the high level state changes to the low level state; after the signal at the switching signal input SEL changes from the second state to the first state, the second feedback unit 3 sends a second clock stop signal to the clock selection unit 4 at a first level transition of the clock signal at the second clock input CLK2, and the second feedback unit 3 sends a third start signal to the control unit 1 at a second level transition of the clock signal at the second clock input; the clock selection unit 4 stops outputting the clock signal after receiving the second clock stop signal; the control unit 1 sends a fourth start signal to the first feedback unit 1 after receiving the third start signal, after the first feedback unit 1 receives the fourth start signal, the first feedback unit 2 sends a clock start signal to the clock selection unit 4 at a first level transition time of the clock signal at the first clock input end CLK1, and the clock selection unit 4 starts to output the clock signal at the first clock input end CLK1 after receiving the clock start signal; in practical use, the present invention can be realized by the above in this paragraph that the output clock signal is switched from the first clock signal at the second clock input terminal CLK2 to the second clock signal at the first clock input terminal CLK 1.
In the present embodiment, the present invention switches the clock signal output by the present invention from the first clock signal at the first clock input terminal CLK1 to the second clock signal at the second clock input terminal CLK2 in response to the signal at the switching signal input terminal SEL switching from the low level to the high level, and switches the clock signal output by the present invention from the first clock signal at the second clock input terminal CLK2 to the second clock signal at the first clock input terminal CLK1 in response to the signal at the switching signal input terminal SEL switching from the high level to the low level. In one embodiment, the switching of the clock signal output by the present invention from the first clock signal at the first clock input terminal CLK1 to the second clock signal at the second clock input terminal CLK2 may be started when the signal at the switching signal input terminal SEL transitions from a high level to a low level, and the switching of the clock signal output by the present invention from the first clock signal at the second clock input terminal CLK2 to the second clock signal at the first clock input terminal CLK1 may be started when the signal at the switching signal input terminal SEL transitions from a low level to a high level.
Specifically, as shown in fig. 3, the control unit 1 includes a first AND gate AND1, a second AND gate AND2, AND a first inverter INV1, the switching signal input SEL is electrically connected to the input terminal of the first inverter INV1 AND the first input terminal of the second AND gate AND2, respectively, the output terminal of the first inverter INV1 is electrically connected to the first input terminal of the first AND gate AND1, the second input terminal of the first AND gate AND1 is electrically connected to the clock first enable signal output terminal of the second feedback unit 3, the second input terminal of the second AND gate AND2 is electrically connected to the clock second enable signal output terminal of the first feedback unit 2, the output terminal of the first AND gate 1 is electrically connected to the first feedback unit 1, AND the output terminal of the second AND gate AND2 is electrically connected to the second feedback unit 3.
The first feedback unit 2 includes a first negative edge flip-flop D1, a first positive edge flip-flop D2, and a first NOR gate NOR1, a clock terminal of the first negative edge flip-flop D1 and a clock terminal of the first positive edge flip-flop D2 are electrically connected to the first clock input terminal CLK1, respectively, an input terminal of the first negative edge flip-flop D1 is electrically connected to the control unit 1, and receives a first stop signal and a clock first start signal transmitted from the control unit 1, an output terminal of the first negative edge flip-flop D1 is electrically connected to an input terminal of the first positive edge flip-flop D2, a first input terminal of the first NOR gate NOR1, and the clock selection unit 4, respectively, an output terminal of the first positive edge flip-flop D2 is electrically connected to a second input terminal of the first NOR gate NOR1, an output terminal of the first NOR gate 1 is electrically connected to the control unit 1, and transmits a clock second start signal to the control unit 1.
The second feedback unit 3 includes a second negative edge flip-flop D3, a second positive edge flip-flop D4 and a second NOR gate NOR2, a clock terminal of the second negative edge flip-flop D3 and a clock terminal of the second positive edge flip-flop D4 are electrically connected to the second clock input terminal CLK2, respectively, an input terminal of the second negative edge flip-flop D3 is electrically connected to the control unit 1, and receives a second stop signal and a second clock start signal transmitted from the control unit 1, an output terminal of the second negative edge flip-flop D3 is electrically connected to an input terminal of the second positive edge flip-flop D4, a first input terminal of the second NOR gate NOR2 and the clock selection unit 4, an output terminal of the second positive edge flip-flop D4 is electrically connected to a second input terminal of the second NOR gate NOR2, an output terminal of the second NOR gate 2 is electrically connected to the control unit 1, and transmits a clock start signal to the control unit 1.
The clock selection unit 4 comprises a third AND gate AND3, a fourth AND gate AND4 AND a first OR gate OR1, a first input terminal of the third AND gate AND3 is electrically connected to the first clock input terminal CLK1, a second input terminal of the third AND gate AND3 is electrically connected to the first feedback unit 2, AND receives the first clock stop signal AND the first clock start signal sent by the first feedback unit 2, an output terminal of the third AND gate AND3 is electrically connected to a first input terminal of the first OR gate OR1, a first input terminal of the fourth AND gate AND3 is electrically connected to the second clock input terminal CLK2, a second input terminal of the fourth AND gate AND4 is electrically connected to the second feedback unit 3, AND receives the second clock stop signal AND the second clock start signal sent by the second feedback unit 3, an output terminal of the fourth AND gate 4 is electrically connected to a second input terminal of the first OR gate OR1, AND an output terminal of the second OR gate 1 outputs the clock signal.
In this embodiment, the first negative edge flip-flop D1, the first positive edge flip-flop D2, the second negative edge flip-flop D3, and the second positive edge flip-flop D4 are all D flip-flops.
The switching flow of the circuit in fig. 3 is as follows:
the clock signal output by the output of the second OR gate OR1 switches from the clock signal at the second clock input CLK2 to the clock signal at the first clock output CLK1 as follows:
before the selection signal of the switching signal input terminal SEL changes, the output terminal of the second OR gate OR1 outputs the clock signal of the second clock input terminal CLK2, at this time, the second feedback signal output by the second NOR gate NOR2 is in a low level state, AND acts on the first negative edge register D1 together with the selection signal, so that the first negative edge register D1 inputs a low level signal to the third AND gate AND3, AND the first OR gate OR1 does not output the clock signal of the first clock output terminal CLK 1;
the selection signal of the switching signal input terminal SEL changes from high level to low level, acts on the second AND gate AND2, sends out a second stop signal of low level, AND after the synchronization of the second negative edge flip-flop D3, the second stop signal becomes a second clock stop signal AND is input to the fourth AND gate AND4, so that the first OR gate OR1 does not output the clock signal of the second clock output terminal CLK2, AND at this time, a half cycle of the clock signal of the second clock input terminal CLK2 is passed;
the second positive edge register D4 resynchronizes the control signal at the positive edge of the clock signal at the second clock input terminal CLK2, outputs a control signal that is synchronized with the second negative edge register AND then the second clock stop signal is nor-asserted, AND sends a second clock control feedback signal to the first AND gate AND1 at the next positive edge of the clock signal at the second clock input terminal CLK 2.
The second clock control feedback signal is in a high level state, AND acts on the first AND gate AND1 together with the selection signal at the switching signal input terminal SEL, the first AND gate AND1 inputs a high level fourth start signal to the first negative edge flip-flop, AND after the fourth start signal is synchronized by the first negative edge flip-flop D1, the fourth start signal is transmitted to the third AND gate AND3 at the negative edge of the clock signal at the first clock input terminal CLK1, so that the first OR gate OR1 starts to output the clock signal at the first clock input terminal CLK 1.
The waveform diagram of the clock signal output at the output of the second OR gate OR1 switched from the clock signal at the first clock input terminal CLK1 to the clock signal at the second clock output terminal CLK2 of the present invention is shown in fig. 4, where CLK1 is the clock waveform at the first clock input terminal CLK1, CLK2 is the clock waveform at the second clock input terminal CLK2, SEL is the waveform at the switching signal input terminal SEL, the clock-negative edge output is the waveform of the output signal at the output of the first negative edge flip-flop, the clock-positive edge output is the waveform of the output signal at the output of the first positive edge flip-flop, the clock-first control feedback is the waveform of the output signal at the output of the first NOR gate NOR1, the clock-negative edge output is the waveform of the output signal at the output of the second negative voltage swing flip-flop D3, and CKOUT is the waveform of the clock signal output at the output of the first OR gate OR 1.
In fig. 4, after SEL changes from low to high, when the first high level of CLK1 changes to the low level at the time of the dotted line corresponding to 1, the first negative edge flip-flop D1 outputs the first clock stop signal of low level, the output terminal of the first OR gate OR1 does not output the clock signal at the first clock input terminal CLK1, AND when the first low level of CLK1 changes to the high level at the time of the dotted line corresponding to 2, the first positive edge register D2 inputs the first start signal of high level to the second AND gate AND2, the first start signal of high level changes to the low level at the time of the dotted line corresponding to 3 at the second clock input terminal CLK2 AND is input to the fourth AND gate 4, AND at this time, the first OR gate OR1 starts to output the clock signal at the second clock input terminal CLK 2. As can be seen from fig. 4, the switching of the clock signal by using the present invention can be completed within one cycle of the clock signal, and the cycle of the current clock signal is complete during the switching without generating glitch.
The clock signal output by the output of the second OR gate OR1 switches from the clock signal at the first clock input CLK1 to the clock signal at the second clock output CLK2 as follows:
before the selection signal of the switching signal input SEL changes, the output terminal of the second OR gate OR1 outputs the clock signal at the first clock input terminal CLK1, at this time, the second feedback signal output by the first NOR gate NOR1 is in a low state, AND acts on the second negative edge register D3 in conjunction with the selection signal, so that the second negative edge register D3 inputs a low signal to the fourth AND gate AND4, AND the first OR gate OR1 does not output the clock signal at the second clock output terminal CLK 2.
The selection signal of the switching signal input terminal SEL changes from low level to high level, AND acts on the first AND gate AND1 to send out the first stop signal, after the synchronization by the first negative edge flip-flop D1DE, the first stop signal becomes the first clock stop signal AND is input to the third AND gate AND3, so that the first OR gate OR1 does not output the clock signal of the first clock output terminal CLK1, AND at this time, a half cycle of the clock signal of the first clock input terminal CLK1 is passed.
The first positive edge register D2 resynchronizes the control signal at the positive edge of the clock signal at the first clock input terminal CLK1, outputs a control signal that is synchronized with the first negative edge register AND then the first clock stop signal is nor-inverted, AND sends a first clock control feedback signal to the second AND gate AND2 at the next positive edge of the clock signal at the first clock input terminal CLK 1.
The first clock control feedback signal is in a high-level state, AND acts on the second AND gate AND2 together with the selection signal at the switching signal input terminal SEL, the second AND gate AND2 inputs a high-level second start signal to the second negative edge flip-flop D3, AND the second start signal is synchronized by the second negative edge flip-flop D3 AND then transmitted to the fourth AND gate AND4 at the negative edge of the clock signal at the second clock input terminal CLK2, so that the first OR gate OR1 starts to output the clock signal at the second clock input terminal CLK 2.
Specifically, in the present embodiment, since the output terminal of the first AND gate AND1 is electrically connected to the input terminal of the first negative edge flip-flop D1, AND the output terminal of the first negative edge flip-flop D1 is electrically connected to the input terminal of the first positive edge flip-flop D2, after the signal at the switching signal input SEL changes from the first state to the second state, the first level transition time of the clock signal at the first clock input CLK1 of the first feedback unit 2 refers to the time when the clock signal at the first clock input CLK1 changes from the high level to the low level, AND the second level transition time of the clock signal at the first clock input CLK1 of the first feedback unit 2 refers to the time when the clock signal at the first clock input CLK1 changes from the low level to the high level; in one embodiment, when the positions of the first negative edge flip-flop D1 and the first positive edge flip-flop D2 in the first feedback unit 2 are interchanged, the first level transition time in this paragraph may be a time when the low level transitions to the high level, and the second level transition time is a time when the high level transitions to the low level, and the position of the second negative edge flip-flop D3 in the second matching unit also needs to be interchanged with the position of the second positive edge flip-flop D4.
Specifically, in this embodiment, after the second feedback unit 3 receives the second start signal, the first level transition time of the clock signal at the second clock input terminal CLK2 of the second feedback unit 3 refers to the time when the clock signal at the second clock input terminal transitions from high level to low level, AND at this time, the output terminal of the first AND gate AND1 is electrically connected to the input terminal of the first negative edge flip-flop D1; in one embodiment, the first level transition time in the content of this paragraph is the time when the low level transitions to the high level, and the positions of the first negative edge flip-flop D1 and the first positive edge flip-flop D2 in the first feedback unit 2 need to be interchanged.
In summary, in practical use of the present invention, when a clock needs to be switched, the first feedback unit 1 or the second feedback unit 2 can stop sending the current clock signal and enable the present invention to start to prepare for sending the clock signal to be switched at two consecutive level switching moments in the current period of the clock signal, and when the clock signal to be switched needs to be sent, the level switching moment of the clock signal to be switched is taken as a sending starting point, thereby ensuring the integrity of the current sent clock signal when the clock is switched without a glitch, and realizing the clock switching in one clock period.
In light of the foregoing, it is to be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims (7)

1. A clock switching circuit is characterized by comprising a first clock input end, a second clock input end, a switching signal input end, a control unit, a first feedback unit, a second feedback unit and a clock selection unit;
the first clock input end is electrically connected with the first feedback unit and the clock selection unit respectively, and the second clock input end is electrically connected with the second feedback unit and the clock selection unit respectively; the switching signal input end is electrically connected with the control unit;
the control unit sends a first stop signal to the first feedback unit when the signal at the switching signal input end is changed from a first state to a second state; after the signal at the switching signal input end is changed from the first state to the second state, the first feedback unit sends a first clock stop signal to the clock selection unit at the first level transition moment of the clock signal at the first clock input end, and the first feedback unit sends a first start signal to the control unit at the second level transition moment of the clock signal at the first clock input end; the clock selection unit stops outputting clock signals after receiving the first clock stop signal; the control unit sends a second starting signal to the second feedback unit after receiving the first starting signal; after the second feedback unit receives the second start signal, the second feedback unit sends a second clock start signal to the clock selection unit at a first level transition moment of the clock signal at the second clock input end, and the clock selection unit starts to output the clock signal at the second clock input end after receiving the second clock start signal;
the control unit sends a second stop signal to the second feedback unit when the signal at the switching signal input end is changed from the second state to the first state; after the signal at the switching signal input end is changed from the second state to the first state, the second feedback unit sends a second clock stop signal to the clock selection unit at the first level transition moment of the clock signal at the second clock input end, and the second feedback unit sends a third start signal to the control unit at the second level transition moment of the clock signal at the second clock input end; the clock selection unit stops outputting the clock signal after receiving the second clock stop signal; the control unit sends a fourth start signal to the first feedback unit after receiving the third start signal, after the first feedback unit receives the fourth start signal, the first feedback unit sends a clock start signal to the clock selection unit at a first level transition moment of a clock signal at the first clock input end, and the clock selection unit starts to output the clock signal at the first clock input end after receiving the clock start signal.
2. The clock switching circuit of claim 1, wherein the first state is a low state and the second state is a high state.
3. The clock switching circuit according to claim 1, wherein after the signal at the switching signal input terminal changes from the first state to the second state, the first level transition time of the clock signal at the first clock input terminal of the first feedback unit is a time when the clock signal at the first clock input terminal changes from a high level to a low level, and the second level transition time of the clock signal at the first clock input terminal of the first feedback unit is a time when the clock signal at the first clock input terminal changes from a low level to a high level; after the second feedback unit receives the second start signal, the first level transition time of the clock signal at the second clock input end of the second feedback unit is the time when the clock signal at the second clock input end is transitioned from the high level to the low level;
after the signal at the switching signal input end is changed from the second state to the first state, the first level transition time of the clock signal at the second clock input end of the second feedback unit refers to the time when the clock signal at the second clock input end is changed from the high level to the low level, and the second level transition time of the clock signal at the second clock input end of the second feedback unit refers to the time when the clock signal at the second clock input end is changed from the low level to the high level; after the first feedback unit receives the fourth start signal, the first level transition time of the clock signal at the first clock input end of the first feedback unit refers to the time when the clock signal at the first clock input end transitions from a high level to a low level.
4. The clock switching circuit according to claim 1, wherein the control unit comprises a first and gate, a second and gate and a first inverter, the switching signal input terminal is electrically connected to the input terminal of the first inverter and the first input terminal of the second and gate, respectively, the output terminal of the first inverter is electrically connected to the first input terminal of the first and gate, the second input terminal of the first and gate is electrically connected to the clock first enable signal output terminal of the second feedback unit, the second input terminal of the second and gate is electrically connected to the clock second enable signal output terminal of the first feedback unit, the output terminal of the first and gate is electrically connected to the first feedback unit, and the output terminal of the second and gate is electrically connected to the second feedback unit.
5. The clock switching circuit according to claim 1, wherein the first feedback unit comprises a first negative edge flip-flop, a first positive edge flip-flop and a first nor gate, a clock terminal of the first negative edge flip-flop and a clock terminal of the first positive edge flip-flop are electrically connected to the first clock input terminal respectively, an input terminal of the first negative edge flip-flop is electrically connected to the control unit, the first negative edge flip-flop receives a first stop signal and a clock start signal sent by the control unit, an output terminal of the first negative edge flip-flop is electrically connected to an input terminal of the first positive edge flip-flop, a first input terminal of the first nor gate and the clock selection unit respectively, an output terminal of the first positive edge flip-flop is electrically connected to a second input terminal of the first nor gate, and an output terminal of the first nor gate is electrically connected to the control unit, and sending a clock two starting signal to the control unit.
6. The clock switching circuit according to claim 1, wherein the second feedback unit comprises a second negative edge flip-flop, a second positive edge flip-flop and a second nor gate, a clock terminal of the second negative edge flip-flop and a clock terminal of the second positive edge flip-flop are electrically connected to the second clock input terminal respectively, an input terminal of the second negative edge flip-flop is electrically connected to the control unit, the second negative edge flip-flop receives the second stop signal and the second clock start signal sent by the control unit, an output terminal of the second negative edge flip-flop is electrically connected to an input terminal of the second positive edge flip-flop, a first input terminal of the second nor gate and the clock selection unit respectively, an output terminal of the second positive edge flip-flop is electrically connected to a second input terminal of the second nor gate, and an output terminal of the second nor gate is electrically connected to the control unit, and sending a clock start signal to the control unit.
7. The clock switching circuit according to claim 1, wherein the clock selecting unit comprises a third and gate, a fourth and gate and a first or gate, a first input terminal of the third and gate is electrically connected to the first clock input terminal, a second input terminal of the third and gate is electrically connected to the first feedback unit, and receives the first clock stop signal and the first clock start signal sent by the first feedback unit, an output terminal of the third and gate is electrically connected to the first input terminal of the first or gate, a first input terminal of the fourth and gate is electrically connected to the second clock input terminal, a second input terminal of the fourth and gate is electrically connected to the second feedback unit, and receives the second clock stop signal and the second clock start signal sent by the second feedback unit, and an output terminal of the fourth and gate is electrically connected to the second input terminal of the first or gate, the output terminal of the second or gate outputs a clock signal.
CN202111320632.2A 2021-11-09 2021-11-09 Clock switching circuit Pending CN114039581A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169814A (en) * 1987-01-07 1988-07-13 Tokyo Electric Co Ltd Frequency switching circuit
TW480821B (en) * 2001-05-29 2002-03-21 Realtek Semiconductor Corp Multiphase switching circuit with bidirectional switch and without false signal
US20040012435A1 (en) * 2002-07-16 2004-01-22 Tetsumasa Meguro Clock switching circuit
US6873183B1 (en) * 2003-05-12 2005-03-29 Xilinx, Inc. Method and circuit for glitchless clock control

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169814A (en) * 1987-01-07 1988-07-13 Tokyo Electric Co Ltd Frequency switching circuit
TW480821B (en) * 2001-05-29 2002-03-21 Realtek Semiconductor Corp Multiphase switching circuit with bidirectional switch and without false signal
US20040012435A1 (en) * 2002-07-16 2004-01-22 Tetsumasa Meguro Clock switching circuit
US6873183B1 (en) * 2003-05-12 2005-03-29 Xilinx, Inc. Method and circuit for glitchless clock control

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