CN114038388B - Output control circuit of source electrode driving chip and display panel - Google Patents
Output control circuit of source electrode driving chip and display panel Download PDFInfo
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- CN114038388B CN114038388B CN202111528756.XA CN202111528756A CN114038388B CN 114038388 B CN114038388 B CN 114038388B CN 202111528756 A CN202111528756 A CN 202111528756A CN 114038388 B CN114038388 B CN 114038388B
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- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
- 239000002096 quantum dot Substances 0.000 claims description 3
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present disclosure relates to an output control circuit for a source driving chip in a display panel, the output control circuit including: the output buffer circuit is electrically connected with the clock circuit; the clock circuit generates at least one path of clock signal through oscillation; the output buffer circuit receives the voltage signal and the clock signal and outputs the voltage signal according to the clock signal to drive the pixel unit corresponding to the voltage signal, wherein the voltage signal is generated by the source drive chip according to the input image digital data. The output control circuit and the display panel provided by the disclosure independently generate at least one path of clock signal through the clock circuit to control the output buffer circuit to output and drive the voltage signal of each pixel unit, so that the problem of water ripple or color cast and other phenomena generated due to the fact that the distances between the pixel units and the source electrode driving chip are different is solved, the probability of abnormal pictures of the display panel is further reduced, and the display quality of the display panel is improved.
Description
Technical Field
The disclosure relates to the field of display panels, and in particular, to an output control circuit of a source driving chip and a display panel.
Background
With the continuous development of science and technology, further demands are also put on the display quality of the display panel. The conventional display panel generally uses a gate driving chip and a source driving chip to commonly drive a plurality of pixel units. Specifically, after the gate driving chip supplies a scanning signal to the display panel through the gate scanning line to turn on the pixel unit switch, the source driving chip supplies a data signal to the display panel through the data line perpendicular to the gate scanning line to charge the capacitor inside the corresponding pixel unit. However, since the data line has a resistive-capacitive load, the more the resistive-capacitive load of the data line is greater the farther the data line is from the source driving chip, the less the voltage is received by the pixel unit the farther the data line is from the source driving chip, and the shorter the charging period is. Therefore, the pixel units far away from the source electrode driving chip have the phenomenon of insufficient charging, and the phenomenon of insufficient charging of the pixel units is along with the increase of the refresh rate and the screen size of the display panel, so that the charging difference among all the pixel units in the display panel is more obvious, and therefore, the phenomenon of moire or color shift and the like can be generated when the display panel displays pictures, the pictures of the display panel are abnormal, and the display quality of the display panel is seriously affected.
Accordingly, there is a need in the art for a display panel that reduces the charging shortage of the remote pixel units and the short charging time.
Disclosure of Invention
In view of this, the disclosure provides an output control circuit of a source driving chip and a display panel.
According to an aspect of the present disclosure, there is provided an output control circuit of a source driving chip, the output control circuit including: the output buffer circuit is electrically connected with the clock circuit; the clock circuit generates at least one path of clock signal through oscillation; the output buffer circuit receives the voltage signal and the clock signal, and outputs the voltage signal according to the clock signal to drive the pixel unit corresponding to the voltage signal, wherein the voltage signal is generated by the source drive chip according to the input image digital data.
Further, the clock circuit includes: the clock oscillation circuit and the compensation generation circuit are electrically connected with the clock oscillation circuit; the compensation generating circuit receives the oscillation clock signal generated by the clock oscillating circuit and generates the clock signal by adjusting the duty ratio of each pulse in the oscillation clock signal.
Further, the clock oscillation circuit further includes: an oscillator and a clock generator electrically connected with the oscillator; the clock generator receives an oscillation signal generated by the oscillator, adjusts the frequency of the oscillation signal according to a frequency lookup table, and generates the oscillation clock signal; the frequency lookup table comprises a corresponding relation between signal frequency and voltage loss of the display panel; the voltage loss of the display panel is inversely related to the ratio of the voltage signal output by the output buffer circuit to the voltage signal obtained by the corresponding pixel unit.
Further, the ratio of the voltage signal output by the output buffer circuit to the voltage signal obtained by the corresponding pixel unit is positively correlated with the resistance value of the data line used for transmitting the voltage signal in the source electrode driving chip.
Further, the ratio of the voltage signal output by the output buffer circuit to the voltage signal input to the corresponding pixel unit is positively correlated with the resistance of the glass substrate of the display panel.
Further, the compensation control circuit includes: a PWM generator; the signal input end of the PWM generator receives the oscillation clock signal generated by the clock generator, adjusts the duty ratio of pulses in the oscillation clock signal according to a compensation lookup table, determines the number of the clock signals and generates at least one path of clock signals; the compensation lookup table is a corresponding relation between the output time of the voltage signal and a trigger edge of the clock signal, and the trigger edge is used for triggering the output buffer circuit to output the voltage signal.
Further, the clock circuit outputs a preset number of clock signals in parallel, and the output buffer circuit outputs voltage signals for driving corresponding pixel units according to the first periodic pulse of the clock signals.
Further, the clock circuit outputs two paths of parallel clock signals, and the output buffer circuit outputs two paths of voltage signals at the same time according to a first periodic pulse of the clock signals so as to drive the first pixel unit and the second pixel unit at the same time; the first pixel unit and the second pixel unit are pixel units positioned at two ends of the same grid scanning line.
Further, the interval between the trigger edges of at least two adjacent pulses in the clock signal is not equal to the interval between the trigger edges of other adjacent pulses.
According to another aspect of the present disclosure, there is provided a display panel including the output control circuit of any one of the preceding.
Further, the display panel is one of a liquid crystal display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel and an organic light emitting diode display panel.
The output control circuit and the display panel provided by the disclosure independently generate at least one path of clock signal through the clock circuit to control the output buffer circuit to output and drive the voltage signal of each pixel unit, so that the problem of water ripple or color cast and other phenomena generated due to the fact that the distances between the pixel units and the source electrode driving chip are different is solved, the probability of abnormal pictures of the display panel is further reduced, and the display quality of the display panel is improved. In addition, the output control circuit in the display panel provided by the disclosure can independently generate the clock signal for controlling the output buffer circuit to output the voltage signal, so that compared with a clock circuit which needs to generate the clock signal according to the system clock of the display panel, the clock signal generated by the output control circuit and the time of the trigger edge of each pulse are not limited by the clock signal in the display panel, the clock signal can be flexibly generated, and the purposes of generating the clock signal more in accordance with the actual application requirement, freely controlling the output buffer circuit to output the voltage signal and driving the corresponding pixel unit are realized.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic diagram of a display panel in the prior art
Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the disclosure.
Fig. 3 is a circuit configuration diagram of an output control circuit according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of output time of a voltage signal and coordinates of a corresponding pixel unit according to an embodiment of the disclosure.
Fig. 5 is a schematic diagram of an output timing of another voltage signal and a coordinate of a corresponding pixel unit according to an embodiment of the disclosure.
Fig. 6 is a schematic diagram of an output timing of another voltage signal and a coordinate of a corresponding pixel unit according to an embodiment of the disclosure.
Fig. 7 is a schematic diagram of an output timing of another voltage signal and a coordinate of a corresponding pixel unit according to an embodiment of the disclosure.
Fig. 8 is a schematic diagram of an output timing of another voltage signal and a coordinate of a corresponding pixel unit according to an embodiment of the disclosure.
Fig. 9 is a schematic diagram of an output timing of another voltage signal and a coordinate of a corresponding pixel unit according to an embodiment of the disclosure.
Fig. 10 is a schematic diagram of an output timing of another voltage signal and a coordinate of a corresponding pixel unit according to an embodiment of the disclosure.
Fig. 11 is a circuit diagram of a source driving chip according to an embodiment of the disclosure.
Fig. 12 is a circuit diagram of another source driver chip according to an embodiment of the disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
Referring to fig. 1, in the prior art, each pixel unit of the display panel is commonly driven by a source driving chip 400 and a gate driving chip 500, which is equivalent to that one pixel unit is driven by transmitting a scanning signal to a corresponding gate scanning line 510 through the gate driving chip, so as to turn on a TFT switch in the pixel unit, and the source driving chip provides a voltage signal to the display panel through a data line 410 perpendicular to the gate scanning line 510, so as to charge a capacitor inside the corresponding pixel unit. Although the pixel units in the display panel are generally uniformly arranged inside the panel, the distance between each pixel unit and the source driving chip is not the same. In this way, when the source driving chip transmits the voltage signals to the plurality of pixel units at the same time, the time when the voltage signals are received by the plurality of pixel units is different, and compared with the duration of the voltage signals received by the pixel units close to the source driving chip, the duration of the voltage signals received by the pixel units far away from the source driving chip is shorter.
Meanwhile, since the source driving chip 400 sends voltage signals to each pixel unit through the data line, and the data line 410 has a resistive-capacitive load, the resistive-capacitive load of the data line 410 corresponding to the pixel unit far from the source driving chip is large, so that the loss of the voltage signals received by the pixel unit in the transmission process is large, and the resistive-capacitive load of the data line 410 corresponding to the pixel unit near to the source driving chip 400 is small, so that the loss of the voltage signals received by the pixel unit in the transmission process is small.
In summary, in the case where the source driving chip 400 simultaneously transmits a voltage signal to each pixel cell, the pixel cell distant from the source driving chip 400 is much smaller in duration of charging or the voltage signal received than the pixel cell close to the source driving chip 400. In this case, since the charging time of each pixel unit is not uniform, water ripple or color shift may occur when the display panel displays a picture, which may cause abnormal picture of the display panel and seriously affect the display quality of the display panel.
Therefore, it is a strong technical need to design a display panel capable of reducing the phenomena of insufficient charging and short charging time of the remote pixel unit.
In view of the above-described practical technical needs, referring to fig. 2-10, the present disclosure provides an output control circuit for a source driving chip in a display panel, the output control circuit comprising: the clock circuit 1 and the output buffer circuit 2, wherein the clock circuit 1 is electrically connected with the output buffer circuit 2.
Further, the clock circuit 1 generates at least one clock signal by oscillation. The output buffer circuit 2 receives the voltage signal and the clock signal, and outputs the voltage signal according to the clock signal to drive the pixel unit corresponding to the voltage signal. The voltage signal is illustratively a voltage signal generated by the source driver chip from the input image digital data.
The output control circuit provided by the disclosure can independently generate at least one clock signal through the clock circuit to control the output buffer circuit to output the voltage signal for driving each pixel unit. The method can control the output buffer circuit to output voltage signals to each pixel unit, further solves the problems that the charging conditions of the pixel units in the same grid scanning line are different (namely, the charging time is different from the voltage of the obtained voltage signals) due to the fact that the distances between the pixel units and the source electrode driving chip are different, and further generates phenomena such as moire or color shift, so that the probability of abnormal images of the display panel is reduced, and the display quality of the display panel is improved. Further, referring to fig. 12, the clock circuit 1 in fig. 12 obtains a system clock signal in the display panel through the input interface 4 and performs a corresponding process thereon, generating a clock signal to control the output buffer circuit 2 to output a voltage signal. Compared with the clock circuit in fig. 12, the clock circuit in the output control circuit provided by the disclosure can independently generate the clock signal for controlling the output buffer circuit to output the voltage signal, so that the clock signal generated by the clock circuit in the output control circuit provided by the disclosure is not limited by the clock signal in the display panel (such as signal frequency, trigger edge position, etc.), the problem that the clock circuit cannot flexibly generate the clock signal is solved, and the purposes of generating the clock signal more in line with the actual application requirement, freely controlling the output buffer circuit to output the voltage signal and driving the corresponding pixel unit are realized.
In some embodiments of the present disclosure, the clock circuit 1 outputs a preset number of clock signals in parallel, and the output buffer circuit outputs a preset number of voltage signals simultaneously according to a first period pulse of the clock signals for driving a preset number of pixel units simultaneously.
Further, the preset number of clock signals output by the clock circuit 1 may be determined according to the display requirement of the actual display panel or the circuit structure inside the display panel. Illustratively, one clock signal may trigger the output buffer circuit 2 to output one voltage signal through one edge (referred to as a trigger edge, for example, may be a rising edge of the clock signal) thereof to drive one pixel unit. The multiple clock signals outputted in parallel can trigger the output buffer circuit 2 to output multiple voltage signals in parallel through one edge of the multiple clock signals so as to drive a plurality of corresponding pixel units in parallel.
For each clock signal, each edge (e.g., each rising edge) of the clock signal may trigger the output buffer circuit 2 to output a voltage signal to drive one pixel unit, that is, through a plurality of edges (e.g., a plurality of rising edges) of the clock signal, the output buffer circuit 2 may be sequentially triggered to output a plurality of voltage signals to drive different pixel units. The multiple paths of parallel output clock signals can respectively drive each pixel unit in a group of corresponding pixel units in sequence.
For example, since the pixel units located at both ends of the same gate scan line 510 are two pixel units farthest from the source driving chip 400 in the conventional display panel, the pixel units located at both ends of the same gate scan line 510 may be preferentially driven in order to ensure the picture quality of the display panel, which corresponds to transmitting voltage signals to the pixel units in the display panel according to the descending order of the distances between the pixel units and the source driving chip 400. Based on the above description, the preset number of clock signals may be set to 2, that is, the clock circuit 1 outputs two parallel clock signals, and the output buffer circuit 2 outputs two voltage signals simultaneously according to the first period pulse of the clock signal for driving the first pixel unit and the second pixel unit simultaneously (see the pixel unit X1 and the pixel unit X5 in fig. 2). The first pixel unit and the second pixel unit are pixel units positioned at two ends of the same grid scanning line.
The control circuit provided by the disclosure can generate two paths of parallel clock signals through oscillation of the clock circuit to control the output buffer circuit to output two paths of voltage signals simultaneously, so that the purpose of driving pixel units positioned at two ends of the same grid scanning line simultaneously is achieved. Because the output buffer circuit is used for driving the pixel units positioned at two ends of the same grid scanning line, namely, the two pixel units farthest from the source electrode driving chip according to the first periodic pulse of the clock signal, the display panel adopting the control circuit provided by the disclosure can adjust the charging time of the pixel units positioned at two ends of the same grid scanning line according to the distance between the pixel units and the source electrode driving chip, namely, the charging time of the pixel units far from the source electrode driving chip is long, and the charging time of the pixel units near to the source electrode driving chip is short, thereby ensuring the equal electric quantity of each pixel unit in the same grid scanning line, further solving the problem of water ripple or color cast and other phenomena generated due to the unequal distance between the pixel units and the source electrode driving chip, further reducing the abnormal probability of the picture of the display panel and improving the display quality of the display panel.
Referring to fig. 3, in some embodiments of the present disclosure, a clock circuit 1 includes: a clock oscillation circuit 11, and a compensation generation circuit 12 electrically connected to the clock oscillation circuit.
Further, the compensation generating circuit 12 receives the oscillation clock signal generated by the clock oscillating circuit 11, and generates a clock signal by adjusting the duty ratio of each pulse in the oscillation clock signal.
Further, the clock oscillation circuit 11 includes: an oscillator 111, and a clock generator 112 electrically connected to the oscillator. The clock generator 112 receives the oscillation signal generated by the oscillator 111, and adjusts the frequency of the oscillation signal according to the frequency lookup table 200, thereby generating the oscillation clock signal.
Optionally, the frequency lookup table 200 includes a correspondence between signal frequency and voltage loss. The voltage loss is inversely related to the ratio of the voltage signal output by the output buffer circuit to the voltage signal obtained by the corresponding pixel unit. The correspondence relationship between the signal frequency and the voltage loss in the frequency lookup table 200 is related to the type of display panel, that is, the frequency of the oscillation clock signal is the same in the same display panel.
In the first display panel, the voltage signal output by the output buffer circuit 2 is 5 volts, the voltage signal obtained by the third pixel unit is 3 volts, and in the second display panel, the voltage signal obtained by the third pixel unit at the same position is 4 volts, the voltage loss of the first display panel is greater than that of the second display panel.
Illustratively, the ratio of the voltage signal output by the output buffer circuit 2 to the voltage signal obtained by the corresponding pixel unit is positively correlated with the resistance value of the data line for transmitting the voltage signal in the source driving chip 400. The voltage signal output by the output buffer circuit 2 is transmitted to the corresponding pixel unit through the data line 410 of the source driving chip 400, and the larger the resistance value of the data line 410 is, the larger the resistance to the voltage signal is, which finally results in the smaller the voltage signal received by the pixel unit, and further results in the larger the ratio of the voltage signal output by the output buffer circuit 2 to the voltage signal obtained by the corresponding pixel unit.
Illustratively, the ratio of the voltage signal output by the output buffer circuit 2 to the voltage signal input to the corresponding pixel unit is positively correlated with the resistance of the glass substrate of the display panel. Since the data lines 410 of the source driving chip 400 are formed on the glass substrate inside the display panel, the resistance of the data lines 410 is equal to that of the glass substrate. For the same reason, in different display panels, the larger the resistance value of the glass substrate of the display panel, the larger the resistance force applied to the voltage signal output by the output buffer circuit 2 in the transmission process, the smaller the voltage signal received by the pixel unit is finally caused, and the larger the ratio of the voltage signal output by the output buffer circuit 2 to the voltage signal obtained by the corresponding pixel unit is caused.
The ratio of the voltage signal output by the output buffer circuit 2 to the voltage signal obtained by the corresponding pixel unit is related to the degree of density of the pixel units arranged on the display panel, that is, the voltage loss is large in the display panel with sparse pixel unit arrangement, whereas the voltage loss is small in the display panel with dense pixel unit arrangement. For example: in the third display panel and the fourth display panel, the resistances of the glass substrates are equal, and the pixel units are uniformly distributed, if the number of the pixel units in the third display panel is the same as the number of the pixel units in the fourth display panel, and the size of the third display panel is larger than that of the fourth display panel, the arrangement of the pixel units in the third display panel is sparse, and the distance between the pixel units in the third display panel and the source driving chip 400 is further than that of the fourth display panel. When the pixel units at the same position (i.e., the pixel units in the same row and the same column) in the third display panel and the fourth display panel are driven by the voltage signals with the same voltage, the voltage of the voltage signals obtained by the pixel units in the third display panel is smaller than the voltage of the voltage signals obtained by the pixel units in the fourth display panel (i.e., the voltage loss of the voltage signals of the third display panel is larger).
Alternatively, the signal frequency is inversely related to the voltage loss in the frequency lookup table 200, i.e., the signal frequency decreases with increasing voltage loss. Also, taking the first display panel and the second display panel as examples, since the voltage loss of the first display panel is greater than that of the second display panel, the frequency of the oscillating clock signal output by the clock generator 112 in the first display panel is smaller than that of the oscillating clock signal output by the clock generator 112 in the second display panel. For another example, in the third display panel and the fourth display panel in the above description, since the pixel units of the third display panel are arranged more sparsely, the voltage loss of the third display panel is greater than the voltage loss of the fourth display panel, so that the frequency of the oscillation clock signal output by the clock generator 112 in the third display panel is smaller than the frequency of the oscillation clock signal output by the clock generator 112 in the fourth display panel.
Referring to fig. 3, the compensation control circuit includes: a PWM generator 121. The signal input of the PWM generator 121 receives the oscillating clock signal generated by the clock generator 112, adjusts the duty ratio of the pulses in the oscillating clock signal according to the compensation lookup table 300, determines the number of clock signals, and generates at least one clock signal. The compensation lookup table 300 is a correspondence between an output time of the voltage signal and a trigger edge of the clock signal, where the trigger edge is used to trigger the output buffer circuit to output the voltage signal, such as a rising edge.
Illustratively, the PWM generator 121 is controlled to adjust the duty cycle of the oscillating clock signal to generate the clock signal by looking up the corresponding clock signal from the compensation look-up table according to the expected output sequence of the voltage signal. For example, if the expected output sequence of the voltage signals is shown in fig. 4, that is, the pixel unit X1 and the pixel unit X5 are driven at the time T0, and the pixel unit X2 and the pixel unit X4 are driven at the time T1, and the pixel unit X3 is driven at the time T2, the PWM generator 121 is controlled to generate two clock signals, and the first trigger edge (rising edge) of the two clock signals is located at the time T0, and the output buffer circuit outputs two voltage signals according to the first trigger edge of the two clock signals at the time T0 to drive the pixel unit X1 and the pixel unit X5. Similarly, when the second trigger edge (rising edge) of the clock signal is located at time T1, the output buffer circuit outputs two voltage signals according to the second trigger edge of the two clock signals at time T1 to drive the pixel unit X2 and the pixel unit X4. Similarly, when the third trigger edge (rising edge) of the clock signal is located at time T2, the output buffer circuit outputs a voltage signal at time T2 according to the third trigger edge of the two clock signals, so as to drive the pixel unit X3.
For another example, the expected output sequence of the voltage signals is that the 1 st to 10 th voltage signals are sequentially output at the time T0 to T9, then the PWM generator 121 is controlled to generate a clock signal to trigger the output buffer circuit according to the compensation lookup table, and the duty ratio of the oscillating clock signal is adjusted, so that the trigger edges of the generated clock signal respectively correspond to the time T0 to T9, that is, the first trigger edge (rising edge) of the clock signal is located at the time T0, the second trigger edge (rising edge) of the clock signal is located at the time T1, and so on. If the expected output sequence of the voltage signals is the 1 st to 10 th voltage signals, two paths of the voltage signals are output in parallel at the time T0 to T4 in sequence, the PWM generator 121 is controlled to generate two paths of clock signals according to the compensation lookup table to trigger the output buffer circuit, and the duty ratio of the oscillation clock signals is adjusted, so that the trigger edges of the two paths of clock signals respectively correspond to the time T0 to T4, namely, the first trigger edges (rising edges) of the two paths of clock signals are all located at the time T0, the second trigger edges (rising edges) of the two paths of clock signals are all located at the time T1, and so on.
For easy understanding, the following description will be given by taking the output buffer circuit 2 provided in fig. 4-10 as an example, which outputs 5 voltage signals and the clock signals corresponding to the voltage signals, where the pixel unit X1 and the pixel unit X5 are the pixel units (as shown in fig. 2) in the same gate scan line 510 that are farthest from the source driving chip 400.
Taking the example that the rising edge of the clock signal triggers the output buffer circuit 2 to output the voltage signal, the output buffer circuit 2 in fig. 4 outputs two voltage signals at the time T0 of the two clock signals output by the clock circuit 1, so as to drive the pixel unit X1 and the pixel unit X5 respectively. The output buffer circuit 2 similarly outputs two voltage signals at time T1 of the clock signal, and drives the pixel unit X2 and the pixel unit X4, respectively. The output buffer circuit 2 outputs only one voltage signal at the time T2 of the clock signal, and drives the pixel unit X3.
The order in which the output buffer circuit 2 in fig. 5 outputs the voltage signals is the same as the order in which fig. 4 outputs the voltage signals. The duty ratio of the clock signal is adjusted by fixing the falling edge and adjusting the rising edge position. As can be seen from the waveform chart of the clock signal in fig. 5, the time interval between T0 and T1 is larger than the time interval between T1 and T2, and since the output buffer circuit 2 outputs the voltage signal according to the rising edge of the clock signal, the rate of driving the pixel unit at the time T1 by the output buffer circuit 2 is smaller than the rate of driving the pixel unit at the time T2. It can be seen that by adjusting the duty cycle of the oscillating clock signal generated by the clock generator 112, the clock signal is generated such that the interval between the rising edges of at least two adjacent pulses in the clock signal is not equal to the interval between the rising edges of other adjacent pulses, and the rate at which the output buffer circuit 2 drives the pixel unit can be changed. Illustratively, the rate at which the output buffer circuit 2 drives the pixel cells is inversely related to the interval between the rising edges of adjacent pulses of the clock signal, i.e., the greater the interval between the rising edges of adjacent pulses of the clock signal, the smaller the rate at which the output buffer circuit 2 drives the pixel cells, and vice versa, the smaller the interval between the rising edges of adjacent pulses of the clock signal, the greater the rate at which the output buffer circuit 2 drives the pixel cells.
As can be seen from the foregoing description and fig. 2 and 5, the driving sequence of the pixel units provided in fig. 5 is that the pixel units far from the source driving chip are preferentially driven, and then the pixel units near to the source driving chip are driven, so that the charging condition of the pixel units far from the source driving chip is not affected by the distance, and further the problem of water ripple or color shift and other phenomena caused by the unequal distances between the pixel units and the source driving chip is solved. In addition, in fig. 5, the interval between the triggering edges (rising edges) of each pulse in the rear part of the clock signal is reduced, so that the output buffer circuit can drive the last pixel units (i.e. the pixel units near to the source driving chip) at a higher speed, the influence of the charging deficiency caused by the latest driving of the pixel units near to the source driving chip is reduced as much as possible, the abnormal picture probability of the display panel is further reduced, and the display quality of the display panel is improved. On the contrary, if the interval between the pulse triggering edges (rising edges) in the previous part of the clock signal is reduced, the output buffer circuit rapidly drives the pixel units far from the source driving chip and then slowly drives the pixel units near to the source driving chip, so that the defects of insufficient charging and the like generated by the fact that the pixel units far from the source driving chip can be compensated to the maximum extent, the probability of abnormal picture of the display panel is reduced, and the display quality of the display panel is improved.
Optionally, by adjusting the interval length between the rising edges of the pulses in the clock signal, the rate at which the output buffer circuit drives the pixel unit is gradually increased and then gradually decreased, or gradually decreased and then gradually increased, or may be increased and then decreased, or may be decreased and then decreased. The present disclosure is not limited to this, and can be set according to actual requirements.
The output buffer circuit 2 in fig. 6-7 outputs a voltage signal at time T0 of a clock signal outputted from the clock circuit to drive the pixel unit X1 or the pixel unit X5. For example, in the case where the output buffer circuit 2 drives the pixel unit X1 at time T0 (as in fig. 6), the output buffer circuit 2 drives the pixel unit X2 at time T1 of the clock signal, drives the pixel unit X3 at time T2 of the clock signal, drives the pixel unit X4 at time T3 of the clock signal, and drives the pixel unit X5 at time T4 of the clock signal. For example, in the case where the output buffer circuit 2 drives the pixel unit X5 at time T0 (as in fig. 7), the output buffer circuit 2 drives the pixel unit X4 at time T1 of the clock signal, drives the pixel unit X3 at time T2 of the clock signal, drives the pixel unit X2 at time T3 of the clock signal, and drives the pixel unit X1 at time T4 of the clock signal.
Illustratively, in fig. 6 and 7, the duty cycle in the clock signal is equal (i.e., the intervals between the trigger edges of each adjacent pulse are equal), and by adjusting the interval between the rising edges of two adjacent pulses in the clock signal, the rate at which the output buffer circuit drives the pixel cell can be adjusted. For example: the output buffer circuit 2 in fig. 8 and 9 outputs a voltage signal at the time T0 of the clock signal outputted from the clock circuit 1 to drive the pixel unit X1 or the pixel unit X5. Hereinafter, taking a case where the output buffer circuit 2 drives the pixel unit X1 at time T0 (as in fig. 8), the output buffer circuit drives the pixel unit X2 at time T1 of the clock signal, drives the pixel unit X3 at time T2 of the clock signal, drives the pixel unit X4 at time T3 of the clock signal, and drives the pixel unit X5 at time T4 of the clock signal. The interval between the time T0 and the time T1 in the clock signal is equal to the interval between the time T1 and the time T2 and is larger than the interval between the time T2 and the time T3, which is equivalent to that the output buffer circuit 2 in fig. 8 drives the pixel unit slowly before the time T2 (i.e. T0-T2) and drives the pixel unit rapidly after the time T2 (i.e. T3-T4). For the same reason, the output buffer circuit 2 in fig. 9 drives the pixel cells fast before time T2 (i.e., T0-T2), and drives the pixel cells slow after time T2 (i.e., T3-T4). Alternatively, the clock signal may be such that the intervals between each time are not equal (i.e. the intervals between the rising edges of the pulses in the clock signal are not equal), so that the rate at which the buffer circuit 2 drives the pixel cells is changed a plurality of times. That is, as shown in fig. 10, the interval between the rising edges of the pulses in the clock signal becomes larger and smaller, and the rate at which the output buffer circuit 2 drives the pixel unit becomes larger and smaller and larger.
The output control circuit and the display panel provided by the disclosure independently generate at least one path of clock signal through the clock circuit to control the output buffer circuit to output and drive the voltage signal of each pixel unit, so that the problem of water ripple or color cast and other phenomena generated due to the fact that the distances between the pixel units and the source electrode driving chip are different is solved, the probability of abnormal pictures of the display panel is further reduced, and the display quality of the display panel is improved. In addition, the output control circuit in the display panel provided by the disclosure can independently generate the clock signal for controlling the output buffer circuit to output the voltage signal, so that compared with a clock circuit which needs to generate the clock signal according to the system clock of the display panel, the clock signal generated by the output control circuit and the time of the trigger edge of each pulse are not limited by the clock signal in the display panel, the clock signal can be flexibly generated, and the purposes of generating the clock signal more in accordance with the actual application requirement, freely controlling the output buffer circuit to output the voltage signal and driving the corresponding pixel unit are realized.
The present disclosure also provides a display panel including the output control circuit of the source driving chip described above.
Optionally, the display panel may be one of a liquid crystal display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, and an organic light emitting diode display panel.
The display panel provided by the disclosure can independently generate at least one path of clock signal through the clock circuit to control the output buffer circuit to output the voltage signal for driving each pixel unit. The method can control the output buffer circuit to output voltage signals to each pixel unit, further solve the problem of water ripple or color cast and other phenomena caused by unequal distances between the pixel units and the source electrode driving chip, further reduce the probability of abnormal pictures of the display panel and improve the display quality of the display panel. In addition, the output control circuit in the display panel provided by the disclosure can independently generate the clock signal for controlling the output buffer circuit to output the voltage signal, so that compared with a clock circuit which needs to generate the clock signal according to the system clock of the display panel, the clock signal generated by the output control circuit and the time of the trigger edge of each pulse are not limited by the clock signal in the display panel, the clock signal can be flexibly generated, and the purposes of generating the clock signal more in accordance with the actual application requirement, freely controlling the output buffer circuit to output the voltage signal and driving the corresponding pixel unit are realized.
In some embodiments of the present disclosure, a display panel includes: the display device includes a timing control circuit, a source driving chip 400, a plurality of data lines 410, a gate driving chip 500, and a plurality of gate scan lines 510.
Referring to fig. 2 and 11, the source driving chip 400 includes: an input interface 4, a shift register 5, a data latch 6, a digital-to-analog converter 7, a gamma corrector 8, and an output control circuit (including the clock circuit 1 and the output buffer circuit 2).
Further, the shift register 5 receives display data and a system clock outputted from the timing control circuit through the input interface 4, and generates a strobe signal. The data latch 6 receives display data serially input in accordance with a system clock in accordance with a strobe signal. In the case where the data latch 6 is full of one line of display data, the latched display data is output to the digital-analog converter 7. Wherein the row of display data is capable of driving pixel cells in the same gate scan line 510.
Further, the data analog converter 7 converts the display data outputted from the data latch 6 into a multi-path voltage signal according to the correction signal outputted from the gamma corrector 8, and transmits it to the output buffer circuit 2 in the output control circuit.
Further, the output buffer circuit 2 outputs a voltage signal according to the clock signal output from the clock circuit 1, and drives the corresponding pixel unit.
In addition, after the display data enters the data analog converter 7 to perform digital analog conversion, the data latch 6 can start to receive the display data of the next line. Equivalently, the input of the new line of display data and the digital-to-analog conversion of the previous line of display data are parallel (i.e., performed simultaneously).
The display panel provided by the disclosure can independently generate at least one path of clock signal through the clock circuit to control the output buffer circuit to output the voltage signal for driving each pixel unit. The method can control the output buffer circuit to output voltage signals to each pixel unit, further solve the problem of water ripple or color cast and other phenomena caused by unequal distances between the pixel units and the source electrode driving chip, further reduce the probability of abnormal pictures of the display panel and improve the display quality of the display panel. In addition, the output control circuit in the display panel provided by the disclosure can independently generate the clock signal for controlling the output buffer circuit to output the voltage signal, so that compared with a clock circuit which needs to generate the clock signal according to the system clock of the display panel, the clock signal generated by the output control circuit and the time of the trigger edge of each pulse are not limited by the clock signal in the display panel, the clock signal can be flexibly generated, and the purposes of generating the clock signal more in accordance with the actual application requirement, freely controlling the output buffer circuit to output the voltage signal and driving the corresponding pixel unit are realized.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (11)
1. An output control circuit for a source driving chip in a display panel, the output control circuit comprising: the output buffer circuit is electrically connected with the clock circuit;
the clock circuit generates at least one path of clock signal through oscillation;
the output buffer circuit receives a voltage signal and the clock signal, and outputs the voltage signal according to the clock signal to drive a pixel unit corresponding to the voltage signal, wherein the voltage signal is generated by a source drive chip according to input image digital data;
wherein the clock signal comprises a trigger edge; the trigger edge is used for triggering the output buffer circuit to output the voltage signal.
2. The output control circuit of claim 1, wherein the clock circuit comprises: the clock oscillation circuit and the compensation generation circuit are electrically connected with the clock oscillation circuit;
the compensation generating circuit receives the oscillation clock signal generated by the clock oscillating circuit and generates the clock signal by adjusting the duty ratio of each pulse in the oscillation clock signal.
3. The output control circuit of claim 2, wherein the clock oscillation circuit further comprises: an oscillator and a clock generator electrically connected with the oscillator;
the clock generator receives an oscillation signal generated by the oscillator, adjusts the frequency of the oscillation signal according to a frequency lookup table, and generates the oscillation clock signal;
the frequency lookup table comprises a corresponding relation between signal frequency and voltage loss of the display panel;
the voltage loss of the display panel is inversely related to the ratio of the voltage signal output by the output buffer circuit to the voltage signal obtained by the corresponding pixel unit.
4. The output control circuit according to claim 3, wherein a ratio of the voltage signal output from the output buffer circuit to the voltage signal obtained by the corresponding pixel unit is positively correlated with a resistance value of a data line for transmitting the voltage signal in the source driving chip.
5. The output control circuit according to claim 3, wherein a ratio of the voltage signal output from the output buffer circuit to the voltage signal input to the corresponding pixel unit is positively correlated with a resistance value of the glass substrate of the display panel.
6. The output control circuit according to claim 3, wherein the compensation generating circuit includes: a PWM generator;
the signal input end of the PWM generator receives the oscillation clock signal generated by the clock generator, adjusts the duty ratio of pulses in the oscillation clock signal according to a compensation lookup table, determines the number of the clock signals and generates at least one path of clock signals;
the compensation lookup table is a corresponding relation between the output time of the voltage signal and the triggering edge of the clock signal.
7. The output control circuit according to claim 1, wherein the clock circuit outputs a predetermined number of clock signals in parallel, and the output buffer circuit outputs the voltage signals for driving the corresponding pixel units simultaneously according to the first periodic pulse of the clock signals.
8. The output control circuit according to claim 1, wherein the clock circuit outputs two parallel clock signals, and the output buffer circuit outputs two voltage signals simultaneously according to a first period pulse of the clock signals for driving the first pixel unit and the second pixel unit simultaneously;
the first pixel unit and the second pixel unit are pixel units positioned at two ends of the same grid scanning line.
9. The output control circuit according to any one of claims 1 to 8, wherein the interval between the trigger edges of at least two adjacent pulses in the clock signal is not equal to the interval between the trigger edges of other adjacent pulses.
10. A display panel, characterized in that the display panel comprises an output control circuit as claimed in any one of claims 1-9.
11. The display panel of claim 10, wherein the display panel is one of a liquid crystal display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, and an organic light emitting diode display panel.
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