CN1140366A - Parameter Table Reduction Device for Variable Length Decoder - Google Patents

Abstract

A parameter table reduction device of a variable length decoder comprises a parameter table device and a mask circuit. The parameter table device decodes the input data into a level code and a length code, and uses the mask circuit to operate the input data and the length code to generate a symbol bit, and then takes the level code and the symbol bit as the output.

Description

Parameter Table Reduction Device for Variable Length Decoder

The present invention relates to a decoding device in a data transmission system, in particular to a parameter table (codetable) device of a variable length decoder.

Variable length coding (variable length coding) technology is used for data compression systems that require lossless (lossless), and converts fixed-length data into codewords with an indefinite length according to statistical results, so that data with higher frequency It can be stored or transmitted with a small amount of information, and a larger amount of data can be compressed. Therefore, in a transmission or processing system that requires a large amount of data, such as high-definition television (HDTV), a variable-length decoding circuit with a faster processing speed is used to provide high-efficiency conversion of video information data.

The structure generally used for variable-length decoding, as shown in FIG. In the above structure, especially for the video information processing system used to cooperate with MPEG I (Motion Picture Experts Group) or MPEG II standard, it is used to decode the parameter table device of the coefficient of discrete cosine transform (Discrete cosine transform, referred to as DCT), will is the largest part. For example, the zeroth DCT parameter table device applicable to the MPEG II standard has 114 variable-length codewords, and the longest codeword among them contains 17 bits. Therefore, if this part of the structure can be properly designed, the occupied area can be reduced, making the overall video information processing system more refined and high-density.

Since the general parallel variable-length decoder mostly uses the programmable logic array (PLA) to provide the information required for decoding, so that the size of the programmable logic array and the delay time of the transmitted signal are the key factors of the decoding efficiency of the variable-length decoder. . Therefore, in order to meet the above-mentioned requirements for improving the functions of the overall video information processing system, there are currently redesigning the structure of the variable-length decoder, or rebuilding the combined type of the programmable logic array. Even read-only memory (ROM) replaced the programmable logic array in an attempt to increase processing speed. However, because the ROM requires a large space, it is unacceptable even though it provides a faster running function.

Then, analyze the configuration situation of the parameter table device in the variable length decoder, take the MPEG standard as an example, the discrete cosine transform coefficient table is decoded into a length code (run) and a level code (Level), so that the bit level code has Codewords with positive and negative values. Please refer to the device structure of the parameter table shown in Figure 2, because there are positive and negative values, the bit-level code contains a data and a sign bit (sign bit), and the data is combined with the sign bit to form a parameter table Part of a given codeword plan within a device. That is to say, in the parameter table device, corresponding to the same data but different symbol bit code words must be processed separately, and the order codes of positive and negative values are regarded as two irrelevant code words, and respectively in the positive value code area 11 Convert with the negative value code area 12. In this way, the parameter table device must repeatedly support other identical data because it provides and processes codewords with only different sign bits, resulting in waste of hardware space, and even longer delay time, which affects processing efficiency.

Therefore, the main purpose of the present invention is to provide a variable-length decoder parameter table reduction device, which avoids repeated processing of bits of codeword symbols, saves hardware space, and improves decoding efficiency.

In order to achieve the above object, the present invention promptly provides a kind of variable length decoder parameter list reduction device, in order to decode an input data with positive and negative values, and this device comprises:

A parameter table device generates a corresponding scale code and a length code with the numerical value part of the input data; and

A mask circuit operates the input data and the length code provided by the parameter table device to generate a sign bit; the combination of the sign bit and the level code generated by the parameter table device is the decoding result.

Wherein, the parameter table device can be a programmable logic array. The parameter table device may also be a read-only memory device.

The value portion of the input data used by the parameter table device can be obtained by removing the sign bit of the input data.

The mask circuit may include:

An AND gate has two sets of input ports for respectively inputting the length code and the input data for logical operation;

An OR gate has a plurality of input ports, and performs "OR" logic operation on the output bits of the AND gate to generate the sign bit. The input data may be provided by a barrel shifter.

Since the mask circuit only needs to be composed of simple logic circuits, the space of the decoder can be greatly reduced, and a smaller-sized programmable logic array is used as a parameter table device, which can minimize the delay time and improve decoding efficiency. .

In order to make the above-mentioned and other purposes, features and advantages of the present invention more obvious, a preferred embodiment is specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows:

FIG. 1 shows the structure of a known variable length decoder.

FIG. 2 is a schematic diagram showing the configuration of the parameter table device in the structure of FIG. 1 .

FIG. 3 is a structure of a variable length decoder according to a preferred embodiment of the present invention.

FIG. 4 is a structural diagram of a mask circuit in the structure of FIG. 3 .

In the variable length decoder of the present invention, the sign bit of the input codeword is not sent to the parameter table device for decoding, but is processed by a mask circuit, and has a circuit structure as shown in FIG. 3 .

In the preferred embodiment circuit shown in FIG. 3, a barrel shifter 25, a parameter table device 27 and a mask circuit 29 are included. The barrel shifter 25 feeds input data into the parameter table device 27 according to the code word length information provided by the parameter table device 27 . However, the parameter table device 27 only takes the numerical part of the input data for decoding, and discards the sign bit of the input data. That is to say, for the input data having the same value part but different signs, the parameter table device 27 generates scale codes by processing in the same decoding area, so that the decoding circuit can be reduced by half.

On the other hand, the length information deciphered by the parameter table device 27, that is, the aforementioned length code, is combined with the input data provided by the barrel shifter 25 to carry out logic operations in the mask circuit 29 to select the input data. The sign bit of the data. Since this logic operation is only simple "AND" (AND) and "or" (OR) processing, the circuit structure is very simple, which is very suitable for high-density manufacturing of integrated circuits.

Therefore, if the result generated by the parameter table device 27 and the mask circuit 29, that is, the sign bit and the scale code, are combined, the decoding result can be obtained. In order to make the operation of the present invention easier to understand, an embodiment is given below for illustration.

Assume that if a part of the input data sent by the barrel shifter 25 is 0111, a total of four bits, and the last bit is the sign bit S, that is, S=1, then the value part is 011. Therefore, the code word 011 is received by the parameter table device 27 and decoded to generate a scale code, and the length code 0001000...0 is sent to the barrel shifter 25 and the mask circuit 29 respectively.

A mask circuit 29 of a preferred embodiment of the present invention is shown in FIG. 4 , including an AND gate 290 and an OR gate 291 . The AND gate 290 provides two sets of input ports to input data from the parameter table device 27 and the barrel shifter 25 respectively, and then performs an "AND" operation with the same bits of each set of data. Since the length code from the parameter table device 27 has only the value "1" of a single position relative to the sign bit, other bits are all "0", such as the above-mentioned 000100...0, which is consistent with the input data After the AND logic operation, if the sign bit of the input data is "1", the result will be in the same form as the length code, otherwise, the output bits of the AND gate 290 will all be "0". Therefore, after all the bits are input into the AND gate 290 via the OR gate 291 to perform "OR" logic operation, the sign bit value "1" or "0" will be generated.

Thus, the sign bits and scale codes generated by the mask circuit 29 and the parameter table device 27 can be combined into an output.

Since the parameter table device of the present invention is not limited to be made of a programmable logic array, it can also be made of a read-only memory according to actual needs. Compared with the known technology, if the parameter table device is made of a programmable logic array, the device of the present invention can save half of the circuit space in this part alone. Although there is another mask circuit, it is only simple. Logic, design is easy, and the volume is small. Overall, the design and size of the variable-length decoder have great advantages. It is even more feasible to consider choosing a read-only memory as a parameter table device.

Although the preferred embodiment disclosed in the present invention is as above, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the appended claims.

Claims (6)

1, the parameter table reduction device of a kind of variable-length decoder (variable Length decoder), in order to the input data with positive negative value of decoding, this device comprises:

One parameter list device partly produces the position exponent and a length code of a correspondence with the numerical value of these input data; And

One mask circuit, this length code that these input data of computing and this parameter list device provide, and produce a symbol bit; This symbol bit combines with the position exponent that this parameter list device produces and is decoded result.

2, device as claimed in claim 1, wherein, this parameter list device is a programmable logic array (PLA).

3, device as claimed in claim 1, wherein, this parameter list device is a ROM device.

4, device as claimed in claim 1, wherein, this input value data that this parameter list device utilized partly is to get with the symbol bit of removing these input data.

5, device as claimed in claim 1, wherein, this mask circuit comprises:

One with door, have two group input ports, in order to import this length code respectively and this input data are done logical operation;

One or door, have a plurality of input ports, this each bit of output with door is carried out " or " logical operation, and produce this symbol bit.

6, device as claimed in claim 1, wherein, these input data are provided by a barrel shifter.

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