CN1049309C - Parameter table reduction device for changeable length decoder - Google Patents

Abstract

The present invention relates to a parameter list reducing device of a variable length decoder, which comprises a parameter list device and a mask circuit. The parameter list device decodes input data into a bit order code and a length code, the operation of the input data and the length code is realized by the mask circuit to generate symbol bit elements, and the bit order code and the symbol bit elements are simultaneously used as output.

Description

The coefficient table reduction device of variable-length decoder

The invention relates to the decoding device in the data transmission system, particularly the coefficient table (codetable) relevant for a kind of variable-length decoder (variable length decoder) installs.

Variable length code (variable length coding) technology is that the data compression system by needs lossless (lossless) is utilized, and convert the data of regular length to code word according to statistics with indefinite length, make frequency of occurrences higher data store or transmit with less amount of information, huger data volume just can be compressed.Also therefore, in the transmission or treatment system of the relatively large data of needs, for example high definition TV (HDTV) promptly to cooperate the length-changeable decoding circuit of faster treatment speed, provides the high efficiency conversion of video information data.

General in order to carry out the structure of length-changeable decoding, as shown in Figure 1, comprise a barrel shifter (barrel shifter) 15, one coefficient table device (code table) 17 and one multiplexer 19 etc.In said structure, particularly in order to cooperate the video information process system of MPEGI (MotionPicture Experts Group) or MPEG II standard, it is in order to decoding discrete cosine transform (Discrete cosine transform, the coefficient table device of coefficient abbreviation DCT) will be the hugest part.The zero DCT coefficient table device that for example is applicable to MPEG II standard promptly has 114 variable length codewords, and the longest central code word more contains 17 positions.Therefore, if can suitably design this partial structure, make the area occupied reduction, make the exquisiter and densification of whole video information process system.

Provide decoding required information because general parallel variable-length decoder is many with programmable logic array (PLA), so that the key factor that is the variable-length decoder decoding efficiency time of delay of the size of programmable logic array and transmission signal thereof.Thereby, in order to satisfy the requirement of the whole video information process systemic-function of above-mentioned raising, have at present, or rebuild the combination form of programmable logic array the redesign of variable-length decoder structure.Even, attempt so as to improving processing speed with read-only memory (ROM) replacement programmable logic array.But it is bigger to take up room because of read-only memory is required eventually, though faster operation function is provided, also is difficult to accept.

So the configuration scenario of coefficient table device is an example with the mpeg standard in the analysis variable-length decoder, and the discrete cosine transform coefficient table is decoded into a length code (run) and an exponent (Level), an order position exponent is the code word that possesses positive negative value.Please refer to coefficient table apparatus structure shown in Figure 2, because of have positive negative value so, exponent inside, position contains data and a sign bit (sign bit), and be both some of planning of constant bit word in the coefficient table device with sign bit in the lump in conjunction with its data.That is, in the coefficient table device, corresponding to identical data but the distinct symbols bit word just must handle respectively, the position exponent of positive and negative values is considered as two incoherent code words, and respectively at changing on the occasion of sign indicating number district 11 and negative value sign indicating number district 12.Thus, the coefficient table device certainly will be handled the only different code word of sign bit because of providing, and must repeat the data of supporting that other are identical, causes the hardware space waste, more causes time of delay elongated, and influences treatment effeciency.

Therefore, main purpose of the present invention is to provide a kind of variable-length decoder coefficient table reduction device, avoids the reprocessing of code-word symbol position, to save hardware space, improves decoding efficiency.

In order to achieve the above object, the present invention promptly provides a kind of variable-length decoder coefficient table reduction device, and in order to the input data with positive negative value of decoding, this device comprises:

One coefficient table device partly produces the position exponent and a length code of a correspondence with the numerical value of these input data; And

One screened circuit, this length code that these input data of computing and this coefficient table device provide, and produce a sign bit; This sign bit combines with the position exponent that this coefficient table device produces and is decoded result.

Wherein, this coefficient table device can be a programmable logic array.This coefficient table device also can be a ROM device.

This input value data that this coefficient table device utilized partly can be got by the sign bit of removing these input data.

This screened circuit can comprise:

One with door, have two group input ports, in order to import this length code respectively and this input data are done logical operation;

One or door, have a plurality of input ports, with this and the output of door everybody carry out " or " logical operation produces this sign bit.These input data can be provided by a barrel shifter.

Because screened circuit only needs to form with the simple logic circuit and get final product, can significantly reduce the space of decoder, and be the coefficient table device, can be reduced to the shortest time of delay with the formula logic array able to programme of reduced size, and the lifting decoding efficiency.

For make above-mentioned and other purposes of the present invention, feature and advantage can be more obvious, especially exemplified by a preferred embodiment, and conjunction with figs., be described in detail below:

Fig. 1 has illustrated a structure of knowing variable-length decoder.

Fig. 2 has illustrated the configuration schematic diagram of coefficient table device in Fig. 1 structure.

Fig. 3 is the variable-length decoder structure according to a preferred embodiment of the present invention.

Fig. 4 is the screened circuit structure chart in Fig. 3 structure.

In variable-length decoder of the present invention, the sign bit of enter code word is not sent into decoding in the coefficient table device, but handles with a screened circuit in addition, and circuit structure is as shown in Figure 3 arranged.

In preferable enforcement lateral circuit shown in Figure 3, include barrel shifter 25, a coefficient table device 27 and screened circuit 29.Barrel shifter 25 is the code word size information that provides according to coefficient table device 27 and will import data feed-in coefficient table device 27.But coefficient table device 27 is only got the numerical value of input data and is partly decoded, and the sign bit of the input data of forgoing.That is for having identical numerical value part but the input data of symbol inequality, coefficient table device 27 is to be handled by mutually same area decoder to produce a position exponent, and makes decoding circuit can reduce half.

On the other hand, the length information that coefficient table device 27 solves, promptly aforesaid length code, the input data that then cooperate barrel shifter 25 to be provided are carried out logical operation in the lump in screened circuit 29, to select out the sign bit of input data.Since this logical operation only be simple " with " (AND) and " or " (OR) handle, circuit structure is very simple, very suitable integrated circuit high density manufacturing use.

So if the result that coefficient table device 27 and screened circuit 29 produced, promptly a sign bit and a position exponent combine, decoded result gets final product.For making the easier understanding of ruuning situation of the present invention, below for an embodiment to explain.

Suppose if some inputs data of being sent by barrel shifter 25 are 0111, totally four, its last is-symbol position S, i.e. S=1, then its numerical value partly is 011.So code word 011 is decoded after coefficient table device 27 receives and is produced an exponent, and has length code 0001000......0 to deliver to barrel shifter 25 and screened circuit 29 respectively.

29 of screened circuits of a preferred embodiment of the present invention as shown in Figure 4, comprise one with door 290 and one or door 291.Provide two groups of input ports respectively by coefficient table device 27 and barrel shifter 25 input data with door 290, carry out AND operation with the identical bits of each group data again.Owing to value " 1 " with respect to the single position of sign bit is only arranged from the length code of coefficient table device 27, other positions are all " 0 ", as above-mentioned 000100......0, its with the input data carry out with logical operation after, if the sign bit of input data is " 1 ", its result will be identical with the form of length code, otherwise everybody will be all " 0 " with the output of door 290.Therefore via or door 291 will carry out with all positions of door 290 inputs " or " after the logical operation, can produce symbol place value " 1 " or " 0 ".

So the sign bit and the position exponent that produce via screened circuit 29 and coefficient table device 27 can be combined into output.

Because coefficient table device of the present invention does not limit by programmable logic array and makes, it also can be made because of actual needs changes by read-only memory.With know technology and compare, make the coefficient table device if adopt with programmable logic array, device of the present invention singly can be saved the circuit space of half in this some, establish screened circuit in addition though have, so it only is a simple logic, and design easily, volume is also little, generally speaking, the design of variable-length decoder and size all have very big advantage, even consider to select read-only memory more feasible as the coefficient table device.

Though the present invention discloses preferred embodiment as above; right its is not in order to qualification the present invention, any those who are familiar with this art, without departing from the spirit and scope of the present invention; change and modification when doing some, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.

Claims (6)

1, the coefficient table reduction device of a kind of variable-length decoder (variable Length decoder), in order to the input data with positive negative value of decoding, this device comprises:

One coefficient table device partly produces the position exponent and a length code of a correspondence with the numerical value of these input data; And

One screened circuit, this length code that these input data of computing and this coefficient table device provide, and produce a sign bit; This sign bit combines with the position exponent that this coefficient table device produces and is decoded result.

2, device as claimed in claim 1, wherein, this coefficient table device is a programmable logic array (PLA).

3, device as claimed in claim 1, wherein, this coefficient table device is a ROM device.

4, device as claimed in claim 1, wherein, this input value data that this coefficient table device utilized partly is to get with the sign bit of removing these input data.

5, device as claimed in claim 1, wherein, this screened circuit comprises:

One with door, have two group input ports, in order to import this length code respectively and this input data are done logical operation;

One or door, have a plurality of input ports, with this and the output of door everybody carry out " or " logical operation, and produce this sign bit.

6, device as claimed in claim 1, wherein, these input data are provided by a barrel shifter.

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