CN114034945A - Performance test unit for system-on-chip device - Google Patents

Abstract

The invention discloses a device performance test unit of a system-on-chip, which comprises a temperature controller, a test tool and a test instrument, wherein the temperature controller comprises a control computer and a temperature heating cover arm, the control computer controls the temperature heating cover arm to cover a tested SOC device to form a cavity space, and the control computer regulates the temperature of the cavity space according to test requirements; the test tool is used for installing and fixing the SOC device, providing an excitation signal required by the SOC device and a small system environment required by SOC operation, and simultaneously providing a related interface in butt joint with a test instrument; the test instrument is used for generating an external excitation signal required by the test tool and measuring and monitoring a state signal generated by the SOC device. The invention can provide a special environment for normal temperature and high and low temperature test for the system-on-chip device, and can promote the commercial-grade system-on-chip device with low quality grade to the system-on-chip device meeting the military grade and aerospace grade use standards.

Description

Performance test unit for system-on-chip device

Technical Field

The invention belongs to the field of electronic engineering, and relates to a system-on-chip device performance testing unit which provides a special environment for normal-temperature and high-low temperature testing for a system-on-chip device and can improve a commercial-grade system-on-chip device with low quality grade into a system-on-chip device meeting military grade and aerospace grade use standards.

Background

The quality grade of an electronic component is an important index for representing the quality of the component, is an important basis for selecting, purchasing and checking the component in the design and production process of electronic equipment, and the component is generally divided into five grades, namely a commercial grade, an industrial grade, an automobile grade, a military grade and an aerospace grade according to the application scene environment of the electronic equipment where the component is located, and the characteristics of the five grades are respectively introduced as follows:

a. commercial grade:

the adaptive temperature range is 0 ℃ to +70 ℃, plastic package or resin package is generally adopted, commercial-grade indexes are adopted for production and manufacture for testing, and common household appliances, computers, mobile phones and the like basically adopt commercial-grade components and are low in price.

b. Industrial grade

The adaptive temperature range is-40 ℃ to +85 ℃, the method is similar to the commercial grade, plastic package or resin package is generally adopted, the method adopts the same process as the commercial grade and produces on the same production line, and only the test index adopts the industrial grade index.

c. Automobile level

The adaptive temperature range is-40 ℃ to +125 ℃, compared with commercial-grade and industrial-grade products, the automobile can run in harsh environments such as outdoor, high temperature, high cold, humidity and the like, the design life is generally 15 years or 20 ten thousand miles, and the requirements on environment, vibration, impact, reliability and consistency are higher, so that automobile-grade devices have better performance, stronger temperature adaptive capacity and anti-interference capacity, and need to pass AEC-Q certification, and the price is more expensive than that of industrial-grade devices.

d. Military grade

The adaptive temperature range is-55 ℃ to +150 ℃, the ceramic package is generally adopted, the most advanced process and test indexes are adopted in design and manufacture, the method is mainly used in the military industry fields of missiles, airplanes, tanks, aircraft carriers and the like, and the price is high and the precision is high.

e. Aerospace grade

The adaptive temperature range is-55 ℃ to +150 ℃, which is the highest level of components, ceramic packaging is generally adopted, the most advanced process and test indexes are adopted in design and manufacture, the device is mainly used in the aerospace fields of rockets, airships, satellites and the like, and the radiation resistance and the anti-interference capability are improved compared with the military level.

The above description of the five levels of component characteristics ranks the component quality levels from low to high: commercial grade → industrial grade → automotive grade → military grade → aerospace grade, with the most varied arrangement by number of uses: the commercial grade → the industrial grade → the automobile grade → the military grade → the aerospace grade, it can be seen that the commercial grade has the lowest quality grade but the most quantity, and from the economic benefit analysis, the commercial grade electronic component is inevitably promoted to become the dominant industry for the development and development of the component, which brings forward the current situation that the high-performance electronic component is generally the commercial grade, and the high-performance military grade and aerospace grade electronic components have the vacancy.

However, component development is not always performed, and particularly in the aspect of high-end electronic components, a certain period is necessarily required for input and output, so that special performance test units are required, and the high-end high-performance commercial-grade electronic components can be upgraded into electronic components capable of meeting the military-grade and aerospace-grade use standards through the special performance test units.

Disclosure of Invention

Aiming at the current situation of shortage of high-end high-performance military grade and aerospace grade electronic components, in order to provide a high-end system-on-chip device (SOC) meeting the application of military grade and aerospace grade products in a short time, accelerate the modernization process of national defense and aerospace in China and better promote the deep development of military and civil integration, the invention aims to provide a performance testing unit of a system-on-chip device, the performance testing unit can provide a special environment for normal temperature and high and low temperature testing for the system-on-chip device, and can improve the commercial grade system-on-chip device with low quality grade into the system-on-chip device meeting the use standards of military grade and aerospace grade.

The invention aims to be realized by the following technical scheme:

a device performance test unit of a system-on-chip comprises a temperature controller, a test tool and a test instrument;

the temperature control instrument comprises a control computer and a temperature heating cover arm, the control computer controls the temperature heating cover arm to cover the SOC device to be tested to form a cavity space, and the control computer adjusts the temperature of the cavity space according to the test requirement;

the test tool is used for installing and fixing the SOC device, providing an excitation signal required by the SOC device and a small system environment required by SOC operation, and simultaneously providing a related interface in butt joint with a test instrument;

the test instrument is used for generating an external excitation signal required by the test tool and measuring and monitoring a state signal generated by the SOC device.

Preferably, the test tool comprises an SOC device clamp, a power supply excitation unit, a functional signal excitation unit, an interface control unit, a clock unit, a discrete magnitude control unit, a FLASH loading unit, a memory unit and a signal indication unit;

the SOC device clamp is used for installing and fixing the SOC device on the test tool, needs to be adapted to the packaging size of the SOC device and can guide all functional pin signals on the SOC to the test tool;

the performance of the power supply excitation unit, the function signal excitation unit, the interface control unit, the clock unit, the discrete quantity control unit, the FLASH loading unit, the memory unit and the signal indication unit is determined by designing after analyzing the SOC device to be tested; wherein:

the power supply excitation unit provides energy supply necessary for normal operation of the SOC device;

the functional signal excitation unit provides an excitation source signal for testing and a functional signal output channel processed by the SOC device for the SOC device;

the interface control unit provides a common command and state information interaction function for the SOC device;

the clock unit forms a clock circuit together with an externally provided clock and a feedback circuit inside the SOC device to provide clock excitation for the SOC device;

the discrete magnitude control unit provides reset, watchdog and pin configuration signals of the SOC device;

the FLASH loading unit is used for storing necessary information required by starting the SOC device;

the memory unit provides necessary cache space for the SOC device, and is used for instruction storage control and data cache;

the signal indicating unit displays some important state quantities when the SOC device runs.

The invention has the beneficial effects that:

a. the performance test unit of the system-on-chip device can provide a complete and advanced functional performance test environment for the system-on-chip device, so that the high-end and high-performance commercial-grade system-on-chip device can be quickly and effectively improved to be a high-quality-grade system-on-chip device meeting the application of military-grade and aerospace-grade products.

b. The performance test unit of the system-on-chip device provided by the invention simulates the real working environment of the system-on-chip device by carrying out the functional performance test on the system-on-chip device, tests the system-on-chip device from the aspects of functional performance and environmental adaptability, eliminates devices with early failure or potential defects, is simple to realize and comprehensive in test, is suitable for quality grade promotion test of all commercial grade type system-on-chip devices, and has universality.

Drawings

FIG. 1 is a flowchart of a method for context screening and reliability enhancement of a system-on-chip device.

FIG. 2 is a diagram of a system-on-chip device performance testing unit.

FIG. 3 is a functional block diagram of a test fixture for a device performance test unit of a system-on-chip.

FIG. 4 is a schematic block diagram of a test fixture for a device performance test unit of a system-on-chip.

FIG. 5 is a diagram of a fixture specific to a system-on-chip device.

FIG. 6 is a power supply excitation schematic block diagram of a system-on-chip device performance test unit test fixture.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

According to the functional complexity and the performance superiority of the system-on-chip device, the design of a test project is developed by researching the physical failure mechanism of a semiconductor and the potential defects of a process, meanwhile, the principle of first simple and then complex, first low cost and then high cost, and first short-time test and then long-time test are combined, as shown in FIG. 1, the test items for improving the reliability of the SOC device generally include 9 steps of appearance inspection, normal temperature initial test, temperature cycle, X-ray detection, high temperature dynamic electrical aging, normal temperature final test, low temperature test, high temperature test, and appearance re-inspection, the normal temperature initial test, the normal temperature final test, the low temperature test and the high temperature test are functional performance tests which need to electrify the system-on-chip device to be tested, are the most important links for improving the reliability of the system-on-chip device, and need to be completed on a special performance test unit of the system-on-chip device.

As shown in fig. 2, the unit for testing device performance of a system on chip in this embodiment includes a temperature controller, a test fixture, and a test instrument. In this embodiment, the functional functions of each instrument and equipment of the device performance testing unit of the system on chip are described by using the haisi Hi3559AV100 device as a test object. Hi3559AV100 is a commercial-grade 8K Ultra HD Mobile Camera SOC, a high-performance multi-core processor with a built-in ARM v8 architecture, a GPU, an NPU, an Encoder/Decoder and an ISP functional unit, and can simultaneously encode 8-channel 1080p @60Hz video, and provide functions of visual computing processing, video panorama splicing and the like.

Temperature controller

The temperature controller comprises a control computer and a temperature heating cover arm, the control computer controls the temperature heating cover arm to cover the SOC device to be tested to form a cavity space, the control computer adjusts the temperature of the cavity space according to the test requirement, and if the Hi3559AV100 is supposed to be used for a certain type of automobile, the reliability level of the Hi3559AV100 needs to be improved to an automobile level, and at the moment, the control computer can control the temperature range of the cavity space to be-40 ℃ to +125 ℃, and can set operation modes such as temperature keeping and temperature circulation.

Second, test the frock

The test tool is the core of an electrical performance test unit of the system-on-chip device, is used for installing and fixing the SOC device, provides an excitation signal required by the SOC device and a small system environment required by SOC operation, and simultaneously provides a relevant interface for butting with a test instrument. Fig. 3 is a functional block diagram of a test fixture, which includes an SOC fixture, a power excitation unit, a functional signal excitation unit, an interface control unit, a clock unit, a discrete quantity control unit, a FLASH loading unit, a memory unit, a signal indication unit, and the like, where characteristics of the SOC fixture, the power excitation unit, the functional signal excitation unit, the interface control unit, the clock unit, the discrete quantity control unit, the FLASH loading unit, the memory unit, and the signal indication unit are determined by design after analysis of a SOC device under test. The design of the test tool is completed according to the following steps:

1. SOC device clamp model selection

The SOC device clamp is used for installing and fixing the SOC device on the testing tool, needs to be matched with the packaging size of the SOC device, can guide all functional pin signals on the SOC to the testing tool, and can conveniently replace the SOC device to be tested.

Hi3559AV100 was packaged with FCBGA, with a total of 1067 pins, a pin pitch of 0.65mm, and 25mm by 25mm dimensions, from which package a proprietary fixture from Shanghai Kagaku electronic technology corporation was selected, as shown schematically in FIG. 5.

2. Test function Block determination

Starting from the characteristics of the SOC device, analyzing the minimum hardware configuration environment required by the normal operation of the SOC device, classifying and confirming the peripheral interface of the SOC device, and considering the key state signals generated and obtained by exciting the function signals of the SOC to be tested.

Hi3559AV100 is a professional SOC for multimedia processing, a high-performance multi-core processor with an ARMv8 architecture, a GPU, an NPU, an Encoder/Decoder and an ISP functional unit are built in the SOC, two groups of DDR4 SDRAM controllers and external interfaces such as I2C, I2S, UART, GPIO and SPI are integrated on the chip at the same time. According to the characteristic features of Hi3559AV100, the electrical performance test thereof needs to provide:

a. power supply

Providing the energy supply necessary for the normal operation of the Hi3559AV 100.

b. Small system support

Clock: an externally provided clock and an internal feedback circuit form a clock circuit together to provide clock excitation for the clock circuit;

v discrete quantity: the method comprises the steps of resetting, watchdog and some configuration signals, so that the small system can be started normally, and the working mode of a chip is determined;

v memory space: providing necessary cache space for normal operation of the system, and being used for operations such as instruction storage control, data caching and the like;

v FLASH space: for storing necessary information required by the system operation, such as BOOT programs, operating system programs, application programs, and the like.

c. Interface and signal excitation

The serial port and the network port are used as basic interface configurations and provide common information interaction functions; the video interface is used as an important functional interface of the Hi3559AV100 and provides access and output of video image signals;

3. test schematic block diagram determination

According to a test function block diagram of the test tool, the principle of the test tool is designed in detail by combining the characteristics of the SOC device, and the correctness of the principle design of the test tool is the key for the success of the test tool.

Taking the Hi3559AV100 as an example, a schematic block diagram of a test fixture is shown in fig. 4, the test fixture is a test carrier of a Hi3559AV100 device, the test fixture takes a Hi3559AV100 clamp as a center, the exterior mainly comprises a power supply excitation unit, a clock unit, a discrete quantity control unit, a memory unit, a FLASH loading unit, an interface control unit and a function signal excitation unit, and after the Hi3559AV100 starts to work, the interface and function conditions of the Hi3559AV100 can be judged by observing RS232 serial port information in the interface control unit and information output by HDMI display in the function signal excitation unit. The detailed description is as follows:

1) power supply excitation unit

As shown in fig. 6, the power supply excitation unit shown in this embodiment is composed of a plurality of DC-DC power converters LTM4644, which convert an external power supply (12V or 5V) into internal voltages of 0.8V, 1.2V, 1.8V, 2.5V, and 3.3V and output the internal voltages to the Hi3559AV100, where the functions of the voltages are specifically:

the V of V0.8 is used for supplying power to an Hi3559AV100 kernel, and comprises four kernel power supplies of DVDD _ MEDIA, DVDD _ CPU and DVDD _ GPU;

v is 1.2V for supplying power to a Hi3559AV100 DDR4 controller and a DDR4 SDRAM;

v1.8 is used for supplying power to Hi3559AV100 PLL, Hi3559AV100 IO, SPI NAND Flash chip and eMMC;

v is 2.5V for DDR4 SDRAM power supply;

V3.3V for Hi3559AV100 IO, ethernet PHY, eMMC power.

2) Clock unit

The crystal oscillators in the clock units generate 24MHz clock signals which are directly sent to a special XIN pin and an XOUT pin of the Hi3559AV100, and the corresponding frequency clock signals required by each internal functional unit are generated through a PLL (phase locked loop) in the Hi3559AV 100.

3) Discrete quantity control unit

The Hi3559AV100 selects internal Reset or external Reset by judging the state of a special POR _ SEL pin when being electrified, and selects the internal Reset when the POR _ SEL is in a high level, namely the Hi3559AV100 is Reset by an internal Power On Reset circuit after being electrified; when POR _ SEL is low, an external reset is selected, at which time the Hi3559AV100 internal watchdog takes effect and monitors the chip.

In the power-on initialization process of the Hi3559AV100, the working mode of each unit is determined according to the pull-up and pull-down states of the configuration pins, specifically:

TEST _ MODE: the 0 time is a function mode, and the 1 time is a test mode;

v. BOOT _ SEL [1:0 ]: starting from SPI FLASH at 00, NAND FLASH at 01, EMMC at 10 and UFS at 11;

v SFC _ DEVICE _ MODE: SPI NOR FLASH is selected when 0, and SPI NAND FLASH is selected when 1;

root _ SEL 2: starting according to the mode set by BOOT _ SEL [1:0] at 0, and starting from BOOTROM at 1;

root _ SEL 3: 0 from A53MP Core0, 1 from A53 UP;

root _ SEL 4: 0-time PCIe autonomous starting mode, 1-time PCIe slave starting mode;

PCIE _ deep _ SEL: the PCIe PHY de-emphasis parameter is-3.5 dB at 0, and-6 dB at 1;

PCIE _ REFCLK _ SEL: the PCIe PHY selects an internal clock when 0 and selects an external clock when 1;

√ PCIE _ USB3_ MODE [1:0 ]: the multifunctional interface is PCIe 2 mode at 00, PCIe 1+ USB 3P 1 mode at 01, and USB 3P 0+ USB 3P 1 mode at 10.

The discrete magnitude control unit shown in this embodiment provides the reset, watchdog and pin configuration signals, so as to ensure that the SOC device can be normally started, and determine the operating mode of the SOC device.

4) Memory cell

Hi3559AV100 is provided with a DDRC (DDR SDRAM controller) to realize data access to a DDR4/LPDDR4 SDRAM, and a DDR4/LPDDR4 SDRAM device conforming to the JEDEC standard can be supported by configuring a timing parameter register of the DDRC, and the method specifically comprises the following steps:

a. butt DDR4 SDRAM device

When a DDR4 SDRAM device is butted, the lowest working frequency is supported to be DDR4-1600Mbps, the highest working frequency is supported to be DDR4-2666Mbps, a dual-channel mode is adopted, and each channel supports 32bit interconnection.

b. Butt-joint LPDDR4 SDRAM device

When the LPDDR4 SDRAM device is docked, the lowest operating frequency is supported to be LPDDR4-800Mbps, the highest operating frequency is supported to be LPDDR4-2666Mbps, a four-channel mode is adopted, each channel supports 16-bit interconnection, and 1 LPDDR4 SDRAM is docked every two channels.

The DDRC interface timing sequence meets JEDEC standard, and data access and state control of DDR4/LPDDR4 SDRAM, including read-write access, automatic refresh, low power consumption control and the like of DDR4/LPDDR4 SDRAM, are completed by sending command words of DDR4/LPDDR4 SDRAM.

In this embodiment, the memory unit to which the Hi3559AV100 is interfaced is composed of DDR4 SDRAM devices, the model of the DDR4 SDRAM device is MT40a512M16LY-062E IT, the total capacity is 4 × 8Gb (8 Gb/chip), and each channel contains 2 chips of 512M × 16 bits. The memory unit provides necessary cache space for normal operation of the SOC device, and is used for operations such as instruction storage control and data caching.

5) FLASH loading unit

The Hi3559AV100 includes an FMC (Flash Memory controller), and the FMC provides a Memory interface to connect with an external SPI NAND Flash, an SPI NOR Flash, and a NAND Flash, thereby completing data reading. The CS0 space of the Hi3559AV100 has a BOOT function, the BOOT space of 1MB is supported, the FMC is in a BOOT mode by default, data can be directly read from Flash to be started, and the read address range is 0x 000000-0 xFFF.

BOOT of SPI NOR Flash

Since the address space of the SPI NOR Flash is continuous, 1MB of BOOT data is directly mapped to the address space 0x 000000-0 xFFFFF of the SPI NOR Flash, before starting BOOT, when the Hi3559AV100 reads the BOOT space for the first time, the FMC acquires WIP of the SPI NOR Flash through the Read Status command, if WIP is 1, the FMC continues to acquire until the WIP return value is 0, and the FMC starts to send a Read operation to the SPI NOR Flash.

SPI NAND Flash and BOOT of NAND Flash

For SPI NAND Flash and NAND Flash, because the address space is discontinuous and there is a possibility of bad blocks, the BOOT data of 1MB cannot be directly mapped to Flash, and the BOOT also needs page _ size and block _ size information for address decoding. The FMC supports an adaptive BOOT function, and can automatically adapt the ecc _ type, page _ size and Block _ size information of the device according to the data of Block 0. FMC requires that physical Block0 must be a good Block and that other blocks be bad blocks that can be automatically skipped. When the FMC is at BOOT, the FMC can automatically jump over a bad block to find a good block and read BOOT information after encountering the bad block, 4 bad blocks can be continuously jumped over at most in each bad block jumping process, and BOOT fails if 5 physical bad blocks continuously appear in the process of one bad block jumping. The whole BOOT process can have a plurality of bad block jumping processes, when a good block is encountered, the bad block jumping process is finished, and if a bad block is encountered again, a new bad block jumping process is started. The FMC logic has the following three conditions for determining bad blocks:

marking the bad block marking bits of the first page and the last page of the current physical block as 0 xFF;

the first page and last page empty block flag bits of the current physical block are labeled 0x 00;

the error correction unit ECC at OOB of the first page and the last page of the current physical block can correct errors.

When the three conditions are met at the same time, the FMC logic can judge the block as a good block, otherwise, the block is judged as a bad block.

In this embodiment, the FLASH loading unit to which the Hi3559AV100 is docked is an SPI NAND FLASH device, the model of the SPI NAND FLASH device is MT29F2G01ABBGDWB-IT, the total capacity is 2Gb, 2 plane × 1024block/plane × 64page/block × 2176B/page, and the number of times of erasing is 100000 times. The FLASH loading unit is used for storing necessary information required by the operation of the SOC device, such as a BOOT program, an operating system program, an application program and the like.

6) Interface control unit

The interface control unit provides debugging functions of a serial port and a network port through the RS232 transceiver and the PHY, and common information interaction is realized.

In the embodiment, the UART0 interface of the Hi3559AV100 is connected with an RS232 transceiver device with a model of MAX3232EUE +.

The Hi3559AV100 is provided with a GMAC interface, and can realize Ethernet communication through an externally-arranged PHY (physical layer), so that the aims of logic programming and state monitoring debugging of a video processing daughter card are fulfilled. In this embodiment, the RGMII interface of Hi3559AV100 is connected to PHY of 88E1512-A0-NNP2I000, and supports 10/100/1000BASE-T IEEE 802.3.

7) Functional signal excitation unit

In this embodiment, the functional signal driver unit includes a video input interface VI and a video output interface VO.

The video input interface VI is a video input acquisition processing unit supporting multiple timing inputs, the Hi3559AV100 can configure different functional modes so that it can flexibly adapt to different input video interfaces, and VI supports at most 8 video inputs, typical inputs are as follows:

v1-path 8k @30Hz (dual-core VIPROC parallel processing);

4k @120Hz (dual core VIPROC parallel processing) for the V1 path;

inputting 4k @120Hz 2F WDR through a V1 path;

a V2 path 4k @60Hz input;

4-way 4k @30Hz input of the check mark;

a V8 path is input at 1080p @30 Hz;

a square root 1 path 4k @6Hz input and a 4 path 1080p @30Hz input;

v2-way 720p input (74.25MHz single edge sampling);

v 2 way 1080p input (148.5MHz single edge sampling).

In this embodiment, VI of the Hi3559AV100 is configured as a MIPI Rx Interface, a Mobile Industry Processor Interface MIPI Rx (Mobile Industry Processor Interface Receiver) is an acquisition unit supporting multiple differential video input interfaces, a main function is conversion of Interface timing, the MIPI Rx can receive data of the MIPI/LVDS/sub-LVDS/HiSPi Interface through different functional configurations and support transmission requirements of multiple speeds and resolutions, the MIPI Rx includes 4D-PHYs, each PHY has two pairs of differential associated clocks (CLK0/CLK1), each pair of clocks corresponds to 2 pairs of data, and thus the MIPI Rx can simultaneously support 1-8 paths of video input.

As shown in fig. 4, in this embodiment, the FPGA generates 4 paths of original MIPI video signals (including an LVDS high-speed portion and a CMOS low-speed portion), generates MIPI D-PHY data streams after being converted by the protocol chip MC20902, and sends the MIPI D-PHY data streams into VI of Hi3559AV100

The video output interface VO is a display channel interface of video and image data in the memory, and the VO of the Hi3559AV100 includes HDMI, MIPI Tx, and bt.1120 interfaces, in this embodiment, the HDMI is used as a video output interface, supports 2160p @60Hz video output, and conforms to the HDMI2.0 standard specification.

Third, the test instrument

The test instrument is used for generating an external excitation signal required by the test tool and measuring and monitoring a state signal generated by the SOC device.

The external excitation signals comprise power supply excitation and function signal excitation, the excitation signals are determined according to the test tool and the SOC characteristics to be tested, for example, the Hi3559AV100 is tested, the DC-DC requirement input power supply on the test tool is 12V or 5V, so the test instrument provides 12V or 5V power supply excitation signals, the video excitation signals required by the Hi3559AV100 are generated by an FPGA on the test tool, the test instrument does not need to generate additional video excitation signals, and the test instrument can also send control instructions such as control commands for starting image splicing and video coding to the Hi3559AV100 through a serial port and a network port.

State signals generated by the SOC device and the function operation result of the SOC device are output to a testing instrument through a testing tool, the testing instrument can print, display or judge the signals, for example, the Hi3559AV100 is tested, after interface traversal test is carried out on the Hi3559AV100 by testing software, the testing instrument needs to output a testing result through an RS232 debugging serial port, the testing instrument needs to be provided with an RS232 receiving port and can print the testing result, the result of processing videos by the Hi3559AV100 is finally output through an HDMI interface, and the testing instrument needs to have the capacity of receiving and displaying the HDMI videos.

The test instrument may provide the following test items:

1) interface traversal testing

The method comprises the steps of establishing a cross compiling environment on a Linux server, providing cross compiling service for software operation, traversing an SPI NAND interface, a DDR4 interface, an Ethernet interface, a UART interface, an HDMI interface, an MIPI interface and a PCIE interface through software, and confirming test results of the interfaces through serial port printing information of a test instrument.

2) Functional testing

Image stitching function

An ARM core of a Hi3559AV100 device reads data from a memory, and the data sequentially pass through VI- > VPSS- > AVS- > VO, so that a single image or a multi-path spliced image can be displayed.

GPU computing function

The Hi3559AV100 device ARM core reads data from the memory and transmits the data to the GPU video memory area, after the GPU is calculated, the result data are transmitted back to the ARM core, and the ARM core calls the VO to display the operation result.

Video encoding and decoding function

The Hi3559AV100 device receives original video data sent by the FPGA through the MIPI interface and stores the original video data into a memory, an ARM core reads the data from the memory, the encoding and decoding functions are completed through VI- > VPSS- > VENC- > VDNC (H.264/H.265), and finally the decoded video is output through VO.

The control computer, the test tool and the test instrument in the system-on-chip device performance test unit need to be matched with each other to exert the efficacy of the test unit to the maximum extent, taking the electrical performance test of the Hi3559AV100 device as an example, the test flow is as follows:

a. the tested Hi3559AV100 device is fixed on a test tool through a special SOC clamp;

b. the temperature heating cover arm covers the tested Hi3559AV100 device to form a small space, and the control computer adjusts the temperature of the small space;

c. the test fixture provides an excitation signal required by the Hi3559AV100 device according to an instruction of the test instrument, and the Hi3559AV100 device works and outputs state information, video information and network information to the test instrument through a related interface;

d. the test instrument receives signals output by the test tool, and the electrical property condition of the tested Hi3559AV100 device can be determined by observing serial port printing information, video display information and the like.

It should be understood that equivalents and modifications of the present invention and its concept may occur to those skilled in the art, and all such modifications and alterations are intended to fall within the scope of the appended claims.

Claims (2)

1. The utility model provides a system on chip device capability test unit, includes temperature controller, test fixture and test instrument, its characterized in that:

the temperature control instrument comprises a control computer and a temperature heating cover arm, the control computer controls the temperature heating cover arm to cover the SOC device to be tested to form a cavity space, and the control computer adjusts the temperature of the cavity space according to the test requirement;

the test tool is used for installing and fixing the SOC device, providing an excitation signal required by the SOC device and a small system environment required by SOC operation, and simultaneously providing a related interface in butt joint with a test instrument;

the test instrument is used for generating an external excitation signal required by the test tool and measuring and monitoring a state signal generated by the SOC device.

2. The system-on-chip device performance testing unit of claim 1, wherein the testing tool comprises an SOC device clamp, a power supply excitation unit, a functional signal excitation unit, an interface control unit, a clock unit, a discrete quantity control unit, a FLASH loading unit, a memory unit, and a signal indication unit;

the SOC device clamp is used for installing and fixing the SOC device on the test tool, needs to be adapted to the packaging size of the SOC device, and can guide all functional pin signals on the SOC to the test tool;

the characteristics of the power supply excitation unit, the functional signal excitation unit, the interface control unit, the clock unit, the discrete quantity control unit, the FLASH loading unit, the memory unit and the signal indication unit are designed and determined after the SOC device to be tested is analyzed; wherein:

the power supply excitation unit provides energy supply necessary for normal operation of the SOC device;

the functional signal excitation unit provides an excitation source signal for testing and a functional signal output channel processed by the SOC device for the SOC device;

the interface control unit provides a common command and state information interaction function for the SOC device;

the clock unit forms a clock circuit together with an externally provided clock and a feedback circuit inside the SOC device to provide clock excitation for the SOC device;

the discrete magnitude control unit provides reset, watchdog and pin configuration signals of the SOC device;

the FLASH loading unit is used for storing necessary information required by starting the SOC device;

the memory unit provides necessary cache space for the SOC device, and is used for instruction storage control and data cache;

the signal indicating unit displays some important state quantities when the SOC device runs.

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