CN114024783B - Power calibration method, device, PSE, electronic equipment and readable storage medium - Google Patents
Power calibration method, device, PSE, electronic equipment and readable storage medium Download PDFInfo
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- CN114024783B CN114024783B CN202111151065.2A CN202111151065A CN114024783B CN 114024783 B CN114024783 B CN 114024783B CN 202111151065 A CN202111151065 A CN 202111151065A CN 114024783 B CN114024783 B CN 114024783B
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The application discloses a power calibration method, a device, PSE, electronic equipment and readable storage medium. The method comprises the following steps: detecting whether a first PSE meets a power calibration condition, if so, acquiring first output power of a first power supply unit in the first PSE and first load power of a first target load; calibrating a first rated power of the first PSE based on the first output power and the first load power; the first output port of the first power supply unit is connected with the first target load, so that calibration of rated power of the PSE is achieved.
Description
Technical Field
The application belongs to the technical field of communication, and particularly relates to a power calibration method, a device, PSE, electronic equipment and a readable storage medium.
Background
In the prior art, PSE is capable of powering IP-based terminals (e.g., IP phones, wireless lan access points AP, webcams, etc.) while transmitting data signals for such devices. As a PSE, a PoE switch generally uses an ADC to detect voltage and current of each port, calculates total output power, and performs maximum output power limitation management by determining whether the output power exceeds a set rated value and then powering down the port. The conventional PSE device generally sets the rated output power set value below the maximum value provided by the device power supply, the lower limit of the rated output power is ensured by reducing the set value, the power supply power cannot be fully utilized, and the consistency of the output power of the PSE with the same rated output power set value is poor due to individual differences of the chip ADC precision, sampling resistor precision, wiring and device power loss, so that the problem of calibrating the rated power of the PSE is urgently solved.
Disclosure of Invention
The embodiment of the application provides a scheme for calibrating the rated power of PSE, which aims to solve the technical problem that the rated power of PSE cannot be calibrated in the prior art.
In a first aspect, the present application provides a power calibration method based on a power sourcing equipment PSE, comprising: detecting whether a first PSE meets a power calibration condition, if so, acquiring first output power of a first power supply unit in the first PSE and first load power of a first target load; calibrating a first rated power of the first PSE based on the first output power and the first load power; wherein a first output port of the first power supply unit is connected with the first target load.
In a second aspect, the present application provides a power calibration method, comprising: acquiring a calibration request sent by a main control chip in a main control chip group, wherein the calibration request is used for indicating that a first PSE corresponding to the main control chip meets a power calibration condition; transmitting a calibration instruction to the main control chip based on the calibration request to trigger the main control chip to acquire a first output power of a first power supply unit and a first load power of a first target load in the first PSE; calibrating a first rated power of the first PSE based on the first output power and the first load power; wherein a first output port of the first power supply unit is connected with the first target load.
In a third aspect, the present application provides a PSE-based power calibration device comprising: the device comprises a detection module, an acquisition module and a calibration module; wherein: the detection module is used for detecting whether the first PSE meets the power calibration condition, and if yes, the first output power of a first power supply unit in the first PSE and the first load power of a first target load are obtained through the obtaining module; the calibration module is used for calibrating a first rated power of the first PSE based on the first output power and the first load power; wherein a first output port of the first power supply unit is connected with the first target load.
In a fourth aspect, the present application provides a PSE comprising: main control chip, first power supply unit, and first output port, wherein: the main control chip is used for detecting whether the first PSE meets a power calibration condition, and if so, acquiring first output power of a first power supply unit in the first PSE and first load power of a first target load; calibrating a first rated power of the first PSE based on the first output power and the first load power; wherein a first output port of the first power supply unit is connected with the first target load; the first power supply unit is used for supplying power to the first target load.
In a fifth aspect, the present application provides an electronic device, comprising:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the method of any one of the first aspect, the second aspect, each possible implementation manner of the first aspect, and each possible implementation manner of the second aspect via execution of the executable instructions.
In a sixth aspect, embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method according to any one of the first aspect, the second aspect, each possible implementation manner of the first aspect, and each possible implementation manner of the second aspect.
In a seventh aspect, embodiments of the present application provide a computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of the first aspect, the second aspect, each possible implementation manner of the first aspect, and each possible implementation manner of the second aspect.
According to the scheme provided by the application, whether the first PSE meets the power calibration condition is detected, and if yes, the first output power of a first power supply unit in the first PSE and the first load power of a first target load are obtained; calibrating a first rated power of the first PSE based on the first output power and the first load power; the scheme that the first output port of the first power supply unit is connected with the first target load realizes calibration of rated power of the PSE.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1a is a flow chart illustrating a PSE-based power calibration method according to an embodiment of the present application;
FIG. 1b is a schematic diagram of a calibration circuit according to an embodiment of the present application;
FIG. 1c is a schematic diagram of a calibration circuit according to another embodiment of the present application;
FIG. 2a is a flow chart of a power calibration method according to another embodiment of the present application;
FIG. 2b is a schematic diagram of a calibration circuit according to another embodiment of the present application;
FIG. 3 is a schematic diagram of a PSE-based power calibration apparatus according to another embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.
The terms first and second and the like in the description, the claims and the drawings of embodiments of the application are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 1a is a schematic diagram of a power calibration method based on PSE according to an exemplary embodiment of the application, which may be applied to a master control chip in a first PSE, the method may include:
s101, detecting whether a first PSE meets a power calibration condition, if so, executing the following step S102;
s102, acquiring first output power of a first power supply unit and first load power of a first target load in the first PSE;
s103, calibrating a first rated power of the first PSE based on the first output power and the first load power;
wherein a first output port of the first power supply unit is connected with the first target load.
Specifically, when the first power-on flag is detected to be a preset flag, it is determined that the first PSE satisfies a power calibration condition, or
When a first calibration switch of the first PSE is detected as being on, it is determined that the first PSE satisfies a power calibration condition.
Referring to fig. 1b, the first power-on flag may be stored in a nonvolatile memory area of the main control chip, and the preset flag may be 0 or 1, which may be specifically set by a related person, which is not limited by the present application.
Further, the first calibration switch is connected in the circuit in a manner as shown in fig. 1 b.
In some optional embodiments of the present application, in S103, calibrating the first rated power of the first PSE based on the first output power and the first load power may specifically include:
s1031, calculating a first deviation value of the first load power and the first output power;
s1032, when the absolute value of the first deviation value is smaller than a first preset value, calibrating the first rated power based on the first deviation value.
Specifically, the first deviation value may be determined by a difference between the first output power and the first load power, and specifically, the first deviation value is a value obtained by subtracting the first load power from the first output power, and calibrating the first rated power based on the first deviation value includes: and taking the sum of the first deviation value and the first rated power as a calibrated first rated power.
Further, if the first deviation value is not smaller than the first preset value, displaying prompt information according to a preset prompt mode.
Optionally, the preset prompting mode may be one or more of voice prompt, text prompt, indicator light prompt, and the like. Correspondingly, the prompt information is corresponding voice content, text content or the on or off of the lamp. The first PSE may further include or correspond to a display device such as a display screen, a buzzer, or an indicator light, so as to display the prompt information.
Further, the present solution may calibrate the rated power of a plurality of PSE at the same time, based on which the above method further includes:
s11, detecting whether the second PSE meets the power calibration condition, if so, then
S12, acquiring second output power of a second power supply unit and second load power of a second target load in the second PSE;
s13, calibrating a second rated power of the second PSE based on the second output power and the second load power;
and S14, connecting a second output port of the second power supply unit with the second target load.
Referring to fig. 1c, the number of the second PSE may be one or more, and the first target load and the second target load may be the same load or may be loads with the same parameters. Wherein the parameters include rated load value, load power value, etc. In this way, the rated powers of the PSEs can be identically calibrated to improve the consistency of the output powers of the PSEs with identical rated power setting values. The principle of the calibration method for the output power of each PSE is similar to that of the foregoing calibration method, and the foregoing may be specifically referred to, which is not repeated here.
Further, in some alternative embodiments of the present application, the first load power is smaller than the first rated power, and the difference between the first rated power and the first load power is larger than a second preset value, where it is mainly ensured that the power of the PSE can be enough to support the power of the first load, and the second preset value represents the allowable deviation of the first rated power, which may be understood as the actual control accuracy of the first rated power, i.e. the power of the PSE is still capable of supporting the first load power when the rated power deviates downward (the first rated power minus the second preset value).
It should be noted that, the first target load and the second target load may also have different parameters, and the main control chip may calibrate the second rated power of the second target load respectively for different second PSEs, so as to calibrate the plurality of PSEs at the same time, and save calibration time.
Further, for the case of performing rated power calibration on multiple PSE devices at the same time, the following further describes the scheme of the present application with reference to a specific scenario:
the main control chip in the PSE samples and controls the output power of the PSE module (corresponding to the first power supply unit), and the rated value of the PSE output power is set by the main control chip. The initial rated power setting value of each PSE device can be the same, a first power-on sign is stored in a nonvolatile area of a main control chip, when the PSE device is powered on for the first time, an output port of the PSE device is connected with a rated load, the main control chip acquires the first power-on sign through the nonvolatile area, if the PSE device is judged to be powered on for the first time, the rated output power of the PSE is calibrated according to the PSE output power obtained through sampling calculation at the moment and the rated load power, meanwhile, a calibration selection switch is reserved, and the rated output power of the PSE can be calibrated by starting the calibration switch when the PSE device is not powered on for the first time.
The calibration mechanism may specifically include the following:
1) After the calibration switch is powered on and started for the first time, the calibration mode can be started by connecting the rated load, and the rated output power of the PSE is calibrated;
2) The primary power-on mark F of the main control chip is stored in a nonvolatile storage area of the main control chip, the rated output power preset value of PSE is P0, the preset rated load power is P1, the set allowable deviation range is P2, the rated load power P1 is less than P0, and the rated load power P0-P1 is ensured to be more than P2.
3) When the equipment is powered on, the main control chip judges whether to power on for the first time by reading a first power-on mark F of the nonvolatile memory, if F=1 is the first power-on, the equipment enters a calibration mode, and at the moment, an output port of the PSE equipment is connected with a rated load. After calibration starts, the main control chip samples and calculates the output power P4 of the PSE module at the moment, compares P4 with P1, compensates the rated power preset value of PSE in the main control chip if the difference value (absolute value of P4-P1) between the P4 and P1 is smaller than the preset deviation value P3, namely, the rated output power set value of the main control chip is changed to be 'P0+P4-P1', if the difference value (absolute value of P4-P1) between the P4 and P1) is larger than the preset deviation value P3, the calibration is considered to fail, the result of the calibration failure is fed back in a mode such as an indicator lamp, and after the calibration is completed, the calibration flag bit F of a nonvolatile area in the main control chip is clear 0.
4) In order to realize the calibration requirement of non-first power-on, a calibration switch is reserved, and when the master control chip detects that the calibration switch is turned on, after a rated load is connected, PSE equipment can also enter a calibration mode, and the calibration process is the same as that of first power-on.
In the calibration mechanism, P0 corresponds to the first rated power, P1 corresponds to the first load power, P2 corresponds to the second preset value, P3 corresponds to the first offset value, and P4 corresponds to the first output power; alternatively, the correspondence relationship herein may refer to the same.
According to the scheme provided by the application, whether the first PSE meets the power calibration condition is detected, and if yes, the first output power of a first power supply unit in the first PSE and the first load power of a first target load are obtained; calibrating a first rated power of the first PSE based on the first output power and the first load power; the scheme that the first output port of the first power supply unit is connected with the first target load realizes calibration of rated power of the PSE.
In addition, the maximum output power among different PSE individuals at present is different in set rated value due to the differences caused by the differences of ADC precision, sampling resistor precision, wiring and device power consumption loss; the scheme is simple and easy to implement, high in feasibility and compatibility, can be rapidly deployed on the existing PSE equipment, and is high in power calibration efficiency.
Fig. 2a is a schematic diagram of a power calibration method according to another exemplary embodiment of the present application, which is applicable to a calibration management device, and the method includes:
s201, acquiring a calibration request sent by a main control chip in a main control chip group, wherein the calibration request is used for indicating that a first PSE corresponding to the main control chip meets a power calibration condition;
s202, a calibration instruction is sent to the main control chip based on the calibration request so as to trigger the main control chip to acquire first output power of a first power supply unit and first load power of a first target load in the first PSE; calibrating a first rated power of the first PSE based on the first output power and the first load power; wherein a first output port of the first power supply unit is connected with the first target load.
Referring specifically to fig. 2b, the master control chip in step S202 may be any one of the master control chips in the master control chip group, and different master control chips in the master control chip group may have different PSE' S.
The specific rated power calibration process corresponding to this embodiment can be found in the foregoing, and will not be described herein.
Fig. 3 is a schematic diagram of a PSE-based power calibration apparatus according to an exemplary embodiment of the application, the apparatus comprising: a detection module 31, an acquisition module 32, and a calibration module 33; wherein:
the detecting module 31 is configured to detect whether the first PSE meets a power calibration condition, if yes, then
Acquiring, by the acquiring module 32, a first output power of a first power supply unit in the first PSE and a first load power of a first target load;
the calibration module 33 is configured to calibrate a first rated power of the first PSE based on the first output power and the first load power;
wherein a first output port of the first power supply unit is connected with the first target load.
Optionally, when the first power on flag is detected as a preset flag, determining that the first PSE meets a power calibration condition, or
When a first calibration switch of the first PSE is detected as being on, it is determined that the first PSE satisfies a power calibration condition.
Optionally, the calibration module 33 is specifically configured to, when configured to calibrate the first rated power of the first PSE based on the first output power and the first load power:
calculating a first deviation value of the first load power and the first output power;
and when the absolute value of the first deviation value is smaller than a first preset value, calibrating the first rated power based on the first deviation value.
Optionally, the device is further configured to: and if the first deviation value is not smaller than the first preset value, displaying the prompt information according to a preset prompt mode.
Optionally, the device is further configured to: detecting whether the second PSE meets the power calibration condition, if so, then
Acquiring a second output power of a second power supply unit in the second PSE and a second load power of the second target load;
calibrating a second rated power of the second PSE based on the second output power and the second load power;
wherein a second output port of the second power supply unit is connected with the second target load.
The foregoing may be referred to in the specific implementation manner corresponding to this embodiment, and will not be described herein.
An exemplary embodiment of the present application also provides a power calibration apparatus, including:
the system comprises an acquisition module, a power calibration module and a power calibration module, wherein the acquisition module is used for acquiring a calibration request sent by a main control chip in a main control chip group, wherein the calibration request is used for indicating that a first PSE corresponding to the main control chip meets a power calibration condition;
the transmitting module is used for transmitting a calibration instruction to the main control chip based on the calibration request so as to trigger the main control chip to acquire the first output power of the first power supply unit and the first load power of the first target load in the first PSE; calibrating a first rated power of the first PSE based on the first output power and the first load power; wherein a first output port of the first power supply unit is connected with the first target load.
The foregoing may be referred to in the specific implementation manner corresponding to this embodiment, and will not be described herein.
It should be understood that apparatus embodiments and method embodiments may correspond with each other and that similar descriptions may refer to the method embodiments. To avoid repetition, no further description is provided here. Specifically, the apparatus may perform the above method embodiments, and the foregoing and other operations and/or functions of each module in the apparatus are respectively for corresponding flows in each method in the above method embodiments, which are not described herein for brevity.
The apparatus of the embodiments of the present application is described above in terms of functional modules with reference to the accompanying drawings. It should be understood that the functional module may be implemented in hardware, or may be implemented by instructions in software, or may be implemented by a combination of hardware and software modules. Specifically, each step of the method embodiment in the embodiment of the present application may be implemented by an integrated logic circuit of hardware in a processor and/or an instruction in a software form, and the steps of the method disclosed in connection with the embodiment of the present application may be directly implemented as a hardware decoding processor or implemented by a combination of hardware and software modules in the decoding processor. Alternatively, the software modules may be located in a well-established storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, and the like. The storage medium is located in a memory, and the processor reads information in the memory, and in combination with hardware, performs the steps in the above method embodiments.
Further, the present application also provides a PSE, comprising: main control chip, first power supply unit, and first output port, wherein: the main control chip is used for detecting whether the first PSE meets a power calibration condition, and if so, acquiring first output power of a first power supply unit in the first PSE and first load power of a first target load; calibrating a first rated power of the first PSE based on the first output power and the first load power; wherein a first output port of the first power supply unit is connected with the first target load; the first power supply unit is used for supplying power to the first target load.
The foregoing details of the embodiment may be referred to in the foregoing description, and will not be described herein.
Fig. 4 is a schematic block diagram of an electronic device provided by an embodiment of the present application, which may include:
a memory 401 and a processor 402, the memory 401 being for storing a computer program and for transmitting the program code to the processor 402. In other words, the processor 402 may call and run a computer program from the memory 401 to implement the method in an embodiment of the present application.
For example, the processor 402 may be configured to perform the above-described method embodiments according to instructions in the computer program.
In some embodiments of the application, the processor 402 may include, but is not limited to:
a general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like.
In some embodiments of the application, the memory 401 includes, but is not limited to:
volatile memory and/or nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (Double Data Rate SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), and Direct memory bus RAM (DR RAM).
In some embodiments of the application, the computer program may be split into one or more modules that are stored in the memory 401 and executed by the processor 402 to perform the methods provided by the application. The one or more modules may be a series of computer program instruction segments capable of performing the specified functions, which are used to describe the execution of the computer program in the electronic device.
As shown in fig. 4, the electronic device may further include:
a transceiver 403, the transceiver 403 being connectable to the processor 402 or the memory 401.
The processor 402 may control the transceiver 403 to communicate with other devices, and in particular, may send information or data to other devices or receive information or data sent by other devices. The transceiver 403 may include a transmitter and a receiver. The transceiver 403 may further include antennas, the number of which may be one or more.
It will be appreciated that the various components in the electronic device are connected by a bus system that includes, in addition to a data bus, a power bus, a control bus, and a status signal bus.
The present application also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a computer, enables the computer to perform the method of the above-described method embodiments. Alternatively, embodiments of the present application also provide a computer program product comprising instructions which, when executed by a computer, cause the computer to perform the method of the method embodiments described above.
When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.
Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules illustrated as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. For example, functional modules in various embodiments of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily appreciate variations or alternatives within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. A power calibration method based on a power sourcing equipment PSE, comprising:
detecting whether the first PSE meets the power calibration condition, if so, then
Acquiring a first output power of a first power supply unit and a first load power of a first target load in the first PSE;
calibrating a first rated power of the first PSE based on the first output power and the first load power;
calibrating the first power rating of the first PSE based on the first output power and the first load power includes:
calculating a first deviation value of the first load power and the first output power;
when the absolute value of the first deviation value is smaller than a first preset value, taking the sum of the first deviation value and the first rated power as a calibrated first rated power;
if the first deviation value is not smaller than the first preset value, displaying prompt information according to a preset prompt mode;
wherein a first output port of the first power supply unit is connected with the first target load.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
when the first power-on sign is detected to be a preset sign, determining that the first PSE meets a power calibration condition, or
When a first calibration switch of the first PSE is detected as being on, it is determined that the first PSE satisfies a power calibration condition.
3. The method according to claim 1, wherein the method further comprises:
detecting whether the second PSE meets the power calibration condition, if so, then
Acquiring a second output power of a second power supply unit and a second load power of a second target load in the second PSE;
calibrating a second rated power of the second PSE based on the second output power and the second load power;
wherein a second output port of the second power supply unit is connected with the second target load.
4. A method of power calibration, comprising:
acquiring a calibration request sent by a main control chip in a main control chip group, wherein the calibration request is used for indicating that a first PSE corresponding to the main control chip meets a power calibration condition;
transmitting a calibration instruction to the main control chip based on the calibration request to trigger the main control chip to acquire a first output power of a first power supply unit and a first load power of a first target load in the first PSE; calibrating a first rated power of the first PSE based on the first output power and the first load power; wherein calibrating the first rated power of the first PSE based on the first output power and the first load power comprises: calculating a first deviation value of the first load power and the first output power, when the absolute value of the first deviation value is smaller than a first preset value, taking the sum of the first deviation value and the first rated power as a calibrated first rated power, and if the first deviation value is not smaller than the first preset value, displaying prompt information according to a preset prompt mode; the first output port of the first power supply unit is connected with the first target load.
5. A PSE-based power calibration device, comprising: the device comprises a detection module, an acquisition module and a calibration module; wherein:
the detection module is used for detecting whether the first PSE meets the power calibration condition, if so, then
Acquiring a first output power of a first power supply unit and a first load power of a first target load in the first PSE through the acquisition module;
the calibration module is used for calibrating a first rated power of the first PSE based on the first output power and the first load power;
the calibration module is used for calculating a first deviation value of the first load power and the first output power when being used for calibrating the first rated power of the first PSE based on the first output power and the first load power; when the absolute value of the first deviation value is smaller than a first preset value, taking the sum of the first deviation value and the first rated power as a calibrated first rated power; if the first deviation value is not smaller than the first preset value, displaying prompt information according to a preset prompt mode;
wherein a first output port of the first power supply unit is connected with the first target load.
6. A PSE comprising: main control chip, first power supply unit, and first output port, wherein:
the main control chip is used for detecting whether the first PSE meets a power calibration condition, and if so, acquiring first output power of a first power supply unit in the first PSE and first load power of a first target load; calibrating a first rated power of the first PSE based on the first output power and the first load power; wherein calibrating the first rated power of the first PSE based on the first output power and the first load power comprises: calculating a first deviation value of the first load power and the first output power; when the absolute value of the first deviation value is smaller than a first preset value, taking the sum of the first deviation value and the first rated power as a calibrated first rated power; if the first deviation value is not smaller than the first preset value, displaying prompt information according to a preset prompt mode; a first output port of the first power supply unit is connected with the first target load;
the first power supply unit is used for supplying power to the first target load.
7. An electronic device, comprising:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the method of any one of claims 1-3 or claim 4 via execution of the executable instructions.
8. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the method of any of claims 1-3 or 4.
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