CN114024289A - Over-temperature protection circuit and method for power management - Google Patents
Over-temperature protection circuit and method for power management Download PDFInfo
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- CN114024289A CN114024289A CN202111310156.6A CN202111310156A CN114024289A CN 114024289 A CN114024289 A CN 114024289A CN 202111310156 A CN202111310156 A CN 202111310156A CN 114024289 A CN114024289 A CN 114024289A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H5/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection
- H02H5/04—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H5/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection
- H02H5/04—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature
- H02H5/044—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature using a semiconductor device to sense the temperature
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Abstract
The invention discloses an over-temperature protection circuit for power supply management, which comprises a current input end, an over-temperature protection device, a comparator and a comparator output end, wherein the over-temperature protection device comprises a first port, a second port, a third port and a semiconductor device connected among the ports, when the voltage drop of the current input end is high potential, the comparator outputs low voltage, an LDO system works normally, when the temperature of the LDO system exceeds the normal working temperature, the voltage drop of the current input end is low potential, the comparator outputs high voltage, when the LDO system stops working, the voltage drop of the over-temperature protection device changes along with the temperature change, the voltage drop of the over-temperature protection device in the normal working temperature range is high conduction voltage drop, the current input end flows through the first port to be high potential, the over-temperature protection device is low conduction voltage drop in the high temperature state, the current input end flows through the first port to be low potential, the integration level is high, the production cost is low, and the working reliability of the LDO system for power management is improved.
Description
Technical Field
The invention relates to the technical field of power management systems, in particular to an over-temperature protection circuit and method for power management.
Background
With the continuous influx of portable electronic products such as mobile phones, notebook computers, MP3, etc. into people's daily life, how to effectively perform power management of these electronic products becomes a research focus, and under the trend that emerging electronic products are popular worldwide, the Power Management Chip (PMC) is more challenging due to its larger display screen and more complete functions. At present, the market has more than ten kinds of chips, and most commonly, there are several kinds of chips, including a charge pump, a switching regulator, a linear regulator (LDO), a Power Factor Correction (PFC) pre-regulator, a pulse width modulation Controller (PWM Controller), a pulse frequency modulation Controller (PFM Controller), and a Power Management Unit (PMU), among which the first three are widely applied and occupy a large market share.
The current portable electronic products generally require that a power management chip has the advantages of small size, few peripheral circuits, no ripple, no electromagnetic interference and the like, and a main circuit of the LDO chip, a band gap reference circuit, an error amplifier EA, a negative feedback resistance network and a power stage form the LDO chip. The over-temperature protection, the over-current protection and the short-circuit protection are three auxiliary functional modules of the LDO system, and the over-temperature/over-heat protection structure is mainly used for enabling the LDO system to pause working when the temperature is too high and preventing the LDO system from being damaged due to the too high temperature. Because LDO can be opened and stop work constantly and shock appears when shutting off the temperature for the excess temperature protection circuit of LDO system has the hysteresis function, makes the temperature that the system stopped working be higher than the system recovery operating temperature after the thermal shutdown, and the structure that plays excess temperature protection often needs two-sided technology, and a large amount of components and parts such as resistance need be connected to the device port, has increased the circuit cost of manufacture like this, also can lead to the work efficiency reduction of LDO system.
Disclosure of Invention
In view of the above, the present invention provides an over-temperature protection circuit and method for power management, which have a simple over-temperature protection structure, reduce system energy consumption, and have high operational reliability, so as to solve the above technical problems.
In a first aspect, the invention provides an over-temperature protection circuit for power management, comprising a current input terminal, an over-temperature protection device, a comparator and a comparator output terminal, wherein the over-temperature protection device comprises a first port connected with the current input terminal, a second port connected with the comparator and the comparator output terminal, a third port for grounding and a semiconductor device connected between the ports;
wherein the semiconductor device includes:
a substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on the substrate;
the epitaxial layer is provided with a first injection region of a first conductivity type formed in the epitaxial layer and a second injection region of a second conductivity type formed on the upper surface of the first injection region at intervals, and a silicon oxide layer correspondingly arranged is formed on the upper surface of the epitaxial layer and positioned between the second injection regions;
the first dielectric layer is formed on the epitaxial layer, the first injection region and part of the second injection region, the second dielectric layer is formed on the second injection region and the first injection region and is arranged at intervals with the first dielectric layer, and the first contact hole is positioned between the first dielectric layer and the second dielectric layer and is positioned on the upper surface of the second injection region;
a plurality of first polycrystalline silicon layers of a second conduction type and second polycrystalline silicon layers of a first conduction type which are sequentially staggered are formed on the upper surface of the silicon oxide layer, the second dielectric layers are symmetrically arranged relative to the second polycrystalline silicon layers, and the silicon oxide layer is positioned between the two second dielectric layers;
the second contact hole is formed on the upper surface of the first polycrystalline silicon layer connected with the second dielectric layer, and the third dielectric layer is positioned between the two second contact holes and covers the first polycrystalline silicon layer and the second polycrystalline silicon layer;
the metal layers are formed in the first contact hole, on the first dielectric layer, on the second dielectric layer, in the second contact hole and on part of the third dielectric layer, and are arranged at intervals, and the opening is positioned between the two metal layers.
In a second aspect, the present invention further provides an over-temperature protection method for an over-temperature protection circuit for power management, where the over-temperature protection method includes the following steps:
acquiring the working temperature of a power management system, and judging whether the working temperature exceeds the preset temperature for safe operation of the semiconductor device;
if not, the current of the current input end passes through the metal layer, the second injection region and a first current path where the first injection region is located to generate a first voltage drop, wherein the first voltage drop is smaller than the starting voltage of a second current path where the first polycrystalline silicon layer and the second polycrystalline silicon layer are located, and the second current path is not conducted;
if so, the starting voltage of the second current path is reduced, the first voltage drop is greater than the starting voltage, and the second current path is conducted;
and in a preset time, when the working temperature exceeds the preset temperature, the second voltage drop of the second current path is smaller than the first voltage drop, and the first current path is not conducted.
The invention provides an over-temperature protection circuit and a method for power supply management, which have the following beneficial effects compared with the prior art:
by adding the over-temperature protection device between the current input end and the comparator, the over-temperature protection device comprises three ports and semiconductor devices connected with the ports, the system is simple in structure, and the energy consumption of the system is reduced. The semiconductor device comprises a substrate and an epitaxial layer which is formed on the substrate and has a different conductivity type from the substrate, a first injection region and a second injection region which are arranged at intervals are formed in the epitaxial layer, a silicon oxide layer and a second dielectric layer are formed on the upper surface of the first injection region, a plurality of groups of PN junctions formed by a first polycrystalline silicon layer and a second polycrystalline silicon layer on the silicon oxide layer are isolated, and the current of a passage where a second current path is located is ensured to be uniformly distributed. When the current input end passes through a first current path formed by the first injection region and the second injection region, the voltage drop of the current passing through the first injection region is compared with the starting voltage of the second current path to determine whether the second current path where the multiple groups of PN junctions are located is conducted or not. The working temperature of the device exceeds the safe temperature, the working temperature is reduced to the recovery working temperature lower than the safe working temperature within the preset time, the working state of the device is controlled according to the starting voltage of the first current path and the second current path, and meanwhile, the starting voltage, the safe working temperature and the recovery working temperature of the channel can be realized by adjusting the doping concentration of a plurality of groups of transverse PN junctions on the polysilicon, the number of the PN junctions and the width of the PN junctions under various working temperatures of the LDO system. The over-temperature protection device is adopted to increase the effectiveness of over-temperature protection of the LDO system, the application range is wide, the integration level is high, the production cost is low, and the working reliability of the LDO system for power management is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of an over-temperature protection circuit for power management according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for over-temperature protection according to an embodiment of the present invention;
FIG. 4 is a current path diagram of an over-temperature protection device according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a first current path of an over-temperature protection device according to an embodiment of the present invention;
fig. 6 is a circuit diagram of a second current path of the over-temperature protection device according to the embodiment of the invention.
The main element symbols are as follows:
10-current input; 11-an over-temperature protection device; 12-a comparator; 13-comparator output; 15-a first port; 16-a second port; 17-a third port; 18-a semiconductor device; 20-a substrate; 21-epitaxial layer; 22-a first implanted region; 23-a second implanted region; a 24-silicon oxide layer; 25-a first dielectric layer; 26-a second dielectric layer; 27-a first polysilicon layer; 28-a second polysilicon layer; 29-a first contact hole; 30-a second contact hole; 31-a third dielectric layer; 33-a metal layer; 34-opening.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1 and 2, the present invention provides an over-temperature protection circuit for power management, including a current input terminal 10, an over-temperature protection device 11, a comparator 12 and a comparator output terminal 13, where the over-temperature protection device 11 includes a first port 15 connected to the current input terminal 10, a second port 16 connected to the comparator 12 and the comparator output terminal 13, a third port 17 for grounding, and a semiconductor device 18 connected between the ports;
when the voltage drop of the current input end 10 is a high potential, the comparator output end 13 outputs a low voltage, and the power management LDO system works normally;
when the temperature of the LDO system exceeds the normal working temperature, the voltage drop of the current input end 10 becomes a low potential, and the output end 13 of the comparator outputs a high voltage;
when the LDO system stops working, the voltage drop of the over-temperature protection device 11 changes along with the temperature change, the voltage drop of the over-temperature protection device 11 in the normal working temperature range is high conduction voltage drop, and the current input end 10 flows through the first port 15 and is high potential; the over-temperature protection device 11 is low in conduction voltage drop in a high-temperature state, and the current input end 10 flows through the first port 15 and is low in potential.
Wherein the semiconductor device 18 includes:
a substrate 20 of a first conductivity type, an epitaxial layer 21 of a second conductivity type formed on said substrate 20;
a first implantation region 22 of the first conductivity type formed in the epitaxial layer 21 and a second implantation region 23 of the second conductivity type formed at the upper surface of the first implantation region 22 at intervals, wherein a silicon oxide layer 24 correspondingly arranged is formed on the upper surface of the epitaxial layer 21 and between the second implantation regions 23;
a first dielectric layer 25 formed on the epitaxial layer 21, the first implantation region 22 and a part of the second implantation region 23, a second dielectric layer 26 formed on the second implantation region 23 and the first implantation region 22 and spaced from the first dielectric layer 25, and a first contact hole 29 located between the first dielectric layer 25 and the second dielectric layer 26 and located on the upper surface of the second implantation region 23;
a plurality of first polysilicon layers 27 of a second conductivity type and second polysilicon layers 28 of a first conductivity type, which are formed on the upper surface of the silicon oxide layer 24 and are sequentially staggered, wherein the second dielectric layers 26 are symmetrically arranged with respect to the second polysilicon layers 28, and the silicon oxide layer 24 is located between the two second dielectric layers 26;
a second contact hole 30 formed on the upper surface of the first polysilicon layer 27 connected to the second dielectric layer 26, and a third dielectric layer 31 located between the two second contact holes 30 and covering the first polysilicon layer 27 and the second polysilicon layer 28;
In this embodiment, the LDO, i.e., the low dropout regulator, is a low dropout linear regulator, and the LDO low dropout regulator has the characteristics of low cost, low noise, and small transient current, and if the input voltage and the output voltage are very close to each other, the LDO regulator is preferably selected, so that high efficiency can be achieved. Therefore, LDO regulators are often used in applications where the lithium ion battery voltage is converted to a 3V output voltage. Although the last ten percent of the energy of the battery is not used, the LDO voltage stabilizer can still ensure that the working time of the battery is longer and the noise is lower. The current input terminal 10 is a current bias circuit, the function of the bias circuit is to provide proper bias current for each amplification stage, determine the static operating point of each stage, the requirements of each amplification stage on the bias current are different, a smaller bias current can be provided for the input stage, and the bias current is more stable, so that the input resistance of the integrated operational amplifier is improved, and the input bias current and the input offset current are reduced. The comparator 12 is a circuit for comparing an analog voltage signal with another reference voltage, two inputs of the comparator 12 are analog signals, and the output is a binary signal 0 or 1, and when the difference between the input voltages increases or decreases and the signs are not changed, the output is kept constant. Comparator 12 may be considered a 1-bit analog-to-digital converter (ADC) and the operational amplifier may be used as a comparator when no feedback is applied. The input impedance of the comparator 12 is infinite, which theoretically does not affect the input signal, but the input impedance of the comparator 12 cannot be infinite, and the current at the input end passes through the internal resistance of the signal source and flows into the comparator, thereby generating an additional voltage difference.
It should be noted that the first conductivity type is P-type, the second conductivity type is N-type, the size of the first contact hole 29 is greater than the size of the second contact hole 30, the doping concentration of the first polysilicon layer 27 is the same as the doping concentration of the second polysilicon layer 28, the widths of the second contact hole 30, the first polysilicon layer 27 and the second polysilicon layer 28 are the same, the widths of the opening 34, the third dielectric layer 31 and the silicon oxide layer 24 in the direction parallel to the substrate 20 are sequentially increased, and the doping concentration of the second implantation region 23 is greater than the doping concentration of the epitaxial layer 21. The over-temperature protection device 11 comprises three ports, a first port 15 is connected with the current input end 10 through a port A, a second port 16 is connected with the comparator 12 and the output end 13 of the comparator through a port B, a third port 17 is grounded through a port C, a metal layer 33 in the semiconductor device 18 has two parts, the metal layer 33 located on the left side of an opening 34 is used for connecting leads of the port A and the port B, and the metal layer 33 located on the right side of the opening 34 is used for connecting leads of the port C. The first current path is composed of a metal layer 33, a second injection region 23, a first injection region 22, a second injection region 23 and the metal layer 33, the second current path is composed of a plurality of groups of PN junctions and the metal layer 33, the first polycrystalline silicon layer 27 and the second polycrystalline silicon layer 28, the first current path comprises an NPN structure, and the semiconductor device 18 can perform over-temperature protection on an LDO system for a power tube.
In addition, preferably, the number of the first polysilicon layers 27 is four, the number of the second polysilicon layers 28 is three, the first polysilicon layers 27 and the second polysilicon layers 28 are arranged in a staggered manner, the first polysilicon layers 27 and the second polysilicon layers 28 are just positioned on the upper surfaces of the silicon oxide layers 24, the size of the second contact hole 30 is just the same as the width of one first polysilicon layer 27, the width of the third dielectric layer 31 is the sum of the widths of the three first polysilicon layers 27 and the two second polysilicon layers 28, and the second dielectric layer 26 and the silicon oxide layers 24 isolate multiple groups of PN junctions formed by the first polysilicon layers 27 and the second polysilicon layers 28, so that leakage current is effectively prevented, and the working stability of the over-temperature protection device 11 is improved to a certain extent. The over-temperature protection device 11 can receive signals and clamp off a circuit, is a single-sided device, namely metal is prepared only on the front side, a double-sided manufacturing process is not needed, the integration level of the circuit is improved, and the packaging and manufacturing cost of the device is reduced.
It should be understood that the reference voltage is a reference voltage output by the LDO system, and when the voltage drop at the current input terminal 10 is high, the comparator output terminal 13 outputs a low voltage, and the LDO system operates normally. When the temperature of the LDO system is too high, that is, the operating temperature exceeds the preset temperature, the voltage drop at the current input terminal 10 will become a low potential, the comparator 12 outputs a high potential, and the LDO system stops operating. The voltage drop of the over-temperature protection device 11 will change with the temperature change, and in the normal working temperature range, i.e. the preset temperature is a high conduction voltage drop, and the current input end 10 is a high potential when flowing through the first port 15. In the high temperature state, the conduction voltage drop is low, and the current input terminal 10 is at low potential when flowing through the first port 15. In an actual circuit, if the output of the over-temperature protection circuit is "0", it indicates that the temperature in the system is too high, and the system stops working, whereas if the output of the over-temperature protection circuit is "1", it indicates that the internal temperature of the LDO system is normal, and the system can work normally. The single current bias circuit can reduce the power consumption, the temperature inside the LDO system is detected by a temperature sensitive device (such as VBE of a transistor) traditionally, when the working temperature of the LDO system exceeds the normal working temperature, the device is started, and when the LDO system stops working until the working temperature is reduced to the recovery working temperature, the system can work normally again. Adopt neotype excess temperature protection device 11 can replace traditional triode and resistance combination, system structure is simple, has reduced manufacturing cost, has also improved the reliability of LDO system work.
Referring to fig. 3, the present invention further provides an over-temperature protection method for an over-temperature protection circuit for power management, the over-temperature protection method including the steps of:
s1: acquiring the working temperature of a power management system, and judging whether the working temperature exceeds the preset temperature for safe operation of the semiconductor device 18;
s2: if not, the current of the current input terminal 10 generates a first voltage drop through a first current path in which the metal layer 33, the second injection region 23 and the first injection region 22 are located, the first voltage drop is smaller than the turn-on voltage of a second current path in which the first polysilicon layer 27 and the second polysilicon layer 28 are located, and the second current path is not conducted;
s3: if so, the starting voltage of the second current path is reduced, the first voltage drop is greater than the starting voltage, and the second current path is conducted;
s4: and in a preset time, when the working temperature exceeds the preset temperature, the second voltage drop of the second current path is smaller than the first voltage drop, and the first current path is not conducted.
Referring to fig. 4, in the embodiment, when the over-temperature protection device 11 operates at the safe operating temperature, a voltage drop is denoted as V1 when a current flows through the first injection region 22, V1 is smaller than a start-up voltage of a second current path denoted as V2, the second current path is formed by forming a plurality of PN junctions composed of a plurality of polysilicon layers with different conductivity types on the silicon oxide layer 24, the first polysilicon layer 27 is connected to the second dielectric layer 26, and preferably, the number of the first polysilicon layer 27 is greater than that of the second polysilicon layer 28. V1 will be less than V2 in the safe operating temperature, and the multiunit PN junction breakdown voltage and the voltage drop of conducting on silicon oxide layer 24 will decline fast along with the temperature rise, and after the device operating temperature exceeded safe operating temperature, the opening voltage V2 of second current path will decline, makes V1 be greater than V2, and the second current path is opened. And at high temperature, the voltage drop of the second current path is smaller than that of the first current path, and the first current path cannot be opened.
Optionally, the turn-on voltage of the second current path decreases, including:
when the working temperature rises, the transverse multiple groups of PN junctions formed by the first polysilicon layer 27 and the second polysilicon layer 28 rise along with the temperature, when the working temperature exceeds the safe working temperature, the transverse multiple groups of PN junctions are broken down, and the starting voltage is reduced.
Referring to fig. 5, in the present embodiment, at the normal operating temperature, the turn-on voltage of the second current path is high, the second port 16, i.e., the port B, of the LDO system is in a low voltage state, and the second current path is not turned on. When the working temperature of the LDO system rises, the multiple groups of lateral PN junctions on the silicon oxide layer 24 rise with the temperature, the carriers increase, the leakage current also increases, and when the working temperature exceeds the safe working temperature T1, the carriers increase in response due to high temperature, the PN junctions break down, the turn-on voltage decreases, the path where the second current path is located is turned on, the conduction voltage drop is lower than that of the current path at normal temperature, and the output of the comparator 12, that is, the second port 16, becomes a high voltage state, and the conduction of the path is maintained. When the temperature of the LDO system is reduced to the safe working temperature T1, the opening voltages of the multiple groups of PN junctions are increased, but the path is always conducted due to the high voltage of the second port 16, and the opening voltages of the multiple groups of PN junctions exceed the high voltage of the second port 16 until the temperature of the LDO system is reduced to the recovery working temperature T2 lower than the safe working temperature T1, namely the second current path is cut off. After the current path is cut off, the output end 13 of the comparator outputs low voltage, and the LDO system works normally.
It should be noted that the opening voltage, the safe operating temperature and the recovery operating temperature are changed by adjusting the doping concentration of the plurality of transverse groups of PN junctions, the number of PN junctions and the width of PN junctions, and the preset temperature is the safe operating temperature of the power management system. The safe working temperature T1 is greater than the recovery working temperature T2, so that the system can be recovered to operate only when the temperature of the LDO system is reduced to a lower degree after the temperature is over-temperature, and the reliability and safety redundancy of the system are increased.
Referring to fig. 6, when the temperature of the LDO system is normal, the turn-on voltages of the multiple PN junctions on the silicon oxide layer 24 are greater than the sum of the low voltage input from the second port 16 and the voltage drop of the second current path, the second current path cannot be turned on, the current is conducted through the first current path, the path is composed of a group of PN junctions, the turn-on voltage is low, the voltage drop after conduction is high due to low doping concentration after turn-on, and the path where the first current path is located can be consistently turned on as long as the LDO system operates within the normal temperature range and the low voltage is input from the second port 16.
The invention provides an over-temperature protection circuit and method for power supply management, wherein an over-temperature protection device 11 is added between a current input end 10 and a comparator 12, the over-temperature protection device 11 comprises three ports and semiconductor devices 18 connected with the ports, the system structure is simple, and the system energy consumption is reduced. The semiconductor device 18 comprises a substrate 20, an epitaxial layer 21 formed on the substrate 20 and having a different conductivity type from the substrate, a first injection region 22 formed in the epitaxial layer 21 and a second injection region 23 formed in the first injection region 22 and arranged at intervals, wherein a silicon oxide layer 24 and a second dielectric layer 26 are formed on the upper surface of the first injection region 22 and isolate a plurality of PN junctions formed by a first polysilicon layer 27 and a second polysilicon layer 28 on the silicon oxide layer 24, so that the current of a path where a second current path is located is uniformly distributed. When the current of the current input end 10 passes through a first current path formed by the first injection region 22 and the second injection region 23, the voltage drop of the current passing through the first injection region 22 is compared with the turn-on voltage of the second current path to determine whether the second current path where the multiple groups of PN junctions are located is conducted. The working temperature of the device exceeds the safe temperature, the working temperature is reduced to the recovery working temperature lower than the safe working temperature within the preset time, the working state of the device is controlled according to the starting voltage of the first current path and the second current path, and meanwhile, the starting voltage, the safe working temperature and the recovery working temperature of the channel can be realized by adjusting the doping concentration of a plurality of groups of transverse PN junctions on the polysilicon, the number of the PN junctions and the width of the PN junctions under various working temperatures of the LDO system. The over-temperature protection device 11 is adopted to increase the effectiveness of over-temperature protection of the LDO system, the application range is wide, the integration level is high, the production cost is low, and the working reliability of the LDO system for power management is improved.
In all examples shown and described herein, any particular value should be construed as merely exemplary, and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
Claims (10)
1. An over-temperature protection circuit for power supply management, which is characterized by comprising a current input end, an over-temperature protection device, a comparator and a comparator output end, wherein the over-temperature protection device comprises a first port connected with the current input end, a second port connected with the comparator and the comparator output end, a third port used for grounding and a semiconductor device connected among the ports;
wherein the semiconductor device includes:
a substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on the substrate;
the epitaxial layer is provided with a first injection region of a first conductivity type formed in the epitaxial layer and a second injection region of a second conductivity type formed on the upper surface of the first injection region at intervals, and a silicon oxide layer correspondingly arranged is formed on the upper surface of the epitaxial layer and positioned between the second injection regions;
the first dielectric layer is formed on the epitaxial layer, the first injection region and part of the second injection region, the second dielectric layer is formed on the second injection region and the first injection region and is arranged at intervals with the first dielectric layer, and the first contact hole is positioned between the first dielectric layer and the second dielectric layer and is positioned on the upper surface of the second injection region;
a plurality of first polycrystalline silicon layers of a second conduction type and second polycrystalline silicon layers of a first conduction type which are sequentially staggered are formed on the upper surface of the silicon oxide layer, the second dielectric layers are symmetrically arranged relative to the second polycrystalline silicon layers, and the silicon oxide layer is positioned between the two second dielectric layers;
the second contact hole is formed on the upper surface of the first polycrystalline silicon layer connected with the second dielectric layer, and the third dielectric layer is positioned between the two second contact holes and covers the first polycrystalline silicon layer and the second polycrystalline silicon layer;
the metal layers are formed in the first contact hole, on the first dielectric layer, on the second dielectric layer, in the second contact hole and on part of the third dielectric layer, and are arranged at intervals, and the opening is positioned between the two metal layers.
2. The over-temperature protection circuit for power management as claimed in claim 1, wherein when the voltage drop at the current input terminal is high, the comparator output terminal outputs a low voltage, and the power management LDO system operates normally;
when the temperature of the LDO system exceeds the normal working temperature, the voltage drop of the current input end becomes a low potential, and the output end of the comparator outputs high voltage;
when the LDO system stops working, the voltage drop of the over-temperature protection device changes along with the temperature change, the voltage drop of the over-temperature protection device in the normal working temperature range is high conduction voltage drop, and the current input end flows through the first port and is high potential; the over-temperature protection device is low in conduction voltage drop in a high-temperature state, and the current input end flows through the first port and is low in potential.
3. The over-temperature protection circuit for power management of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type, and wherein the size of the first contact hole is larger than the size of the second contact hole.
4. The over-temperature protection circuit for power management of claim 1, wherein a doping concentration of the first polysilicon layer is the same as a doping concentration of the second polysilicon layer.
5. The over-temperature protection circuit for power management of claim 1, wherein the second contact hole, the first polysilicon layer and the second polysilicon layer have the same width.
6. The over-temperature protection circuit for power management of claim 1, wherein the width of the opening, the third dielectric layer and the silicon oxide layer in a direction parallel to the substrate increases in sequence.
7. The over-temperature protection circuit for power management of claim 1, wherein a doping concentration of the second implanted region is greater than a doping concentration of the epitaxial layer.
8. An over-temperature protection method of an over-temperature protection circuit for power supply management according to any one of claims 1 to 7, wherein the over-temperature protection method comprises the following steps:
acquiring the working temperature of a power management system, and judging whether the working temperature exceeds the preset temperature for safe operation of the semiconductor device;
if not, the current of the current input end passes through the metal layer, the second injection region and a first current path where the first injection region is located to generate a first voltage drop, wherein the first voltage drop is smaller than the starting voltage of a second current path where the first polycrystalline silicon layer and the second polycrystalline silicon layer are located, and the second current path is not conducted;
if so, the starting voltage of the second current path is reduced, the first voltage drop is greater than the starting voltage, and the second current path is conducted;
and in a preset time, when the working temperature exceeds the preset temperature, the second voltage drop of the second current path is smaller than the first voltage drop, and the first current path is not conducted.
9. The over-temperature protection method of claim 7, wherein the turn-on voltage of the second current path is reduced, comprising:
when the working temperature rises, the transverse multiple groups of PN junctions formed by the first polycrystalline silicon layer and the second polycrystalline silicon layer rise along with the temperature, when the working temperature exceeds the safe working temperature, the transverse multiple groups of PN junctions are broken down, and the starting voltage is reduced.
10. The over-temperature protection method according to claim 9, wherein the starting voltage, the safe operating temperature and the recovery operating temperature are changed by adjusting doping concentration of the plurality of transverse sets of PN junctions, the number of PN junctions and the width of the PN junctions, and the preset temperature is the safe operating temperature of the power management system.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012043085A (en) * | 2010-08-17 | 2012-03-01 | Toppan Printing Co Ltd | Voltage regulator circuit |
| US20190006511A1 (en) * | 2017-06-29 | 2019-01-03 | Texas Instruments Incorporated | Programmable non-volatile memory with low off current |
| CN112310940A (en) * | 2020-11-12 | 2021-02-02 | 武汉度美迪新能源科技有限公司 | Over-temperature protection circuit, method and system for LDO system |
| CN112332367A (en) * | 2020-11-12 | 2021-02-05 | 武汉度美迪新能源科技有限公司 | Over-temperature protection circuit, method and device for LDO system |
-
2021
- 2021-11-05 CN CN202111310156.6A patent/CN114024289B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012043085A (en) * | 2010-08-17 | 2012-03-01 | Toppan Printing Co Ltd | Voltage regulator circuit |
| US20190006511A1 (en) * | 2017-06-29 | 2019-01-03 | Texas Instruments Incorporated | Programmable non-volatile memory with low off current |
| CN112310940A (en) * | 2020-11-12 | 2021-02-02 | 武汉度美迪新能源科技有限公司 | Over-temperature protection circuit, method and system for LDO system |
| CN112332367A (en) * | 2020-11-12 | 2021-02-05 | 武汉度美迪新能源科技有限公司 | Over-temperature protection circuit, method and device for LDO system |
| CN113381383A (en) * | 2020-11-12 | 2021-09-10 | 深圳市视景达科技有限公司 | Over-temperature protection circuit, method and system for LDO system |
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