CN114023708A

CN114023708A - Semiconductor packaging structure

Info

Publication number: CN114023708A
Application number: CN202111101312.8A
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-09-18
Filing date: 2021-09-18
Publication date: 2022-02-08

Abstract

The invention relates to a semiconductor packaging structure. The semiconductor package structure includes: a circuit layer; the first chip and the second chip are positioned above the circuit layer; and the strengthening structure is positioned below the first chip and the second chip and is propped against the lower surface of the first chip, the lower surface of the second chip and the upper surface of the circuit layer.

Description

Semiconductor packaging structure

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor packaging structure.

Background

In an existing semiconductor package structure, for example, a FoCoS (Fan-Out Chip-on-Substrate) package structure as shown in fig. 1, a first Chip 12 such as an ASIC (Application Specific Integrated Circuit) and a second Chip 14 such as an HBM (High Bandwidth Memory) are located on a redistribution line (RDL) layer 24 on a Substrate 22. The lower portions of the first chip 12 and the second chip 14 are surrounded by the underfill 30. Warpage (warp) occurs during thermal cycling because of CTE (coefficient of thermal expansion) mismatch between materials. Since the overall package structure cannot directly release the stress caused by warpage, the underfill (Under-Fill) at the stress concentration point between the first chip 12 and the second chip 14 is prone to generate Crack (Crack)29, and the Crack 29 may extend downward to damage the dielectric layer and the RDL in the redistribution layer 24.

One way to solve the above-mentioned crack problem is to provide a Reinforcement (strengthening) structure 35 on the RDL layer below the space between the first chip 12 and the second chip 14, wherein the Reinforcement structure 35 can block the path of the crack 29 of the underfill 30 to prevent the redistribution layer 24 from being damaged downward. However, this approach does not prevent the delamination (delam) and cracking problems of the underfill.

Disclosure of Invention

In view of the above problems in the related art, the present invention provides a semiconductor package structure and a method for forming the same.

According to an aspect of an embodiment of the present invention, there is provided a semiconductor package structure including: a circuit layer; the first chip and the second chip are positioned above the circuit layer; and the strengthening structure is positioned below the first chip and the second chip. The strengthening structure is abutted against the lower surface of the first chip, the lower surface of the second chip and the upper surface of the circuit layer.

In some embodiments, the upper surface of the line layer includes a recess, and the reinforcing structure is disposed within the recess.

In some embodiments, the semiconductor package structure further includes an underfill encapsulating at least the stiffener structure.

In some embodiments, the underfill extends into the recess.

In some embodiments, the trace layer includes a bridge trace extending from beneath the first chip to beneath the second chip, wherein the stiffener structure is located above the bridge trace.

In some embodiments, the reinforcing structure has a first adhesive layer at an upper surface thereof in contact with a lower surface of the first chip and a lower surface of the second chip.

In some embodiments, the reinforcing structure has a second adhesive layer at a lower surface thereof in contact with an upper surface of the layer of wires.

In some embodiments, the stiffening structure is attached to the upper surface of the wiring layer by electrical connections.

In some embodiments, the reinforcing structure includes a passive element.

In some embodiments, the reinforcing structure includes a third chip.

In some embodiments, the reinforcing structure includes a first reinforcing structure and a second reinforcing structure that are spaced apart. The first strengthening structure is propped against the lower surface of the first chip and the upper surface of the circuit layer, and the second strengthening structure is propped against the lower surface of the second chip and the upper surface of the circuit layer.

In some embodiments, the semiconductor package structure further includes a protective layer surrounding the first chip and the second chip.

According to another aspect of the embodiments of the present invention, there is also provided a method of forming a semiconductor package structure, including: forming a dielectric layer defining a recess and a metal wiring in the dielectric layer on a carrier to form a wiring layer including a recess; placing a reinforcing structure within the recess; and bonding the first chip and the second chip above the circuit layer, wherein the lower surface of the first chip and the lower surface of the second chip are pressed against the strengthening structure.

In some embodiments, forming a dielectric layer defining a recess and a metal line in the dielectric layer includes: forming a first metal line of the metal lines on the carrier; forming a first dielectric layer in the dielectric layer on the first metal circuit, wherein the first dielectric layer is provided with a first opening; forming a via hole penetrating the first dielectric layer to the first metal wiring and a second metal wiring located on the first dielectric layer and connected to the metal wiring of the via hole; a second dielectric layer in the dielectric layer is covered over the second metal line, the second dielectric layer having a second opening over the first opening, the recess including the first opening and the second opening.

In some embodiments, the first metal line includes a bridge line, and the first opening exposes the bridge line.

In some embodiments, the method of forming a semiconductor package structure further comprises: an underfill is formed that encapsulates at least the reinforcing structure.

In some embodiments, placing the reinforcing structure within the recess comprises: the reinforcing structure is adhered into the recess by an adhesive layer at a lower surface of the reinforcing structure.

In some embodiments, placing the reinforcing structure within the recess comprises: the reinforcing structure is bonded to the metal wiring under the recess portion by an electrical connector.

In some embodiments, the method of forming a semiconductor package structure further comprises: bonding the structure on the carrier to a second carrier; removing the carrier to expose the circuit layer; a substrate is attached on the exposed surface of the wiring layer.

In some embodiments, the method of forming a semiconductor package structure further comprises: a protective layer is formed surrounding the first chip and the second chip.

In the semiconductor package structure of the present invention, the reinforcing structure is disposed against the lower surfaces of the first chip 132 and the second chip, so that there is no gap for forming the underfill between the circuit layer and the first chip and the second chip. Additional effects, such as thermal bending forces during heat treatment, can thereby be overcome. The problem of bottom filler layering and crackle in the existing packaging structure is avoided.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a schematic diagram of a conventional semiconductor package structure.

Fig. 2A is a schematic diagram of a semiconductor package structure according to an embodiment of the invention.

Fig. 2B is an enlarged view of a region S1 of the semiconductor package structure of fig. 2A.

Fig. 2C is a perspective view of the semiconductor package structure of fig. 2A.

Fig. 2D is a schematic top view of the semiconductor package structure of fig. 2A at section a-a.

Fig. 3A and 3B are schematic diagrams of a reinforcing structure of a semiconductor package structure according to other embodiments of the invention.

Fig. 4A to 4C are schematic views of a reinforcing structure of a semiconductor package structure according to other embodiments of the invention.

Fig. 5A to 5H are schematic views of a reinforcing structure of a semiconductor package structure according to other embodiments of the invention.

Fig. 6A-6W illustrate schematic diagrams of stages of a method of forming a semiconductor package structure according to an embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Fig. 2A is a schematic diagram of a semiconductor package structure according to an embodiment of the invention. Fig. 2B is an enlarged view of a region S1 of the semiconductor package structure of fig. 2A. As shown in fig. 2A and 2B, the semiconductor package structure in fig. 2A includes a circuit layer 120 on a substrate 110. In some embodiments, the line layer 120 is an RDL layer. The first chip 132 and the second chip 134 are bonded over the wiring layer 120. The first chip 132 and the second chip 134 may have different sizes or thicknesses, and the top surfaces of the first chip 132 and the second chip 134 may not be flush. In the illustrated embodiment, first chip 132 and second chip 134 are bonded to wiring layer 120 by electrical connections 142. The electrical connections 142 may include pads, solder, and micro bumps (μ Bump), among others. A reinforcing structure 150 is disposed under the first chip 132 and the second chip 134. Reinforcing structure 150 is located under the space between first chip 132 and second chip 134. The reinforcing structure 150 is disposed against the lower surface of the first chip 132, the lower surface of the second chip 134, and the upper surface of the circuit layer 120.

In the semiconductor package structure of the present invention, the reinforcing structure 150 is disposed against the lower surfaces of the first chip 132 and the second chip 134, so as to directly contact the adjacent corners of the first chip 132 and the second chip 134, and therefore, there is no gap for forming an underfill between the circuit layer 120 and the first chip 132 and the second chip 134. Additional effects, such as thermal bending forces during heat treatment, can thereby be overcome. The upper surface of the reinforcing structure 150 may resist stress generated by thermal bending of the first chip 132 and the second chip 134. The problem of bottom filler layering and crackle in the existing packaging structure is avoided. The stress blocking effect of the package structure with the reinforcing structure 150 provided by the invention is 4-5 times that of the package structure without the reinforcing structure 150.

Referring to fig. 2A and 2B, the underfill 145 encapsulates at least the reinforcing structure 150. Underfill 145 also encapsulates the lower portions of first chip 132 and second chip 134, as well as electrical connections 142 between first chip 132 and second chip 134 and wiring layer 120. In some embodiments, the underfill 145 may be an organic photosensitive material, or/and a photosensitive liquid material, or/and a dry film material. In some embodiments, the underfill 145 may be: organics such as PI, epoxy, acrylic, ABF, PP; and/or moulding compounds based on inorganic substances, such as oxides (SiOx, SiNx, TaOx), glass, silicon, ceramics, etc. Protective layer 148 surrounds first chip 132, second chip 134, and underfill 145. In some embodiments, the protective layer 148 may be an organic photosensitive material, or/and a photosensitive liquid material, or/and a dry film material. In some embodiments, the protective layer 148 may be: organic substances such as PI (polyimide), epoxy, acrylic, ABF, PP (polypropylene); and/or moulding compounds based on inorganic substances, such as oxides (SiOx, SiNx, TaOx), glass, silicon, ceramics, etc.

A first adhesive layer 161 may be disposed on the upper surface of the reinforcing structure 150, and a second adhesive layer 162 may be disposed on the lower surface of the reinforcing structure 150. In some embodiments, the material of the reinforcing structure 150 may be a metal (copper, silver, stainless steel, silver, nickel, iron, solder, aluminum alloy, etc.) or a non-metal (e.g., ceramic, silicon, glass, oxide: SiOx, SiNx, TaOx, etc.) with a higher Young's modulus than that of the underfill 145. The first adhesive layer 161 contacts the lower surface of the first chip 132 and the lower surface of the second chip 134. The second adhesive layer 162 contacts the upper surface of the circuit layer 120.

Fig. 2C is a perspective view of the semiconductor package structure of fig. 2A. As shown in fig. 2A to 2C, the upper surface of the wiring layer 120 includes a recess 129. The recess 129 is located below the space between the first chip 132 and the second chip 134. The reinforcing structure 150 is disposed within the recess 129. The underfill 145 extends into the recess 129. The reinforcing structure 150 may extend along the space between the first chip 132 and the second chip 134. In consideration of the thickness, the reinforcing structure 150 is disposed in the recess 129 of the circuit layer 120, so that unnecessary high conductive pillars or micro bumps can be avoided to adapt to the thickness of the reinforcing structure 150.

Fig. 2D is a schematic top view of the semiconductor package structure of fig. 2A at section a-a. As shown in fig. 2B to 2D, the circuit layer 120 includes a bridge circuit 125 extending from below the first chip 132 to below the second chip 134. The bridge wire 125 may be exposed by the recess 129. The number of bridge lines 125 may be plural. The number of the reinforcing structures 150 may be plural. In some embodiments, the line width/line spacing (L/S) of bridging line 125 is less than 2 μm/2 μm. Reinforcing structure 150 is located above bridge trace 125. A plurality of bridge lines 125 may be disposed under each reinforcing structure 150. In some embodiments, the second adhesive layer 162 at the lower surface of the reinforcing structure 150 may be in direct contact with the bridge circuit 125. By providing reinforcing structure 150 on bridge wires 125, bridge wires 125 may be protected. By providing a plurality of reinforcing structures 150 at intervals in the recess 129, it is possible to increase the bonding area of the underfill 145 to obtain good reliability performance.

In some embodiments, the overall dimensions of the package structure of fig. 2A are the same as the width of the substrate 110, and range between 50mm to 80 mm. In addition, fig. 2B also illustrates some other exemplary dimensional configurations. As shown in fig. 2B, the interval CG between the first chip 132 and the second chip 134 is in the range of 20 μm to 200 μm, and the interval BG between the lower surface of the chip and the upper surface of the wiring layer 120 is in the range of 30 μm to 100 μm. The dimension CZ of the recess 129 is in the range between 5mm and 60 mm. The line width L (not shown) of the bridge wire 125 may be in a range between 0.5 μm and 10 μm, the line Pitch S (not shown) may be in a range between 0.5 μm and 10 μm, and the Pitch (Pitch) (not shown) may be in a range between 1 μm and 20 μm. The thickness (BT) of bridging line 125 may be in the range between 1 μm and 10 μm. The thickness AT of the first adhesive layer 161 or the second adhesive layer 162 may be in a range between 2 μm and 5 μm.

The circuit layer 120 includes a first dielectric layer 121 and a second dielectric layer 122 over the first dielectric layer 121. The thickness TDT of the second dielectric layer 122 in the line layer 120 may be in a range between 5 μm and 20 μm. The thickness IDT of the first dielectric layer 121 under the second dielectric layer 122 in the line layer 120 may be in a range between 5 μm and 20 μm. The distance DCD between the reinforcing structure 150 and the sidewall of the recess 129 may be in the range of 5 μm to 10 μm, and the angle θ of the recess 129 may be in the range of 30 ° to 85 °. The thickness RT of the reinforcing structure 150 may be in the range of between 30 μm and 200 μm, and the dimension RS of the reinforcing structure 150 may be in the range of between 2mm and 5 mm. The ratio between the dimension CZ of the recess 129 and the dimension RS of the reinforcing structure 150 may be in the range of 2 to 10.

Fig. 3A and 3B are schematic diagrams of a reinforcing structure of a semiconductor package structure according to other embodiments of the invention. As shown in fig. 3A, the stiffener structure 150 is attached to the upper surface of the wiring layer 120 by electrical connections 143. In this embodiment, the reinforcing structure 150 may be a chip (third chip), and the first adhesive layer 161 covers the chip. As shown in fig. 3B, the stiffener structure 150 is attached to the upper surface of the wiring layer 120 by electrical connections 142. In this embodiment, the reinforcing structure 150 may be a passive component, and the first adhesive layer 161 is disposed on the passive component. In some embodiments, the passive element may be a resistive element. In the embodiment shown in fig. 3A and 3B, the first dielectric layer 121 of the line layer 120 covers the bridge line 125. In some embodiments, the first dielectric layer 121 covering the bridge circuit 125 may be an organic photosensitive material, or/and a photosensitive liquid material, or/and a dry film material. In some embodiments, the first dielectric layer 121 may be: organics such as PI, epoxy, acrylic, ABF, PP; and/or moulding compounds based on inorganic substances, such as oxides (SiOx, SiNx, TaOx), glass, silicon, ceramics, etc.

Fig. 4A to 4C are schematic views of a reinforcing structure of a semiconductor package structure according to other embodiments of the invention. As shown in fig. 4A, the reinforcing structure 150 includes a first reinforcing structure 151 and a second reinforcing structure 152 disposed at an interval, wherein the first reinforcing structure 151 abuts against the lower surface of the first chip 132 and the upper surface of the circuit layer 120, and the second reinforcing structure 152 abuts against the lower surface of the second chip 134 and the upper surface of the circuit layer 120. The bridge wiring 125 is exposed by the recess 129. In this embodiment, the first adhesive layer 161 is disposed on the upper surfaces of the first reinforcing structure 151 and the second reinforcing structure 152, and the second adhesive layer 162 is disposed under the lower surfaces of the first reinforcing structure 151 and the second reinforcing structure 152. As shown in fig. 4B, the first reinforcing structure 151 and the second reinforcing structure 152 are attached to the upper surface of the wiring layer 120 by the electrical connection members 143. The first reinforcing structure 151 and the second reinforcing structure 152 may be chips (third chips). As shown in fig. 4C, the first reinforcing structure 151 and the second reinforcing structure 152 are passive elements. In some embodiments, the passive element may be a resistive element. The first reinforcing structure 151 and the second reinforcing structure 152 are attached to the upper surface of the wiring layer 120 by the electrical connection members 142. In the embodiment shown in fig. 4B and 4C, the first dielectric layer 121 of the line layer 120 covers the bridge line 125.

Fig. 5A to 5H are schematic views of a reinforcing structure of a semiconductor package structure according to other embodiments of the invention. As shown in fig. 5A, unlike the embodiment shown in fig. 2A, the protective layer 148 does not cover the top surfaces of the first and

second chips

132 and 134, and the protective layer 148 surrounds only the lower portions of the first and

second chips

132 and 134 and the underfill 145. As shown in fig. 5B, the protective layer 148 may be flush with the top surface of the higher one 134 of the first chip 132 and the second chip 134. As shown in fig. 5C, the sidewalls of the protective layer 148 are not aligned with the sidewalls of the substrate 110, and the sidewalls of the protective layer 148 are aligned with the edges of the underfill 145. As shown in fig. 5D, the underfill 145 may not be provided, and only the protective layer 148 is provided to encapsulate the first chip 132, the second chip 134 and the reinforcing structure 150. As shown in fig. 5E, the protection layer 148 may not be provided, and only the underfill 145 may be provided to cover the lower portions of the first chip 132 and the second chip 134 and the reinforcing structure 150. As shown in fig. 5F, underfill 145 may cover only reinforcing structure 150. As shown in fig. 5G, underfill 145 encapsulates reinforcing structure 150 and a lower portion of one of first chip 132 and second chip 134 (e.g., first chip 132). As shown in fig. 5H, the underfill 145 may expose a sidewall of the lower one 134 of the first chip 132 and the second chip 134, and the lower one 134 of the first chip 132 and the second chip 134 may be bonded to the wiring layer 120 by a wire 147. Other aspects of the embodiment of fig. 5A-5H may be similar to the embodiment shown in fig. 2A.

Embodiments of the invention also provide methods of forming semiconductor package structures. Fig. 6A-6W illustrate schematic diagrams of stages of a method of forming a semiconductor package structure according to an embodiment of the invention.

As shown in fig. 6A, a first seed layer 611 is covered on the first carrier 601, and a first photomask layer 621 is covered on the first seed layer 611. As shown in fig. 6B, the first photo mask layer 621 is patterned to form the first photo mask layer 621 having a plurality of openings 631. The opening 631 is filled with a metal material 699. As shown in fig. 6C, the first photo mask layer 621 and the first seed layer 611 under the first photo mask layer 621 are removed. Thereafter, a first metal line 124 including the first seed layer 611 and a first metal layer 641 on the first seed layer 611 is formed, wherein the first metal line 124 includes a bridge line 125.

As shown in fig. 6D, a first dielectric layer 121 is covered on the first metal line 124. As shown in fig. 6E, a plurality of openings 632 exposing the first metal lines 124 are formed in the first dielectric layer 121. A second seed layer 612 is overlying the first dielectric layer 121 and within the plurality of openings 632. As shown in fig. 6F, a second photomask layer 622 is formed on the second seed layer 612. As shown in fig. 6G, the second photomask 622 is patterned, and a plurality of openings 633 exposing the second seed layer 612 are formed in the second photomask 622. After patterning, a second photomask 622 covers over the bridge line 125. The plurality of openings 633 are filled with a metal material 699. As shown in fig. 6H, the second photomask layer 622 and the second seed layer 612 under the second photomask layer 622 are removed. The metal material 699 and the second seed layer 612 within the opening 633 form a via connected to the first metal line 124, and the second seed layer 612 and the metal material 699 on the first dielectric layer 121 form the second metal line 126. The second dielectric layer 122 is covered on the first dielectric layer 121, the bridge wiring 125, and the second metal wiring 126. As shown in fig. 6I, a plurality of openings 634 exposing the second metal lines 126 and the bridge lines 125 are formed in the second dielectric layer 122. A third seed layer 613 is overlying the second dielectric layer 122 and within the plurality of openings 634. As shown in fig. 6J, a third photo mask layer 623 is covered on the third seed layer 613.

As shown in fig. 6K, the third photo mask layer 623 is patterned, and a plurality of openings 635 are formed in the third photo mask layer 623. The opening 635 is not formed over the bridge circuit 125, and the third photo mask layer 623 shields the

openings

632, 634 over the bridge circuit 125. The opening 635 of the third photo mask layer 623 is filled with a metal material 699 and solder 698. As shown in fig. 6L, the third photo mask layer 623 and the third seed layer 613 covered by the third photo mask layer 623 are removed. At this time, the

openings

632, 634 in the first and second

dielectric layers

121, 122 form the recess 129, and the bridge circuit 125 is exposed within the recess 129. The remaining metal material 699 in the opening 635 of the second dielectric layer 122 and the third seed layer 613 form a via. The line layer 120 includes a first metal line 124, a first dielectric layer 121, a second metal line 126, and a second dielectric layer 122. A thermal process is performed to reflow (reflow) the solder 698 to form the micro bumps 690.

As shown in fig. 6M, the reinforcing structure 150 is placed within the recess 129. The upper surface and the lower surface of the reinforcing structure 150 are respectively provided with a first adhesive layer 161 and a second adhesive layer 162. The reinforcing structure 150 is attached to the bridge circuit 125 exposed at the bottom of the recess 129 by a second adhesive layer 162 of the lower surface. As shown in fig. 6N, first chip 132 and second chip 134 are attached to wiring layer 120 on opposite sides of stiffener structure 150, respectively. In this embodiment, attachment to wiring layer 120 is by way of pads 691 and microbumps 690 at the lower surfaces of first chip 132 and second chip 134.

As shown in fig. 6O, the underfill 145 is applied to the wiring layer 120 through a nozzle 688. The underfill encapsulates the lower portions of first chip 132 and second chip 134 and stiffener structure 150 between first chip 132 and second chip 134. As shown in fig. 6P, a protective layer 148 is formed surrounding the first chip 132, the second chip 134, and the underfill 145. The protective layer 148 may cover the top surfaces of the first and

second chips

132 and 134, or the protective layer 148 may expose the top surface of the higher one of the first and

second chips

132 and 134.

As shown in fig. 6Q, the structure in fig. 6P is inverted and attached to a second carrier 602. As shown in fig. 6R, the first carrier 601 is removed, so that the first seed layer 611 at a side surface of the circuit layer 120 opposite to the reinforcing structure 150 is exposed. An etching process is performed to remove the exposed first seed layer 611, thereby exposing the first metal lines 124, such as the bridge lines 125, under the first seed layer 611, as shown in fig. 6S.

As shown in fig. 6T, the wiring layer 120 is attached to the substrate 110 by the adhesive layer 155. As shown in fig. 6U, the second carrier 602 is removed. As shown in fig. 6V, the structure of fig. 6U is inverted, and solder balls 695 are formed on the surface of the substrate 110 opposite to the wiring layer 120. As shown in fig. 6W, a dicing process is performed along the dashed line L1 to form individual semiconductor packages as shown in fig. 2A.

The method for forming the semiconductor packaging structure manufactures the bridging circuit and other circuits in the circuit layer on the carrier. Recesses in the wiring layer and micro bumps on the wiring layer are fabricated. Then, the chip and the reinforcing structure are protected by adhering the chip and the reinforcing structure on the wiring layer and by molding the protective layer. Next, the wiring layer and the structure thereon are bonded to the substrate with the solder by using an adhesive material. Finally, solder balls are placed and a dicing process is performed to form the semiconductor package structure. The resulting package structure may have the benefits discussed above with reference to fig. 2A-2D.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package structure, comprising:

a circuit layer;

the first chip and the second chip are positioned above the circuit layer;

and the reinforcing structure is positioned below the first chip and the second chip and is abutted against the lower surface of the first chip, the lower surface of the second chip and the upper surface of the circuit layer.

2. The semiconductor package structure of claim 1,

the upper surface of the wiring layer includes a recess, and the reinforcing structure is disposed within the recess.

3. The semiconductor package structure of claim 2, further comprising:

an underfill encapsulating at least the reinforcing structure.

4. The semiconductor package structure of claim 1,

the circuit layer comprises a bridging circuit extending from the lower part of the first chip to the lower part of the second chip, wherein the reinforcing structure is positioned above the bridging circuit.

5. The semiconductor package structure of claim 1,

the upper surface of the reinforcing structure is provided with a first adhesive layer which is in contact with the lower surface of the first chip and the lower surface of the second chip.

6. The semiconductor package structure of claim 1,

a second adhesive layer is provided at a lower surface of the reinforcing structure in contact with the upper surface of the layer of wires.

7. The semiconductor package structure of claim 1,

the stiffener structure is attached to the upper surface of the wiring layer by electrical connections.

8. The semiconductor package structure of claim 1,

the reinforcing structure includes a passive element.

9. The semiconductor package structure of claim 1,

the reinforcing structure includes a third chip.

10. The semiconductor package structure of claim 1,

the reinforcing structure comprises a first reinforcing structure and a second reinforcing structure which are arranged at intervals, wherein the first reinforcing structure is propped against the lower surface of the first chip and the upper surface of the circuit layer, and the second reinforcing structure is propped against the lower surface of the second chip and the upper surface of the circuit layer.