CN114023363A

CN114023363A - EEPROM circuit

Info

Publication number: CN114023363A
Application number: CN202111248005.2A
Authority: CN
Inventors: 刘芳芳
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2021-10-26
Filing date: 2021-10-26
Publication date: 2022-02-08

Abstract

The invention discloses an EEPROM circuit, wherein bit lines connected with all storage units in selected bytes are floated when a storage array is erased; when one byte is selected in one row for operation, bit lines connected with corresponding memory cells in unselected bytes in the same row are all floated, and the memory cells are connected with a memory word line, a selection word line and a source line are all connected with 0V; each column of bit lines are connected with a corresponding transmission circuit, each transmission circuit comprises 4 transmission tubes, a first NMOS and a first PMOS form a first differential transmission path, and a second NMOS and a second PMOS form a second differential transmission path; the grid electrodes of the first NMOS tube and the second NMOS tube are both connected with a first control signal, and the grid electrodes of the first PMOS tube and the second PMOS tube are both connected with a second control signal; the first differential transmission path is connected between the third voltage signal and the first bit line signal, and the second differential transmission path is connected between the fourth voltage signal and the second bit line signal. The invention can reduce the circuit area and improve the unit density of the device.

Description

EEPROM circuit

Technical Field

The present invention relates to semiconductor integrated circuits, and more particularly, to an EEPROM circuit.

Background

For small-capacity SONOS EEPROM products, higher requirements are placed on the area of the product, so it is necessary to further reduce the area occupied by the device cells, thereby increasing the device cell density. As shown in fig. 1, is a circuit diagram of a memory array 101 of a conventional EEPROM circuit; the memory array 101 of the conventional EEPROM circuit is formed by arranging a plurality of memory cells 102 in rows and columns, fig. 1 shows only 8 memory cells 102 in 2 rows and 4 columns, the memory cells 102 in the first row are further denoted by a1, a2, A3 and a4, respectively, and the memory cells 102 in the second row are further denoted by B1, B2, B3 and B4, respectively.

The memory cell 102 is formed by connecting a SONOS memory tube 103 and a selection tube 104, and the source of the SONOS memory tube 103 is connected to the drain of the selection tube 104.

The SONOS memory cell 103 and the select transistor 104 of each memory cell 102 are both N-type devices and are formed on a corresponding P-type well, which is connected to a P-well substrate electrode (VBPW) of each memory cell 102.

Each first grid structure of the SONOS storage tube 103 comprises an ONO layer and a polysilicon grid which are sequentially superposed on the P-type well, the ONO layer comprises a first oxide layer, a second nitride layer and a third oxide layer which are sequentially superposed, the first oxide layer is a tunneling oxide layer, the second nitride layer is a storage layer, and the third oxide layer is a control oxide layer.

The second gate structure of each of the select transistors 104 includes a gate dielectric layer and a polysilicon gate sequentially stacked on the P-well.

In the memory array 101, the gates of the SONOS memory tubes 103 in the same row are connected to the memory word line WLS in the corresponding row, and the gates of the selection tubes 104 in the same row are connected to the selection word line WL in the corresponding row. The storage word line WLS and the select word line WL are also followed by a row number for the different rows, such as WLS1 and WLS2 and WL1 and WL2 in FIG. 1.

The drain of each SONOS memory tube 103 in the same column is connected to the bit line BL in the corresponding column, and the source of each selection tube 104 in the same column is connected to the source line SL in the corresponding column. The bit line BL is also followed by column numbers for different columns, such as BL1, BL2, BL3, and BL4 in fig. 1. The source line SL is also numbered correspondingly, and two rows of the memory cells 102 share one source line SL, so that fig. 1 only has two source lines SL, which are respectively marked by SL1 and SL 2.

Operations (operations) on the memory array 101 include Erase (Erase), Program (Program), and Read (Read). The operating voltages applied to each of the memory cells 102 corresponding to WL, WLs, BL, VBPW, and SL during the conventional operation are shown in table one.

Watch 1

In table one, the selected byte 105 is located in the first row, the unit of operation Target (Target) is a1, and a1 is individually denoted by Target (a 1). In general, the memory array 101 also adopts a differential structure, in this case, two adjacent memory cells 102 in the same row form a differential pair, two memory cells 102 of the differential pair process one source line SL, two bit lines BL form a pair of differential structures, for example, the memory cells a1 and a2 in fig. 1 form a pair of differential memory cell structures, and the bit lines BL1 and BL2 form a pair of differential structures; similarly, the memory cells A3 and a4, B1 and B2, and B3 and B4 respectively constitute corresponding differential memory cell structures. It can be seen that the differential memory cell structure corresponds to half the number of columns in units of a single memory cell 102.

As can be seen from table one, when erasing or Erase, word lines WL of memory cells a1 to a4 are all set to the power supply voltage (Vpwr), WLs is all set to 0V, BL is set to the first high level (VPOS), in table one, BL is followed by column number X of memory cell 102, since only 4 columns are shown in fig. 1, BLX (1-4) in table one indicates that the bit line is one of columns 1 to 4, the column number of the corresponding bit line BL is also specifically marked in the bit line corresponding to the Erase operation, and the bit lines BL corresponding to each memory cell 102 in the subsequent Program and read are the same as the column number of the bit line BL in Erase. For Erase, VBPW is set to VPOS and SL is set to float. Also shown in Table one are Erase operating voltage settings for memory cells B1 through B4, and it can be seen that WL are all set to Vpwr, WLS are all set to VPOS, BL are all set to VPOS, VBPW are all set to VPOS, and SL are all set to float.

In programming, i.e., Program, the WL's of memory cells A1-A4 are all set to 0V, WLS is all set to VPOS, VBPW is all set to 0V, and SL is all set to float; BL is set according to write 1 or write 0, BL corresponding to A1 and A3 is 0V, BL corresponding to A2 and A4 is a second positive voltage (Vbl); the second positive voltage is half of the first high level. The Program operating voltage settings for memory cells B1-B4 are also shown in Table one, and it can be seen that WL are all set to 0V, WLS are all set to a third positive Voltage (VPOSU), VBPW is all set to 0V, and SL is all set to float; BL of B1-B4 is set according to the signal of BL corresponding to A-A4 of the same column. VPOSU is smaller than VPOS, so that no programming effect occurs in B1-B4.

At Read, it can be seen from Table one that the WL's of memory cells A1-A4 are all set to Vpwr, WLS is all set to 0V, VBPW is all set to 0V, and SL is all set to 0V; the BL of the target memory cell A1 and the adjacent A2 are both set to the limiting voltage (Vlim), Vlim ≧ 0.65V, and BL of A3 and A4 are both set to 0V. The Read operating voltage settings of the memory cells B1-B4 are also shown in Table one, and it can be seen that WL, WLS, VBPW and SL are all set to 0V, and BL of B1-B4 is set according to the signal of BL corresponding to A-A4 in the same column.

As shown in fig. 2, a circuit diagram of a transmission circuit 201 of a conventional EEPROM circuit is shown. The two bit lines BL in a differential structure in each column corresponding to the differential memory cell structure are connected to the transmission circuit 201, the transmission circuit 201 adopts a differential structure, each column BL corresponds to two differential paths, the transmission circuit 201 includes 10 transmission transistors, and the 10 transmission transistors are respectively NMOS transistors N1, N2, N3, N4, N5 and N6 and PMOS transistors P1, P2, P3 and P4.

The NMOS transistors N1, N2, and N3 and the PMOS transistors P1 and P2 constitute a first differential transmission path 201a, and the NMOS transistors N4, N5, and N6 and the PMOS transistors P3 and P4 constitute a second differential transmission path 201 b.

The gates of NMOS transistors N1 and N4 are both connected to control signal a,

the gates of the NMOS transistors N2 and N5 are both connected to the control signal B.

The gates of the PMOS transistors P1 and P2 are both connected to the control signal C.

The gates of the NMOS transistors N3 and P2 are both connected to the control signal Di.

The gates of NMOS transistors N6 and P4 are both connected to control signal Dib.

The sources of the NMOS transistors N3 and N6 are grounded, and the drains of the PMOS transistors P1 and P3 are connected with the voltage Vbl.

The source of the NMOS transistor N1, the drain of the NMOS transistor N2, and the source of the PMOS transistor P2 output a first bit line signal BLL.

The source of the NMOS transistor N4, the drain of the NMOS transistor N5, and the source of the PMOS transistor P4 output a second bit line signal BLR.

Taking the differential memory cell structure composed of memory cells A1 and A2 as an example, bit line BL1 in FIG. 1 would be connected to BLL and BL2 would be connected to BLR; similarly, the bottom of the bit lines BL3 and BL4 are also connected to one of the pass circuits 201, and the bit line BL3 is connected to BLL and BL4 is connected to BLR.

The settings and outputs of the signals of the transmission circuit 201 are summarized in table two below.

Watch two

Disclosure of Invention

The invention aims to provide an EEPROM circuit, which can reduce the circuit area and improve the unit density of devices.

In order to solve the above technical problem, the memory array of the EEPROM circuit provided by the present invention is formed by arranging a plurality of memory cells in rows and columns, each memory cell is formed by connecting a SONOS memory transistor and a selection transistor, and a source of the SONOS memory transistor is connected to a drain of the selection transistor.

In the memory array, the gates of the SONOS memory tubes in the same row are connected to the memory word lines in the corresponding row, and the gates of the selection tubes in the same row are connected to the selection word lines in the corresponding row.

The drain electrode of each SONOS storage tube in the same column is connected to the bit line of the corresponding column, and the source electrode of each selection tube in the same column is connected to the source line of the corresponding column.

Operations on the memory array include erase, program, and read.

Eight memory cells in a row form a byte, erasing is carried out on each memory cell in the selected byte simultaneously, and bit lines connected with each memory cell in the selected byte are all floated during erasing.

When a byte is selected in one row for operation, the bit lines connected with the corresponding memory cells in the unselected byte in the same row are all floated, and the memory cell connecting memory word lines, the selection word line and the source line are all connected with 0V.

Each column of the bit lines is connected with a corresponding transmission circuit, the transmission circuit comprises 4 transmission tubes, the four transmission tubes are respectively a first NMOS tube, a first PMOS tube, a second NMOS tube and a second PMOS tube, the first NMOS tube and the first PMOS tube form a first differential transmission path, and the second NMOS tube and the second PMOS tube form a second differential transmission path; the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are both connected with a first control signal, and the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are both connected with a second control signal.

The drain electrode of the first NMOS tube and the source electrode of the first PMOS tube are both connected with a third voltage signal, and the source electrode of the first NMOS tube and the drain electrode of the first PMOS tube output a first bit line signal.

And the drain electrode of the second NMOS tube and the source electrode of the second PMOS tube are both connected with a fourth voltage signal, and the source electrode of the second NMOS tube and the drain electrode of the second PMOS tube output a second bit line signal.

The first control signal, the second control signal, the third voltage signal, and the fourth voltage signal are set according to an operation on each of the memory cells in each of the bytes to satisfy an operating voltage requirement on each of the bit lines during an operation on the memory array.

In a further improvement, when the first control signal is at a first low level and the second control signal is at a first high level, both the first bit line signal and the second bit line signal are in a floating state.

In a further improvement, when the first control signal is at a first high level and the second control signal is at a first low level, the third voltage signal is transmitted to the first bit line signal, and the fourth voltage signal is transmitted to the second bit line signal.

In a further improvement, the third voltage signal and the fourth voltage signal are a pair of mutually opposite signals.

In a further improvement, in the erasing and reading operations, the first bit line signal and the second bit line signal of the transmission circuit corresponding to each bit line are in a floating state.

In a further improvement, the programming operation includes writing 1 and writing 0, and in the programming operation, the first bit line signal and the second bit line signal of the transfer circuit corresponding to the bit line of each memory cell of each unselected byte are in a floating state.

The first bit line signal of the transmission circuit corresponding to the bit line of the memory cell requiring 1 writing in the selected byte is a first low level and the second bit line signal is a second positive voltage.

The first bit line signal of the transmission circuit corresponding to the bit line of the memory cell requiring a write 0 in the selected byte is a second positive voltage and the second bit line signal is a first low level.

In a further refinement, the second positive voltage is half of the first high level.

In a further improvement, the first low level is 0V.

In a further improvement, the SONOS memory cell and the selection transistor of each memory cell are both N-type devices and are formed on a corresponding P-well, the P-well of each memory cell being connected to a P-well substrate electrode.

In a further improvement, during erasing, the storage word lines of each memory cell of the selected byte are all connected with 0V, the selection word lines are all connected with a power voltage, the P-well substrate electrodes are all connected with a first high level, and the source lines are all floating.

In a further improvement, during programming, the storage word lines of each memory cell of the selected byte are all connected with a first high level, the selection word lines are all connected with 0V, the P-well substrate electrodes are all connected with the first high level, and the source lines are all floated.

In a further improvement, during programming, the bit line of the memory cell needing to write 1 in the selected byte is connected with 0V; the bit line of the memory cell needing to write 0 in the selected byte is connected with a second positive voltage; the second positive voltage is half of the first high level.

In a further improvement, during reading, the storage word lines of each memory cell of the selected byte are all connected with 0V, the selection word lines are all connected with a power voltage, the P-well substrate electrodes are all connected with 0V, and the source lines are all connected with 0V.

In a further improvement, when reading, the bit line of the memory cell to be read in the selected byte is connected to a limit voltage, and the storage information of the memory cell is read by a sense amplifier connected with the bit line.

The first gate structure of each SONOS storage tube comprises an ONO layer and a polysilicon gate which are sequentially superposed on the P-type well, the ONO layer comprises a first oxide layer, a second nitride layer and a third oxide layer which are sequentially superposed, the first oxide layer is a tunneling oxide layer, the second nitride layer is a storage layer, and the third oxide layer is a control oxide layer.

The second grid structure of each selection tube comprises a grid dielectric layer and a polysilicon grid which are sequentially superposed on the P-type trap.

The memory array is further improved in that the memory array further adopts a differential structure, the differential memory cell structure is composed of two adjacent memory cells in the same row, two bit lines connected with the two memory cells of the differential memory cell structure form a pair of differential structures, and the two bit lines in the differential structure in the column where each differential memory structure is located are connected with one transmission circuit.

The operation mode of the memory array of the EEPROM circuit of the invention is specially set, mainly to float the bit lines connected with each memory unit in the byte selected during erasing, and when one byte in one row is operated, the bit lines connected with the corresponding memory cells in the unselected byte in the same row are all floated, and the memory word line, the selection word line and the source line are all connected with 0V, the invention also specially sets the transmission circuit of each bit line according to the operation setting, the transmission circuit can realize the voltage setting required by the bit line during operation by adopting four transmission tubes, compared with the existing transmission circuit which needs to adopt ten transmission tubes, the invention greatly reduces the number of the transmission tubes, thereby saving the area of the transmission circuit, since one transmission circuit needs to be provided for each column, the circuit area can be reduced, and the device cell density can be increased.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a circuit diagram of a memory array of a prior art EEPROM circuit;

FIG. 2 is a circuit diagram of a transmission circuit of a conventional EEPROM circuit;

FIG. 3 is a circuit diagram of a transmission circuit of an EEPROM circuit according to an embodiment of the present invention.

Detailed Description

As shown in fig. 1, is a circuit diagram of a memory array 101 of a conventional EEPROM circuit; the memory array 101 of the EEPROM circuit according to the embodiment of the present invention is the same as the conventional structure, so the circuit diagram of the memory array 101 of the EEPROM circuit according to the embodiment of the present invention is also shown in fig. 1; the memory array 101 of the EEPROM circuit according to the embodiment of the present invention is formed by arranging a plurality of memory cells 102 in rows and columns, fig. 1 shows only 8 memory cells 102 with 2 rows and 4 columns, each memory cell 102 in the first row is further respectively labeled with a1, a2, A3 and a4, and each memory cell 102 in the second row is further respectively labeled with B1, B2, B3 and B4.

The SONOS memory cell 103 and the select transistor 104 of each memory cell 102 are both N-type devices and are formed on a corresponding P-type well, which is connected to a P-well substrate electrode (.

In the embodiment of the present invention, the memory array 101 further adopts a differential structure, in this case, two adjacent memory cells 102 in the same row form a differential pair, one source line SL is processed for the two memory cells 102 of the differential pair, two bit lines BL form a pair of differential structures, for example, the memory cells a1 and a2 in fig. 1 form a pair of differential memory cell structures, and the bit lines BL1 and BL2 form a pair of differential structures; similarly, the memory cells A3 and a4, B1 and B2, and B3 and B4 respectively constitute corresponding differential memory cell structures. It can be seen that the differential memory cell structure corresponds to half the number of columns in units of a single memory cell 102.

Operations on the memory array 101 include erase, program, and read. In operation of the embodiment of the present invention, the operating voltages applied to each of the WL, WLs, BL, VBPW, and SL of the memory cell 102 are shown in table three.

Watch III

In Table three, BL is followed by column number X of memory cell 102, and since only 4 columns are shown in FIG. 1, BLX (1-4) in Table one represents the bit line as one of columns 1-4.

It can be seen that eight memory cells 102 in a row form a byte 105, and the erasing is performed simultaneously for each memory cell 102 in the selected byte 105, and the bit line BL connected to each memory cell 102 in the selected byte 105 is floated during the erasing.

When one byte 105 in one row is selected to operate, the bit lines BL connected with the corresponding memory cells 102 in the unselected bytes 105 in the same row are all floated, and the memory cells 102 connected with the memory word line WLS, the selection word line WL and the source line SL are all connected with 0V.

During erasing, the storage word lines WLS of the memory cells 102 of the selected byte 105 are all connected to 0V, the selection word lines WL are all connected to a power voltage, the P-well substrate electrodes are all connected to a first high level, and the source lines SL are all floating. In table three, the selected byte 105 is located in the first row, the unit of operation Target (Target) is a1, and a1 is individually denoted by Target (a 1). It can be seen that at the time of erasing, i.e., Erase, the word lines WL of the memory cells a1 through a4 are all set to Vpwr, WLs is all set to 0V, BL is all set to float, VBPW is all set to VPOS, and SL is all set to float. Also shown in Table three are the Erase operating voltage settings for memory cells B1 through B4, and it can be seen that WL are all set to Vpwr, WLS are all set to VPOS, BL is all set to float, VBPW is all set to VPOS, and SL is all set to float.

During programming, the storage word lines WLS of the memory cells 102 of the selected byte 105 are all connected to a first high level, the selection word lines WL are all connected to 0V, the P-well substrate electrodes are all connected to the first high level, and the source lines SL are all floating. Meanwhile, during programming, the bit line BL of the memory cell 102 needing to write 1 in the selected byte 105 is connected to 0V; the bit line BL of the memory cell 102 needing to write 0 in the selected byte 105 is connected to a second positive voltage; the second positive voltage is half of the first high level. As can be seen from Table three, the WL's of memory cells A1-A4 are all set to 0V, WLS is all set to VPOS, VBPW is all set to 0V, and SL is all set to float; BL is set according to write 1 or write 0, BL corresponding to A1 and A3 is 0V, BL corresponding to A2 and A4 is Vbl. The Program operating voltage settings for memory cells B1-B4 are also shown in Table three, and it can be seen that WL are all set to 0V, WLS are all set to a third positive Voltage (VPOSU), VBPW is all set to 0V, and SL is all set to float; BL of B1-B4 is set according to the signal of BL corresponding to A-A4 of the same column.

During reading, the storage word lines WLS of the memory cells 102 of the selected byte 105 are all connected to 0V, the selection word lines WL are all connected to a power voltage, the P-well substrate electrodes are all connected to 0V, and the source lines SL are all connected to 0V. When reading, the bit line BL of the memory cell 102 to be read in the selected byte 105 is connected to Vlim and the storage information of the memory cell 102 is read through the sense amplifier connected to the bit line BL. As can be seen from Table three, the WL's of memory cells A1-A4 are all set to Vpwr, WLS are all set to 0V, VBPW is all set to 0V, and SL is all set to 0V; the BL of the target memory cell A1 and the adjacent A2 are set to Vlim ≧ 0.65V, and the BL of A3 and A4 are set to 0V. The Read operating voltage settings for memory cells B1-B4 are also shown in Table three, and it can be seen that WL, WLS, VBPW and SL are all set to 0V, and the BL of B1-B4 is set according to the signal of BL corresponding to A-A4 of the same column.

Fig. 3 is a circuit diagram of a transmission circuit 301 of an EEPROM circuit according to an embodiment of the present invention. The two bit lines BL in a differential structure in each column corresponding to the differential memory cell structure are connected to a transmission circuit 301, the transmission circuit 301 is in a differential structure, each column BL corresponds to two differential paths, the transmission circuit 301 includes 4 transmission tubes, the four transmission tubes are respectively a first NMOS tube N101, a first PMOS tube P101, a second NMOS tube N102 and a second PMOS tube P102, the first NMOS tube N101 and the first PMOS form a first differential transmission path 301a, and the second NMOS tube N102 and the second PMOS form a second differential transmission path 302 a; the grid electrode of the first NMOS transistor N101 and the grid electrode of the second NMOS transistor N102 are both connected with a first control signal A, and the grid electrode of the first PMOS transistor P101 and the grid electrode of the second PMOS transistor P102 are both connected with a second control signal B.

The drain of the first NMOS transistor N101 and the source of the first PMOS transistor P101 are both connected to a third voltage signal Di, and the source of the first NMOS transistor N101 and the drain of the first PMOS transistor P101 output a first bit line signal BLL. The third voltage signal Di and the fourth voltage signal Dib are a pair of signals that are opposite in phase to each other.

The drain of the second NMOS transistor N102 and the source of the second PMOS transistor P102 are both connected to a fourth voltage signal Dib, and the source of the second NMOS transistor N102 and the drain of the second PMOS transistor P102 output a second bit line signal BLR.

The first control signal a, the second control signal B, the third voltage signal Di, and the fourth voltage signal Dib are set according to the operation of each memory cell 102 in each byte 105 to satisfy the operating voltage requirement of each bit line BL at the time of the operation of the memory array 101.

When the first control signal a is at a first low level and the second control signal B is at a first high level, the first bit line signal BLL and the second bit line signal BLR are both in a floating state.

When the first control signal a is at a first high level and the second control signal B is at a first low level, the third voltage signal Di is transmitted to the first bit line signal BLL, and the fourth voltage signal Dib is transmitted to the second bit line signal BLR.

In the erasing and reading operations, the first bit line signal BLL and the second bit line signal BLR of the transfer circuit 301 corresponding to each of the bit lines BL are in a floating state.

The programming operation includes writing 1 and writing 0, and in the programming operation, the first bit line signal BLL and the second bit line signal BLR of the transfer circuit 301 corresponding to the bit line BL of each memory cell 102 of each unselected byte 105 are in a floating state.

The first bit line signal BLL of the transfer circuit 301 corresponding to the bit line BL of the memory cell 102 requiring 1 writing in the selected byte 105 is at a first low level and the second bit line signal BLR is at a second positive voltage.

The first bit line signal BLL of the transfer circuit 301 corresponding to the bit line BL of the memory cell 102 requiring a write 0 in the selected byte 105 is a second positive voltage and the second bit line signal BLR is a first low level.

The second positive voltage is half of the first high level, i.e., Vbl ═ VPOS/2.

The first low level is 0V.

The settings and outputs of the signals of the transmission circuit 301 described above are summarized in table four below.

Watch four

The operation mode of the memory array 101 of the EEPROM circuit of the embodiment of the present invention is specially set, mainly, bit lines BL connected to each memory cell 102 in a byte 105 selected at the time of erasing are all floated, and bit lines BL connected to each memory cell 102 corresponding to an unselected byte 105 in the same row are all floated, and a memory word line WLS, a selection word line WL, and a source line SL are all connected to 0V when one byte 105 selected in one row is operated, and the present invention also specially sets the transfer circuit 301 of each bit line BL according to the above operation setting, so that the transfer circuit 301 adopts four transfer transistors to realize the voltage setting required by the bit lines BL at the time of operation, compared with the existing transfer circuit 301 which needs to adopt ten transfer transistors, the embodiment of the present invention greatly reduces the number of transfer transistors, thereby saving the area of the transfer circuit 301, because each column needs to arrange one transfer circuit 301, the circuit area can be reduced and the device cell density can be increased.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims

1. An EEPROM circuit, characterized by: the storage array is formed by arranging a plurality of storage units in rows and columns, each storage unit is formed by connecting an SONOS storage tube and a selection tube, and the source electrode of each SONOS storage tube is connected with the drain electrode of the selection tube;

in the memory array, the gates of the SONOS memory tubes in the same row are connected to the memory word lines in the corresponding row, and the gates of the selection tubes in the same row are connected to the selection word lines in the corresponding row;

the drain electrode of each SONOS storage tube in the same column is connected to the bit line of the corresponding column, and the source electrode of each selection tube in the same column is connected to the source line of the corresponding column;

the operations on the memory array include erasing, programming and reading;

forming a byte by eight memory cells in a row, wherein erasing is performed on each memory cell in the selected byte simultaneously, and bit lines connected with each memory cell in the selected byte are all floated during erasing;

when a byte is selected in one row for operation, bit lines connected with corresponding memory cells in unselected bytes in the same row are all floated, and the memory cells are connected with a memory word line, a selection word line and the source line are all connected with 0V;

each column of the bit lines is connected with a corresponding transmission circuit, the transmission circuit comprises 4 transmission tubes, the four transmission tubes are respectively a first NMOS tube, a first PMOS tube, a second NMOS tube and a second PMOS tube, the first NMOS tube and the first PMOS tube form a first differential transmission path, and the second NMOS tube and the second PMOS tube form a second differential transmission path; the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are both connected with a first control signal, and the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are both connected with a second control signal;

the drain electrode of the first NMOS tube and the source electrode of the first PMOS tube are both connected with a third voltage signal, and the source electrode of the first NMOS tube and the drain electrode of the first PMOS tube output a first bit line signal;

the drain electrode of the second NMOS tube and the source electrode of the second PMOS tube are both connected with a fourth voltage signal, and the source electrode of the second NMOS tube and the drain electrode of the second PMOS tube output a second bit line signal;

2. The EEPROM circuit of claim 1, wherein: when the first control signal is at a first low level and the second control signal is at a first high level, the first bit line signal and the second bit line signal are both in a floating state.

3. The EEPROM circuit of claim 2, wherein: when the first control signal is at a first high level and the second control signal is at a first low level, the third voltage signal is transmitted to the first bit line signal, and the fourth voltage signal is transmitted to the second bit line signal.

4. The EEPROM circuit of claim 3, wherein: the third voltage signal and the fourth voltage signal are a pair of mutually opposite signals.

5. The EEPROM circuit of claim 4, wherein: in the erasing and reading operations, the first bit line signal and the second bit line signal of the transmission circuit corresponding to each bit line are in a floating state.

6. The EEPROM circuit of claim 4, wherein: the programming operation comprises 1 writing and 0 writing, and in the programming operation, the first bit line signal and the second bit line signal of the transmission circuit corresponding to the bit line of each storage unit of each unselected byte are in a floating state;

the first bit line signal of the transmission circuit corresponding to the bit line of the memory cell needing 1 writing in the selected byte is a first low level and the second bit line signal is a second positive voltage;

7. The EEPROM circuit of claim 6, wherein: the second positive voltage is half of the first high level.

8. The EEPROM circuit of claim 2, wherein: the first low level is 0V.

9. The EEPROM circuit of claim 1, wherein: the SONOS storage tube and the selection tube of each memory cell are both N-type devices and are formed on corresponding P-type wells, and the P-type wells of each memory cell are connected to a P-well substrate electrode.

10. The EEPROM circuit of claim 9, wherein: when erasing, the storage word lines of each storage unit of the selected byte are all connected with 0V, the selection word lines are all connected with power voltage, the P-well substrate electrodes are all connected with a first high level, and the source lines are all floated.

11. The EEPROM circuit of claim 9, wherein: during programming, the storage word lines of the storage units of the selected byte are all connected with a first high level, the selection word lines are all connected with 0V, the P-well substrate electrodes are all connected with the first high level, and the source lines are all floated.

12. The EEPROM circuit of claim 11, wherein: during programming, connecting 0V to the bit line of the memory cell needing to write 1 in the selected byte; the bit line of the memory cell needing to write 0 in the selected byte is connected with a second positive voltage; the second positive voltage is half of the first high level.

13. The EEPROM circuit of claim 9, wherein: during reading, the storage word lines of the storage units of the selected byte are all connected with 0V, the selection word lines are all connected with power voltage, the P-well substrate electrodes are all connected with 0V, and the source lines are all connected with 0V.

14. The EEPROM circuit of claim 13, wherein: when reading, the bit line of the read memory cell in the selected byte is connected to a limit voltage, and the storage information of the memory cell is read by a sensitive amplifier connected with the bit line.

15. The EEPROM circuit of claim 9, wherein: the first gate structure of each SONOS storage tube comprises an ONO layer and a polysilicon gate which are sequentially overlapped on the P-type well, the ONO layer comprises a first oxide layer, a second nitride layer and a third oxide layer which are sequentially overlapped, the first oxide layer is a tunneling oxide layer, the second nitride layer is a storage layer, and the third oxide layer is a control oxide layer;

16. The EEPROM circuit of claim 1, wherein: the memory array also adopts a differential structure, in the same row, the differential memory cell structure is composed of two adjacent memory cells, two bit lines connected with the two memory cells of the differential memory cell structure form a pair of differential structures, and the two bit lines in the differential structure in the column of each differential memory structure are connected with one transmission circuit.