CN114021831B - Edge response-based PDN network worst voltage noise prediction method - Google Patents
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Abstract
The invention provides a PDN network worst voltage noise prediction method based on edge response, which is used for solving the problems that the complexity is high when a high-speed circuit system predicts the worst voltage noise of a power distribution network and a large error can occur when predicting the worst voltage noise of the whole power distribution network. The implementation steps are as follows: (1) performing frequency domain simulation on a power distribution network; (2) performing time domain simulation on a power distribution network; (3) obtaining a rising edge vector and a falling edge vector; (4) Calculating worst voltage noise V of power distribution network worst . The invention can efficiently and accurately predict the worst voltage noise of the power distribution network and can be used for power integrity analysis.
Description
Technical Field
The invention belongs to the technical field of electronics, and further relates to a worst voltage noise prediction method of a power distribution network PDN (Power Distribution Network) based on edge response in the technical field of high-speed circuit system design. The invention can predict the worst voltage noise of the power distribution network in the design of the high-speed circuit system and provides a reference for the analysis of the power integrity.
Background
The power distribution network is comprised of the power module, capacitance on the printed circuit board PCB (Printed Circuit Board), and power and ground planes, capacitance within the chip package, and power and ground networks, etc. The main function of the power distribution network is to provide enough voltage for all devices or chips in the system and meet the requirement of the system on the stability of the power supply. As chip clock frequencies continue to increase, the design of power distribution networks becomes increasingly difficult. On the one hand, although electronic products are developed towards small volumes, the requirements for the functions of the electronic products are increasing, and the power consumption of the electronic products is also increasing due to the strong chip performance. On the other hand, the switching speed of transistors inside a load chip is faster and faster, so that the requirement for high-frequency transient current of the load is larger and larger. A rational design of the power distribution network is necessary. Currently, power distribution networks are designed primarily based on target impedance. The target impedance is the ratio of the maximum voltage noise and the maximum transient current produced by the system. For a good power distribution network, the voltage variation can meet the design requirement no matter how the load transient current changes, i.e. the fluctuation range of the voltage does not exceed the specified value in any case, and the system meets the design requirement. The core problem of this procedure is how to determine the worst voltage noise for a certain determined power distribution network.
Sandle, steven Picotest, in its published "Target Impedance Limitations and Rogue Wave Assessments on PDN Performance" (conference design con 2015) paper, proposed a method for predicting the worst power supply noise of a PDN network. The method comprises the following implementation steps: performing frequency domain simulation on the power distribution network to obtain an impedance curve of the power distribution network; constructing a load circuit consisting of a series of current sources that produce square wave current signals that contain each antiresonant frequency while allowing the time delay of each current source to be adjusted; and optimizing the delay of the current source of the circuit by using an optimizer in software ADS to find the worst predicted power supply noise. The worst voltage noise can be predicted using this method. However, this method still has the disadvantages: since this design requires the construction of a series of current sources as load circuits, the square wave current signals generated by these current sources are required to contain each antiresonant frequency and the time delay of each current source is strictly required, which results in high complexity in predicting the worst voltage noise of the power distribution network.
The university of western electronic technology discloses a worst power supply noise prediction method in the patent literature of the university of western electronic technology, which applies for an accurate prediction method of the worst power supply noise of a high-speed circuit system (application number: 201710049054.0 grant publication number: CN 106886636B). The method comprises the following implementation steps: performing frequency domain simulation on the power distribution network to obtain a frequency domain self-impedance curve of an output port of the power distribution network; determining an anti-resonance frequency value corresponding to the maximum peak value in a frequency domain self-impedance curve of the power distribution network, and modulating a periodic rectangular wave with a duty ratio of 50% by utilizing the anti-resonance frequency value to obtain an input code pattern causing worst power supply noise; the rising current and the falling current of the output port of the power distribution network are obtained through simulation; predicting the worst current of the output port of the power distribution network; calculating the time domain impedance of the power distribution network; the worst power supply noise of the high-speed circuitry is calculated. The method improves the prediction precision to a certain extent on the premise of ensuring the efficiency, and can be applied to analysis of signal integrity in a high-speed circuit system. However, the patent still has the disadvantages that: the method only models the switching current of a single transistor through rising current and falling current to obtain the worst predicted current of the transistor, and predicts the worst voltage noise of a power supply distribution network by using the worst predicted current. However, the load chip contains thousands of transistors, and a large error occurs in predicting the current of only one of the transistors in the load chip and using it to further predict the worst voltage noise of the whole power distribution network.
Disclosure of Invention
The invention aims to solve the problems that the complexity is high when the worst voltage noise of a power distribution network is predicted and a large error occurs when the worst voltage noise of the whole power distribution network is predicted.
The invention uses an ideal step current source as a load circuit of a power distribution network, carries out time domain simulation on the whole power distribution network of a high-speed circuit system, and obtains rising edge response waveforms and falling edge response waveforms of output ports of the power distribution network. The invention utilizes the obtained edge response of the whole power distribution network of the high-speed circuit system to respectively predict the maximum response voltage value of each bit input by the load current source of the power distribution network when the code patterns of the maximum response voltage value are 1 and 0 and the minimum response voltage value of each bit input by the load current source of the power distribution network when the code patterns of the maximum response voltage value are 1 and 0, and the edge response of the whole power distribution network is jointly determined by the switching currents of a plurality of transistors instead of the switching currents of a single transistor in the process, thereby solving the problem that the prediction result is greatly error caused by predicting the worst voltage noise of the whole PDN network according to the switching current of the single transistor.
The technical scheme adopted by the invention comprises the following steps:
step 1, performing frequency domain simulation on a power distribution network:
performing frequency domain simulation on a power distribution network of the high-speed circuit system to obtain anti-resonance frequency values corresponding to each maximum value point in an impedance curve of the power distribution network;
step 2, performing time domain simulation on a power distribution network:
using an ideal step current source as a load circuit of a power distribution network, and performing time domain simulation on the whole power distribution network of a high-speed circuit system to obtain a rising edge response waveform and a falling edge response waveform of an output port of the power distribution network;
step 3, a rising edge vector and a falling edge vector are obtained:
(3a) Sampling the rising edge response waveform and the falling edge response waveform at equal intervals respectively by using a sampling frequency F;
(3b) The stable value V of the rising and falling edge response waveforms is subtracted from each sampling point of the rising and falling edge response waveforms high And V low Obtaining a rising edge vector V rr And a falling edge vector V ff ；
Step 4, calculating the worst voltage noise V of the power distribution network worst ：
(4a) The maximum response voltage value of each bit input by the load current source of the power distribution network when the code pattern is 1 is calculated according to the following steps:
V 1 (S)＝max(V 1 (S-1),V 0 (S-1)+V rr (i))
wherein V is 1 (S) represents the maximum response voltage value when the S-th bit pattern input by the load current source of the power distribution network is "1", S represents the sequence number of the code pattern in the code pattern sequence input by the load current source of the power distribution network, s=1, 2, …, N represents the rising edge vector V rr Max (·) represents the maximum value taking operation, V 1 (S-1) represents the maximum response voltage value, V, of the S-1 bit pattern input by the load current source of the power distribution network when the S-1 bit pattern is' 1 0 (S-1) represents the maximum response voltage value when the S-1 bit pattern input by the load current source of the power distribution network is "0", when s=1, V 1 (S-1)＝0、V 0 (S-1)＝0，V rr (i) Representing rising edge vector V rr I=1, 2, …, N;
(4b) The maximum response voltage value of each bit input by the load current source of the power distribution network when the code pattern is 0 is calculated according to the following steps:
V 0 (S)＝max(V 0 (S-1),V 1 (S-1)+V ff (j))
wherein V is 0 (S) represents the maximum response voltage value, V, when the S bit code pattern input by the load current source of the power distribution network is 0 ff (j) Representing the falling edge vector V ff The value of j is correspondingly equal to i;
(4c) Calculating the maximum response voltage value V of the last bit code pattern input by the load current source of the power distribution network according to the following formula max ：
V max ＝max(V 1 (S)+V high ,V 0 (S)+V low )；
(4d) The minimum response voltage value of each bit of the power distribution network load current source input when the code pattern is '1' is calculated according to the following steps:
V 11 (S)＝min(V 11 (S-1),V 00 (S-1)+V rr (i))
wherein V is 11 (S) represents the minimum response voltage value when the S bit code pattern input by the load current source of the power distribution network is '1', and min (DEG) represents the operation of taking the minimum value, V 11 (S-1) represents the minimum response voltage value, V, when the S-1 bit pattern input by the load current source of the power distribution network is' 1 00 (S-1) represents the minimum response voltage value when the S-1 bit pattern input by the load current source of the power distribution network is "0", when s=1, V 11 (S-1)＝0、V 00 (S-1)＝0；
(4e) The minimum response voltage value of each bit of the power distribution network load current source input when the code pattern is 0 is calculated according to the following steps:
V 00 (S)＝min(V 00 (S-1),V 11 (S-1)+V ff (j))
wherein V is 00 (S) represents the minimum response voltage value when the S bit code pattern input by the load current source of the power distribution network is 0;
(4f) The minimum response voltage value V of the last bit code pattern input by the load current source of the power distribution network is calculated according to the following steps min ：
V min ＝min(V 11 (S)+V high ,V 00 (S)+V low )；
(4g) Calculating worst voltage noise V of power distribution network worst ＝V max -V min 。
Compared with the prior art, the invention has the following advantages:
firstly, the invention uses an ideal step current source as a load circuit to perform time domain simulation on the whole power distribution network of the high-speed circuit system, and only uses one current source as the load of the power distribution network, thereby overcoming the defect of complexity of modeling the load circuit of the power distribution network in the prior art, reducing the complexity when predicting the worst voltage noise of the power distribution network and improving the efficiency of predicting the worst voltage noise of the power distribution network.
Secondly, the invention predicts the worst voltage noise by using the edge response of the whole power distribution network of the high-speed circuit system, takes the edge response of the whole network as the worst voltage noise prediction basis, overcomes the defect that the prediction result of the voltage noise prediction of the whole power distribution network is greatly error according to the worst current of a single transistor in the prior art, and improves the precision of predicting the worst voltage noise of the power distribution network.
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FIG. 1 is a flow chart of an implementation of the present invention;
fig. 2 is a simulation diagram of the present invention.
Detailed description of the preferred embodiments
The invention will now be described in further detail with reference to the drawings and to specific embodiments.
The specific steps of an implementation of the present invention are described in further detail with reference to fig. 1.
And step 1, performing frequency domain simulation on a power distribution network.
And carrying out frequency domain simulation on a power distribution network of the high-speed circuit system to obtain an anti-resonance frequency value corresponding to each maximum point in an impedance curve of the power distribution network.
In the embodiment of the invention, an alternating current source is added to an output port of a power distribution network, the amplitude of current I (w) of the current source is constant to be 1 ampere, and frequency domain simulation is carried out on the power distribution network of a high-speed circuit system to obtain an amplitude curve of voltage V (w) of the output port of the power distribution network, wherein w is angular frequency, and the unit is radian per second.
From the amplitude curve of the current I (w) of the alternating current source of the power distribution network and the voltage V (w) of the output port of the power distribution network, the method is represented by the formulaCalculating to obtain an impedance curve of the power distribution network, wherein the frequency corresponding to each maximum point in the impedance curve is an antiresonant frequency F 1 ,F 2 ,…,F n Wherein F is n Representing the nth antiresonant frequency value in the power distribution network impedance curve.
And 2, performing time domain simulation on the power distribution network.
And using an ideal step current source as a load circuit of the power distribution network, and performing time domain simulation on the whole power distribution network of the high-speed circuit system to obtain a rising edge response waveform and a falling edge response waveform of an output port of the power distribution network.
In an embodiment of the invention, the current of the step current source is set according to the following formula:
wherein I (t) represents the current value of the step current source at the time t, and a and B represent the current values of the step current source at t > 0 and t=0, respectively, in amperes. When a=1 and b=0, the time domain simulation is performed on the whole power distribution network of the high-speed circuit system, and rising edge response is obtained at the output port of the power distribution network. When a=0 and b= -1, performing time domain simulation on the whole power distribution network of the high-speed circuit system, and obtaining a falling edge response at an output port of the power distribution network.
And step 3, obtaining a rising edge vector and a falling edge vector.
The rising and falling edge response waveforms are sampled at equal intervals using a sampling frequency F:
F≥20*max(F 1 ,F 2 ,…,F n )
wherein, represents multiplication operation, max (·) represents maximum value taking operation;
the stable value V of the rising and falling edge response waveforms is subtracted from each sampling point of the rising and falling edge response waveforms, respectively high And V low Obtaining a rising edge vector V rr And a falling edge vector V ff 。
Step 4, calculating the worst voltage noise V of the power distribution network worst 。
The maximum response voltage value of each bit input by the load current source of the power distribution network when the code pattern is 1 is calculated according to the following steps:
V 1 (S)＝max(V 1 (S-1),V 0 (S-1)+V rr (i))
wherein V is 1 (S) represents the maximum response voltage value when the S-th bit pattern input by the load current source of the power distribution network is "1", S represents the sequence number of the code pattern in the code pattern sequence input by the load current source of the power distribution network, s=1, 2, …, N represents the rising edge vector V rr Max (·) represents the maximum value taking operation, V 1 (S-1) represents the maximum response voltage value, V, of the S-1 bit pattern input by the load current source of the power distribution network when the S-1 bit pattern is' 1 0 (S-1) represents the maximum response voltage value when the S-1 bit pattern input by the load current source of the power distribution network is "0", when s=1, V 1 (S-1)＝0、V 0 (S-1)＝0，V rr (i) Representing rising edge vector V rr I=1, 2, …, N;
recorded in acquisition V 1 Under the condition of (S), each bit of load current source of power distribution network inputs code pattern sequence P 1 。
The maximum response voltage value of each bit input by the load current source of the power distribution network when the code pattern is 0 is calculated according to the following steps:
V 0 (S)＝max(V 0 (S-1),V 1 (S-1)+V ff (j))
wherein V is 0 (S) represents the maximum response voltage value, V, when the S bit code pattern input by the load current source of the power distribution network is 0 ff (j) Representing the falling edge vector V ff The j-th element value in the (b) is equal to the i corresponding value.
Recorded in acquisition V 0 Under the condition of (S), the input code pattern sequence P of the load current source of the power distribution network 0 。
Calculating the maximum response voltage value V of the last bit code pattern input by the load current source of the power distribution network according to the following formula max ：
V max ＝max(V 1 (S)+V high ,V 0 (S)+V low )
Wherein when V max ＝V 1 (S)+V high When the power distribution network loads the current source input code pattern sequence P max Is a code pattern sequence P 1 When V max ＝V 0 (S)+V low When the power distribution network loads the current source input code pattern sequence P max Is a code pattern sequence P 0 。
The minimum response voltage value of each bit of the power distribution network load current source input when the code pattern is '1' is calculated according to the following steps:
V 11 (S)＝min(V 11 (S-1),V 00 (S-1)+V rr (i))
wherein V is 11 (S) represents the minimum response voltage value when the S bit code pattern input by the load current source of the power distribution network is '1', and min (DEG) represents the operation of taking the minimum value, V 11 (S-1) represents the minimum response voltage value, V, when the S-1 bit pattern input by the load current source of the power distribution network is' 1 00 (S-1) represents the minimum response voltage value when the S-1 bit pattern input by the load current source of the power distribution network is "0", when s=1, V 11 (S-1)＝0、V 00 (S-1)＝0。
Recorded in acquisition V 11 Under the condition of (S), each bit of load current source of power distribution network inputs code pattern sequence P 11 。
The minimum response voltage value of each bit of the power distribution network load current source input when the code pattern is 0 is calculated according to the following steps:
V 00 (S)＝min(V 00 (S-1),V 11 (S-1)+V ff (j))
wherein V is 00 (S) represents the minimum response voltage value when the S bit code pattern input by the load current source of the power distribution network is 0.
Recorded in acquisition V 00 Under the condition of (S), each bit of load current source of power distribution network inputs code pattern sequence P 00 。
The minimum response voltage value V of the last bit code pattern input by the load current source of the power distribution network is calculated according to the following steps min ：
V min ＝min(V 11 (S)+V high ,V 00 (S)+V low )
Wherein when V min ＝V 11 (S)+V high When the power distribution network loads the current source input code pattern sequence P min Is a code pattern sequence P 11 When V min ＝V 00 (S)+V low When the power distribution network loads the current source input code pattern sequence P min Is a code pattern sequence P 00 。
Calculating worst voltage noise V of power distribution network worst ＝V max -V min 。
Pattern sequence P min All patterns in (a) are placed in pattern sequence P max After the last pattern, a new pattern sequence P is obtained worst When the load current source input code pattern sequence of the power distribution network is P worst When the voltage obtained at the output port of the power distribution network is peak-to-peak with V worst Equal.
The effects of the present invention are further described below in conjunction with simulation experiments:
1. conditions of simulation experiment:
the hardware platform of the simulation experiment of the invention is: the processor is Intel (R) Core (TM) i7-8700, the main frequency is 3.2GHz, and the memory is 16GB.
The software platform of the simulation experiment of the invention is: windows10 operating system, matlab2019a software, and ADS2020 software.
2. Simulation content of simulation experiment:
in the simulation experiment of the invention, a power distribution network shown in fig. 2 (a) is built in software ADS2020, VDC in fig. 2 (a) represents a direct current voltage source with the voltage of the power distribution network being 0V, V represents unit volt of the voltage, L1, L2, L3 and L4 represent inductances with inductance values of 50nH, 2nH, 3nH and 100pH respectively, nH and pH represent units of nano-henry and pico-henry of the inductance respectively, R1, R2, R3, R4 and R5 represent resistances with resistance values of 2mOhm, 1mOhm, 6mOhm and 2mOhm respectively, mOhm represents units milliohm of the resistances, C1, C2 and C3 represent capacitances with capacitance values of 100uF, 5uF and 0.1uF respectively, uF represents unit micro-method of the capacitances, GND represents grounding, and Itp represents a load of the power distribution network. And respectively adding a step current of 0-1 ampere and a step current of-1-0 ampere into a load current source of the power distribution network for 300 microseconds, and sampling the voltage at an output port of the power distribution network at a time interval of 1 nanosecond and a frequency of 1 gigahertz to obtain rising edge response and falling edge response at the output port of the power distribution network.
Using the rising edge response and the falling edge response obtained by the simulation in step 4 of the present invention, the worst voltage noise V of the power distribution network as shown in fig. 2 (a) is calculated worst At 401 mV, record produces V worst Input code pattern sequence P of network load current source of time power distribution network worst 。
The load current source in the power distribution network in the figure 2 (a) is replaced by a load voltage source, the positive electrode of the load voltage source is connected with a voltage-controlled current source, and the code pattern sequence P is realized worst As an input pattern of the load voltage source, a voltage of 600 microseconds is generated at the output port of the load voltage source, and the voltage at the output port of the power distribution network is sampled at a time interval of 1 nanosecond and a frequency of 1 gigahertz, so as to obtain voltage noise at the output port of the power distribution network, as shown in fig. 2 (b). The abscissa of FIG. 2 (b) is voltageThe number of sampling points, the ordinate is the voltage value of each sampling point of the voltage noise at the output port of the power distribution network, in fig. 2 (b), M1 (9599842,199) represents that the voltage value of the 9599842 th sampling point is 199 millivolts, which is the maximum voltage noise of the power distribution network, and M2 (4799842, -202) represents that the voltage value of the 4799842 th sampling point is 202 millivolts, which is the minimum voltage noise of the power distribution network. As can be seen from FIG. 2 (b), by pattern sequence P worst The worst voltage noise of the power distribution network obtained by simulation is 199- (-202) =401 millivolts.
The accuracy of the proposed method is compared by three methods of calculating the power distribution network voltage noise as shown in table 1.
The first method is to calculate the worst voltage noise V of the power distribution network as shown in FIG. 2 (a) through the simulation experiment of the invention worst 401 millivolts.
The second method is to pass through the code pattern sequence P worst The worst voltage noise of the power distribution network shown in fig. 2 (b) was 401 mv.
The third method is to use Rouge Wave to obtain the worst voltage noise of the power distribution network.
Sandle, steven Picotest, in its published "Target Impedance Limitations and Rogue Wave Assessments on PDN Performance" (conference design con 2015) paper, proposes using Rouge Wave to solve for the worst voltage noise of the power distribution network. Since the power distribution network used in this paper is the same as the power distribution network structure used in the present invention, the worst voltage noise of the power distribution network calculated in this paper is directly used for 370 millivolts.
Table 1 comparison of worst voltage noise of power distribution network obtained by three different methods
| Worst voltage noise | |
| Method one | 401 millivolts |
| Method II | 401 millivolts |
| Method III | 370 millivolts |
By combining the table 1, it can be seen that the worst voltage noise of the power distribution network obtained by the first method and the second method is consistent, which indicates that the result obtained by the invention is accurate, and by comparing the first method and the third method, it can be seen that the worst voltage noise obtained by the invention is 31 millivolts greater than that obtained by the third method, which indicates that the worst voltage noise of the power distribution network obtained by the calculation of the invention is more accurate.
Claims (2)
1. The edge response-based PDN network worst voltage noise prediction method is characterized in that a power distribution network is subjected to time domain simulation to obtain rising edge vectors and falling edge vectors, and worst voltage noise of the power distribution network is calculated; the method comprises the following specific steps:
step 1, performing frequency domain simulation on a power distribution network:
performing frequency domain simulation on a power distribution network of the high-speed circuit system to obtain anti-resonance frequency values corresponding to each maximum value point in an impedance curve of the power distribution network;
step 2, performing time domain simulation on a power distribution network:
using an ideal step current source as a load circuit of a power distribution network, and performing time domain simulation on the whole power distribution network of a high-speed circuit system to obtain a rising edge response waveform and a falling edge response waveform of an output port of the power distribution network;
step 3, a rising edge vector and a falling edge vector are obtained:
(3a) Sampling the rising edge response waveform and the falling edge response waveform at equal intervals respectively by using a sampling frequency F;
(3b) The stable value V of the rising and falling edge response waveforms is subtracted from each sampling point of the rising and falling edge response waveforms high And V low Obtaining a rising edge vector V rr And a falling edge vector V ff ；
Step 4, calculating the worst voltage noise V of the power distribution network worst ：
(4a) The maximum response voltage value of each bit input by the load current source of the power distribution network when the code pattern is 1 is calculated according to the following steps:
V 1 (S)＝max(V 1 (S-1),V 0 (S-1)+V rr (i))
wherein V is 1 (S) represents the maximum response voltage value when the S-th bit pattern input by the load current source of the power distribution network is "1", S represents the sequence number of the code pattern in the code pattern sequence input by the load current source of the power distribution network, s=1, 2, …, N represents the rising edge vector V rr Max (·) represents the maximum value taking operation, V 1 (S-1) represents the maximum response voltage value, V, of the S-1 bit pattern input by the load current source of the power distribution network when the S-1 bit pattern is' 1 0 (S-1) represents the maximum response voltage value when the S-1 bit pattern input by the load current source of the power distribution network is "0", when s=1, V 1 (S-1)＝0、V 0 (S-1)＝0，V rr (i) Representing rising edge vector V rr I=1, 2, …, N;
(4b) The maximum response voltage value of each bit input by the load current source of the power distribution network when the code pattern is 0 is calculated according to the following steps:
V 0 (S)＝max(V 0 (S-1),V 1 (S-1)+V ff (j))
wherein V is 0 (S) represents the maximum response voltage value, V, when the S bit code pattern input by the load current source of the power distribution network is 0 ff (j) Representing falling edgesVector V ff The value of j is correspondingly equal to i;
(4c) Calculating the maximum response voltage value V of the last bit code pattern input by the load current source of the power distribution network according to the following formula max ：
V max ＝max(V 1 (S)+V high ,V 0 (S)+V low )；
(4d) The minimum response voltage value of each bit of the power distribution network load current source input when the code pattern is '1' is calculated according to the following steps:
V 11 (S)＝min(V 11 (S-1),V 00 (S-1)+V rr (i))
wherein V is 11 (S) represents the minimum response voltage value when the S bit code pattern input by the load current source of the power distribution network is '1', and min (DEG) represents the operation of taking the minimum value, V 11 (S-1) represents the minimum response voltage value, V, when the S-1 bit pattern input by the load current source of the power distribution network is' 1 00 (S-1) represents the minimum response voltage value when the S-1 bit pattern input by the load current source of the power distribution network is "0", when s=1, V 11 (S-1)＝0、V 00 (S-1)＝0；
(4e) The minimum response voltage value of each bit of the power distribution network load current source input when the code pattern is 0 is calculated according to the following steps:
V 00 (S)＝min(V 00 (S-1),V 11 (S-1)+V ff (j))
wherein V is 00 (S) represents the minimum response voltage value when the S bit code pattern input by the load current source of the power distribution network is 0;
(4f) The minimum response voltage value V of the last bit code pattern input by the load current source of the power distribution network is calculated according to the following steps min ：
V min ＝min(V 11 (S)+V high ,V 00 (S)+V low )；
(4g) Calculating worst voltage noise V of power distribution network worst ＝V max -V min 。
2. The edge-response-based PDN network worst-case voltage noise prediction method according to claim 1, wherein the sampling frequency F in step (3 a) is obtained by the following formula:
F≥20*max(F 1 ,F 2 ,…,F n )
wherein F is n Representing the nth antiresonant frequency value in the power distribution network impedance curve, representing the multiplication operation, and max (·) representing the maximum value taking operation.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106777843A (en) * | 2017-03-17 | 2017-05-31 | 西安电子科技大学 | Plate level power supply distribution network Decoupling Design method based on maximum time domain transient noise |
| CN106886636A (en) * | 2017-01-23 | 2017-06-23 | 西安电子科技大学 | A kind of accurate Forecasting Methodology of the worst power supply noise of high-speed circuit system |
| CN106886637A (en) * | 2017-01-23 | 2017-06-23 | 西安电子科技大学 | Time Domain Analysis based on PDN Yu passage Cooperative Analysis method |
| CN108959779A (en) * | 2018-07-06 | 2018-12-07 | 西安电子科技大学 | Decoupling network design method based on power supply noise time domain analytical analysis |
| CN109522653A (en) * | 2018-11-16 | 2019-03-26 | 西安电子科技大学 | A kind of PDN AC noise analysis method of three dimensional integrated circuits |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9435840B2 (en) * | 2013-01-07 | 2016-09-06 | Mentor Graphics Corporation | Determining worst-case bit patterns based upon data-dependent jitter |
| US10733347B2 (en) * | 2014-07-07 | 2020-08-04 | Mentor Graphics Corporation | Statistical channel analysis with correlated input patterns |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106886636A (en) * | 2017-01-23 | 2017-06-23 | 西安电子科技大学 | A kind of accurate Forecasting Methodology of the worst power supply noise of high-speed circuit system |
| CN106886637A (en) * | 2017-01-23 | 2017-06-23 | 西安电子科技大学 | Time Domain Analysis based on PDN Yu passage Cooperative Analysis method |
| CN106777843A (en) * | 2017-03-17 | 2017-05-31 | 西安电子科技大学 | Plate level power supply distribution network Decoupling Design method based on maximum time domain transient noise |
| CN108959779A (en) * | 2018-07-06 | 2018-12-07 | 西安电子科技大学 | Decoupling network design method based on power supply noise time domain analytical analysis |
| CN109522653A (en) * | 2018-11-16 | 2019-03-26 | 西安电子科技大学 | A kind of PDN AC noise analysis method of three dimensional integrated circuits |
Non-Patent Citations (3)
| Title |
|---|
| Fast Multiple Edge Response Method Based on the Design of Experiment and Machine Learning;Xiuqin Chu 等;《IEEE Microwave and Wireless Components Letters》;20210531;第31卷(第5期);第521-524页 * |
| 一种改进的Canny边缘检测算法;李红 等;《微计算机信息》;20081225;第24卷;第298-299页 * |
| 高速电路中PDN电源噪声分析及去耦网络设计;鱼鹏;《中国优秀硕士学位论文全文数据库 信息科技辑》;20190215(第2期);第I135-330页 * |
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