CN114019736B - Display substrate and display device - Google Patents
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- CN114019736B CN114019736B CN202111304276.5A CN202111304276A CN114019736B CN 114019736 B CN114019736 B CN 114019736B CN 202111304276 A CN202111304276 A CN 202111304276A CN 114019736 B CN114019736 B CN 114019736B
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- 239000000758 substrate Substances 0.000 title claims abstract description 191
- 239000010410 layer Substances 0.000 claims abstract description 233
- 239000011241 protective layer Substances 0.000 claims abstract description 121
- 229910052751 metal Inorganic materials 0.000 claims abstract description 94
- 239000002184 metal Substances 0.000 claims abstract description 94
- 239000012044 organic layer Substances 0.000 claims abstract description 92
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 40
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 40
- 239000010408 film Substances 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 34
- 239000010409 thin film Substances 0.000 claims abstract description 33
- 238000007789 sealing Methods 0.000 claims abstract description 28
- 239000003292 glue Substances 0.000 claims abstract description 27
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 20
- 230000002093 peripheral effect Effects 0.000 claims abstract description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 25
- 239000000956 alloy Substances 0.000 claims description 25
- ANUQVPMOKIYKBZ-UHFFFAOYSA-N [Ti].[Ni].[Mo] Chemical group [Ti].[Ni].[Mo] ANUQVPMOKIYKBZ-UHFFFAOYSA-N 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 4
- 230000007797 corrosion Effects 0.000 abstract description 9
- 238000005260 corrosion Methods 0.000 abstract description 9
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical group [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 22
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910010272 inorganic material Inorganic materials 0.000 description 10
- 239000011147 inorganic material Substances 0.000 description 10
- 230000008859 change Effects 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 2
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 2
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000012945 sealing adhesive Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 1
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides a display substrate including: the display device comprises an array substrate, a color film substrate, a liquid crystal layer, a grid driving circuit and frame sealing glue, wherein projections of first parts and second parts of a plurality of clock signal lines on a substrate are overlapped, and an overlapping area is formed in the overlapping area; a first inorganic protective layer and a second inorganic protective layer covering the metal oxide thin film transistor, and an organic layer between the first inorganic protective layer and the second inorganic protective layer; the region between the organic layer and one of the side surfaces of the substrate is a hollowed-out region, so that the frame sealing glue completely covers the first inorganic protective layer and the second inorganic protective layer, and part of the region covers the organic layer or does not cover the organic layer at all. According to the invention, according to the relative positions of the organic layer, the frame sealing glue area and the overlapping area, the corrosion risk of the peripheral metal wiring is reduced by arranging the hollowed-out area on the organic layer, changing the material of the peripheral metal wiring and changing the material of the first inorganic protective layer.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate and a display device.
Background
In the field of display technology, the performance of TFTs (Thin Film Transistor, thin film transistors) is particularly important as key devices for controlling pixel switching and signal transmission. Currently, the active layer materials mainly comprise amorphous silicon, metal oxide and low-temperature polysilicon. Among them, metal oxide TFTs are widely used for products with high refresh rate, high PPI (Pixels Per Inch), high transmittance, etc. due to their characteristics of high electron mobility, low off-state current, good uniformity, etc.
However, the metal oxide TFT is sensitive to impurities such as oxyhydrogen, which have a great influence on the characteristics of the TFT, and in severe cases, damages the normal operation of the gate driving circuit or the TFT of the display region. The improvement of the sealing performance of the frame sealing glue area of the display panel is one of the key factors.
Disclosure of Invention
The embodiment of the invention provides a display substrate and a display device, which can improve the high temperature and high humidity resistance of a metal oxide product and reduce the corrosion risk of peripheral metal wires.
A first aspect of the present invention provides a display substrate comprising:
the liquid crystal display comprises an array substrate, a color film substrate, a liquid crystal layer positioned between the array substrate and the color film substrate, a gate driving circuit and frame sealing glue positioned in the peripheral area of the display substrate, wherein the gate driving circuit comprises a plurality of metal oxide thin film transistors;
the array substrate comprises a substrate, wherein the substrate comprises an upper surface and four side surfaces;
the plurality of clock signal lines are positioned on the substrate base plate, each clock signal line comprises a first part and a second part which are arranged on different layers, the first part is connected with the second part through a through hole, and the second part is connected with the metal oxide thin film transistor in the grid driving circuit;
the first parts and the second parts of the clock signal lines are overlapped in projection of the substrate, and an overlapping area is formed in the overlapping area;
a first inorganic protective layer and a second inorganic protective layer covering the metal oxide thin film transistor, and an organic layer between the first inorganic protective layer and the second inorganic protective layer;
the first inorganic protective layer and the second inorganic protective layer extend from the area covering the metal oxide thin film transistor to the frame sealing glue area to be flush with one side surface of the substrate base plate;
the first inorganic protective layer and the second inorganic protective layer are at least in the frame sealing glue area, and the whole surface of the first inorganic protective layer and the second inorganic protective layer is continuous and has no hollowed-out area;
the region between the organic layer and one of the side surfaces of the substrate is a hollowed-out region, so that the frame sealing glue completely covers the first inorganic protective layer and the second inorganic protective layer, and a part of the region covers the organic layer or does not cover the organic layer at all.
Optionally, the second portion of the clock signal line is located closer to the organic layer than the first portion of the clock signal line.
Optionally, the clock signal line includes at least two layers, one layer is a metal line, the other layer is a protection layer of the metal line, and the protection layer is an alloy.
Optionally, a second distance is provided between the overlap nearest to one of the sides of the substrate and one of the sides of the substrate, and when the second distance is greater than or equal to 1000um, the area between the overlap area and the one of the sides of the substrate is a hollowed-out area.
Optionally, a second distance is provided between the overlap nearest to one of the sides of the substrate and one of the sides of the substrate, when the second distance is smaller than 1000um, the area between the overlap area and the one of the sides of the substrate is a hollowed-out area, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium.
Optionally, a first interval is arranged between the organic layer and one of the side surfaces of the substrate, when the first interval is more than or equal to 600um, the area between the organic layer and one of the side surfaces of the substrate is a hollowed-out area,
the organic layer in the overlapping area is provided with a hollowed-out area, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium.
Optionally, a first distance is provided between the organic layer and one of the sides of the substrate, and when the first distance is less than 600um, the area between the organic layer and one of the sides of the substrate is a hollowed-out area,
the organic layer in the overlapping area is provided with a hollowed-out area, the alloy of the protective layer of the clock signal line is molybdenum nickel titanium, the first inorganic protective layer at least comprises two layers, the outer layer close to the organic layer is silicon nitride, the bottom layer far away from the organic layer is silicon oxide, and the second part of the clock signal line is positioned below the silicon oxide layer and is in contact with the silicon oxide layer.
Optionally, the metal oxide thin film transistor includes:
a gate metal layer located on the upper surface of the substrate base plate;
a gate insulating layer covering the gate metal layer;
an active layer located on a side of the gate insulating layer away from the substrate base plate;
and the source-drain metal layer is positioned above the active layer.
Optionally, the clock signal line and the source drain metal layer are disposed in the same material.
A second aspect of the present invention provides a display device including the display substrate described above.
The embodiment of the invention has the following beneficial effects:
according to the invention, according to the relative positions of the organic layer, the frame sealing glue region and the overlapping region, the region between the organic layer and one of the side surfaces of the substrate base plate is hollowed, so that the high temperature and high humidity resistance of the metal oxide product is improved, and the corrosion risk of peripheral metal wiring is reduced.
Drawings
Fig. 1 is a structural diagram of a display substrate in the related art;
FIG. 2 is a schematic diagram of corrosion occurring at an overlap in the related art;
FIG. 3 is a schematic diagram showing the connection positions of the clock signal lines and the gate driving circuit in the related art;
FIG. 4 is a schematic cross-sectional view of a first display substrate according to an embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a second display substrate according to an embodiment of the invention.
Reference numerals
1. Substrate base
2a first Gate insulation layer
2b second Gate insulation layer
3. First inorganic protective layer
3a bottom layer of the first inorganic protective layer remote from the organic layer
3b first inorganic protective layer is close to the top layer of the organic layer
4. A second inorganic protective layer
5. Organic layer
6. Frame sealing adhesive
7. Liquid crystal layer
8. Upper panel
9. Black matrix
10. Color film
11a first portion of the clock signal line
11b second portion of clock signal line
L1 first spacing
L2 second spacing
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention more apparent, the following detailed description will be given with reference to the accompanying drawings and the specific embodiments.
The insulating layer above the active layer is generally an oxide inorganic layer because of the requirement of stable TFT characteristics of the metal oxide product, however, the waterproof property of the oxide inorganic material is poorer than that of the nitride inorganic layer, and external water vapor easily enters the active layer to easily cause corrosion of the metal wiring under the action of H or O or failure of the active layer under the action of H and O.
The display panel can effectively reduce the entry of peripheral water vapor and other impurities through arranging the film layer near the frame sealing glue in the peripheral area.
Fig. 1 is a block diagram of a display substrate in the related art, as shown in fig. 1, the display substrate includes an array substrate, a color film substrate, and a liquid crystal layer 7 between the array substrate and the color film substrate, and a frame sealing adhesive 6 surrounding the liquid crystal layer;
the array substrate comprises a substrate 1, wherein the substrate 1 comprises an upper surface and four side surfaces, the four side surfaces are cut surfaces after a mother board is cut, and the substrate can be a glass substrate or a quartz substrate;
the TFT on the substrate 1 will be described by taking the TFT as a bottom gate structure;
the TFT comprises a grid metal layer positioned on a substrate 1, wherein the grid metal layer comprises at least two layers, one layer is a metal wire, the other layer is a protective layer of the metal wire, the protective layer is an alloy, the alloy is molybdenum and niobium, and the metal wire is a copper wire or an aluminum wire;
a first gate insulating layer 2a covering the gate metal layer, the first gate insulating layer 2a being a nitride inorganic material such as silicon nitride;
an active layer located on one side of the first gate insulating layer 2a away from the substrate 1, wherein the active layer is made of metal oxide;
a second gate insulating layer 2b covering the active layer, the second gate insulating layer 2b being an oxide inorganic material such as silicon oxide;
the source-drain metal layer is positioned above the second gate insulating layer 2b, wherein the source-drain metal layer comprises at least two layers, one layer is a metal wire, the other layer is a protective layer of the metal wire, the protective layer is an alloy, the alloy is molybdenum-niobium, the metal wire is a copper wire or an aluminum wire, and the source-drain metal layer and the gate metal layer are made of the same material;
a first inorganic protective layer 3 covering the source-drain metal layer for protecting the TFT, wherein the first inorganic protective layer 3 comprises one or more layers, the one or more layers at least comprise a silicon oxide film layer, and the first inorganic protective layer shown in fig. 1 comprises a silicon oxide film layer;
a second inorganic protective layer 4 covering the first inorganic protective layer 3, the second inorganic protective layer 4 comprising an inorganic nitride film layer, illustratively, a silicon nitride or silicon oxynitride film layer;
an organic layer 5 located between the first inorganic protective layer 3 and the second inorganic protective layer 4, the organic layer 5 serving to play a planarization role between the first inorganic protective layer 3 and the second inorganic protective layer 4;
the display substrate further comprises a plurality of clock signal lines positioned on the substrate, each clock signal line comprises a first part 11a and a second part 11b which are arranged on different layers, the first part 11a is connected with the second part 11b through a through hole, the second part 11b is connected with the metal oxide thin film transistor in the gate driving circuit, and the projections of the first part 11a and the second part 11b of the plurality of clock signal lines on the substrate 1 are overlapped, so that an overlapped area is formed in the overlapped area;
a peripheral region of the display substrate is provided with a gate driving circuit including a plurality of metal oxide thin film transistors, and the second portion 11b of the clock signal line is connected to the metal oxide thin film transistors in the gate driving circuit;
the display panel described above describes an array substrate, and further includes color film substrates and a liquid crystal layer 7 disposed between the color film substrates, where the color film substrates include an upper panel 8 of the display panel, a black matrix 9, and a color film 10.
The liquid crystal in the liquid crystal layer can deflect to different degrees under different voltages, so that different transmittance can be realized, and after light passes through the liquid crystal layer, color display can be realized by matching with a color film substrate.
Referring to fig. 1, external moisture intrudes into the display substrate from the gap between the second inorganic protective layers 4 of the first inorganic protective layer 3, the organic layer 5 has been extended to the sealant region and covers the overlapped region, and moisture reaches the source drain metal layer because the organic layer 5 is easily absorbed water and the material of the first inorganic protective layer 3 is silicon oxide having poor water repellency. The protective layer material of the source-drain metal layer is molybdenum-niobium, which is easy to be corroded by H or O relative to molybdenum-nickel-titanium, so that the metal wiring (such as the second part of the clock signal line) of the source-drain metal layer is easy to corrode and electrically connected with the first part of the clock signal line in the overlapping area, thereby causing short circuit.
Referring to fig. 1, a portion of the clock signal line where the second portion 11b and the first portion 11a of the clock signal line are located in the frame molding region has an overlapping region perpendicular to the substrate 1. In the overlap region, the second portion 11b of the clock signal line erodes under the influence of H or O, wherein the first portion 11a of the clock signal line is located in a different layer than the second portion 11b of the clock signal line.
Fig. 2 is a schematic diagram showing corrosion occurring at the overlapping portion in the related art, and as shown in fig. 2, the first portion 11a of the first clock signal line is connected to the second portion 11b of the first clock signal line through a via hole, and the first portion 11a of the first clock signal line overlaps with projections of the first portions of the second, third and fourth clock signal lines on the substrate 1 during connection to the metal oxide thin film transistor of the gate driving circuit. The first portion 11a of the second clock signal line is connected to the second portion 11b of the second clock signal line through a via hole, and overlaps with projections of the first portions of the third and fourth clock signal lines on the substrate 1 in the process of connecting the first portion 11a of the second clock signal line to the metal oxide thin film transistor of the gate driving circuit.
The first portion 11a of the first clock signal line has no overlapping with the second portion 11b of the first clock signal line, and the first portion 11a of the second clock signal line has a smaller overlapping area with the second portion 11b of the first clock signal line, so that the first portions of the first and second clock signal lines do not corrode when moisture accumulates. The first portion 11a of the third clock signal line is corroded by H or O due to overlapping with the second portions 11b of the first and second clock signal lines, and the first and second clock signal lines are short-circuited where the third clock signal line is corroded when the clock signal is transmitted to the gate driving circuit, that is, for one to two clock signal lines near the outer edge of the display substrate, the short-circuited clock signal line is generally started from the third clock signal line, irrespective of the occurrence of the short circuit.
Fig. 3 is a schematic diagram of connection positions of the clock signal lines and the gate driving circuit in the related art, as shown in fig. 3, the first clock signal line CLK1, the second clock signal line CLK2 and the third clock signal line CLK3 are connected to the gate driving circuit GOA, and the output of the gate driving circuit GOA provides driving voltages for the gates of the metal oxide thin film transistors located in the Active Area (AA). The second portion of the first clock signal line CLK1 has an overlap with the first portions of the second clock signal line CLK2 and the third clock signal line CLK 3.
It should be noted that: since the high-frequency signal is transmitted on the clock signal line, heat is easily generated at the overlapping portion, and thus corrosion is more easily generated by H or O. The direct current low voltage signal wire VSS of the grid driving circuit has the advantages that the heat generation phenomenon between the direct current low voltage signal wire and the direct current low voltage signal lead wire is not obvious due to the transmission of the direct current signal, and the corrosion phenomenon at the overlapping part of the direct current low voltage signal wire and the direct current low voltage signal lead wire is also not obvious, so the situation of short circuit of the direct current low voltage signal wire VSS is not considered temporarily.
In order to solve the problem that metal wires in the peripheral area of a display substrate are easy to corrode in the related art, the invention provides the display substrate and the display device.
The display substrate provided by the embodiment of the invention comprises:
the liquid crystal display comprises an array substrate, a color film substrate, a liquid crystal layer positioned between the array substrate and the color film substrate, a gate driving circuit and frame sealing glue positioned in the peripheral area of the display substrate, wherein the gate driving circuit comprises a plurality of metal oxide thin film transistors; it is characterized in that the method comprises the steps of,
the array substrate comprises a substrate, wherein the substrate comprises an upper surface and four side surfaces;
the plurality of clock signal lines are positioned on the substrate base plate, each clock signal line comprises a first part and a second part which are arranged on different layers, the first part is connected with the second part through a through hole, and the second part is connected with the metal oxide thin film transistor in the grid driving circuit;
the first parts and the second parts of the clock signal lines are overlapped in projection of the substrate, and an overlapping area is formed in the overlapping area;
a first inorganic protective layer and a second inorganic protective layer covering the metal oxide thin film transistor, and an organic layer between the first inorganic protective layer and the second inorganic protective layer;
the first inorganic protective layer and the second inorganic protective layer extend from the area covering the metal oxide thin film transistor to the frame sealing glue area to be flush with one side surface of the substrate base plate;
the first inorganic protective layer and the second inorganic protective layer are at least in the frame sealing glue area, and the whole surface of the first inorganic protective layer and the second inorganic protective layer is continuous and has no hollowed-out area;
the region between the organic layer and one of the side surfaces of the substrate is a hollowed-out region, so that the frame sealing glue completely covers the first inorganic protective layer and the second inorganic protective layer, and a part of the region covers the organic layer or does not cover the organic layer at all.
Fig. 4 is a schematic cross-sectional view of a first display substrate according to an embodiment of the present invention, where the display substrate according to the embodiment of the present invention includes:
the liquid crystal display comprises an array substrate, a color film substrate, a liquid crystal layer 7 positioned between the array substrate and the color film substrate, a gate driving circuit and frame sealing glue 6 positioned in the peripheral area of the display substrate, wherein the gate driving circuit comprises a plurality of metal oxide thin film transistors;
the array substrate comprises a substrate 1, wherein the substrate 1 comprises an upper surface and four side surfaces, and the four side surfaces are cut surfaces of a mother board after cutting;
a plurality of clock signal lines located on the substrate 1, each clock signal line including a first portion 11a and a second portion 11b disposed on different layers, the first portion 11a and the second portion 11b being connected by a via hole, the second portion 11b being connected to the metal oxide thin film transistor in the gate driving circuit;
the projections of the first portions 11a and the second portions 11b of the clock signal lines on the substrate 1 are overlapped, and an overlapping area is formed in the overlapping area;
a first inorganic protective layer 3 and a second inorganic protective layer 4 covering the metal oxide thin film transistor, and an organic layer 5 between the first inorganic protective layer 3 and the second inorganic protective layer 4;
wherein the first inorganic protective layer 3 comprises a bottom layer 3a far from the organic layer 5 and a top layer 3b near the organic layer 5;
the first inorganic protective layer 3 and the second inorganic protective layer 4 extend from the area covering the metal oxide thin film transistor to the frame sealing glue area to be flush with one of the side surfaces of the substrate base plate 1;
the first inorganic protective layer 3 and the second inorganic protective layer 4 are continuous whole-surface non-hollowed-out areas at least at the parts of the frame sealing glue areas;
the area between the organic layer 5 and one of the side surfaces of the substrate 1 is a hollowed area, so that the frame sealing glue 6 completely covers the first inorganic protective layer 3 and the second inorganic protective layer 4, and a part of the area covers the organic layer 5 or does not cover the organic layer 5 at all.
Optionally, the metal oxide thin film transistor includes:
a gate metal layer located on the upper surface of the substrate base plate;
a gate insulating layer covering the gate metal layer;
an active layer located on a side of the gate insulating layer away from the substrate base plate;
and the source-drain metal layer is positioned above the active layer.
Referring to fig. 4, the embodiment will be described taking a TFT as an example of a bottom gate structure, the TFT including a gate metal layer on a substrate 1;
a first gate insulating layer 2a covering the gate metal layer, the first gate insulating layer 2a being a nitride inorganic material such as silicon nitride;
an active layer which is positioned on one side of the first gate insulating layer 2a far away from the substrate 1, wherein the active layer is made of metal oxide;
a second gate insulating layer 2b covering the active layer, the second gate insulating layer 2b being an oxide inorganic material such as silicon oxide;
the source-drain metal layer is located above the second gate insulating layer 2b, wherein the source-drain metal layer comprises at least two layers, one layer is a metal wire, the other layer is a protective layer of the metal wire, the protective layer is an alloy, the alloy is molybdenum-niobium, the metal wire is a copper wire or an aluminum wire, and the source-drain metal layer and the gate metal layer are made of the same material.
Optionally, the second portion 11b of the clock signal line is located above the first portion 11a of the clock signal line closer to the organic layer 5.
Optionally, a second distance is provided between the overlap nearest to one of the sides of the substrate and one of the sides of the substrate, and when the second distance is greater than or equal to 1000um, the area between the overlap area and the one of the sides of the substrate is a hollowed-out area.
In the display substrate shown in fig. 4, the organic layer 5 has been extended to the sealant region, but does not cover the overlapping region.
As shown in fig. 4, an overlap closest to one of the sides of the substrate and having a short circuit phenomenon is located on the 3 rd clock signal line, one of the sides of the substrate and the 3 rd clock signal line have a second pitch L2 therebetween, and when the second pitch L2 is equal to or greater than 1000um, the overlap region and the region between the overlap region and one of the sides of the substrate are hollowed-out regions, i.e., the organic layer 5 of the overlap region and the region between the overlap region and one of the sides of the substrate is hollowed-out. At this time, the distance that the water vapor reaches the overlapping area is not very small, only the overlapping area and the organic layer between the overlapping area and one of the side surfaces of the substrate need to be dug away, and further, the farther the organic layer 5 is from one of the side surfaces of the substrate, the farther the organic layer 5 absorbs water, and the less water vapor is absorbed by the organic layer 5, the water penetrating from the organic layer 5 to the gate metal layer or the source drain metal layer is reduced, so that the water at the overlapping position is reduced, and short circuit is prevented from occurring at the overlapping position.
Further, if the distance between the water vapor and the overlapping area is not very small, the film structure of the display substrate does not need to be changed, and the material of the film with poor waterproof performance in the film structure does not need to be changed, so that the distance between the organic layer 5 and one side surface of the substrate is only increased.
Further, when the second distance L2 is smaller than 1000um, that is, the distance from the vapor to the overlapping area is reduced compared with the distance from L2 to 1000um, the display substrate needs to further enhance the water-proof capability, and the material of the protective layer of the source-drain metal layer needs to be changed, so that the water-proof capability is increased.
Optionally, a second distance is provided between the overlap nearest to one of the sides of the substrate and one of the sides of the substrate, when the second distance is smaller than 1000um, the area between the overlap area and the one of the sides of the substrate is a hollowed-out area, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium.
In the related art, the source-drain metal layer comprises at least two layers, one layer is a metal wire, the other layer is a protective layer of the metal wire, the protective layer is an alloy, the alloy is molybdenum-niobium, and the metal wire is a copper wire or an aluminum wire. Illustratively, the source-drain metal layer includes a molybdenum-niobium layer, a copper layer, and a molybdenum-niobium layer, which are sequentially stacked.
However, as the distance of the vapor reaching the overlapping area becomes smaller, in addition to increasing the distance between the organic layer 5 and one of the sides of the substrate, a change is required to be made to the material of the film layer with poor waterproof performance in the film layer structure, but no change is required to the film layer structure of the display substrate.
Specifically, the material of the protective layer of the source-drain metal layer can be changed into molybdenum nickel titanium. The source-drain metal layer provided by the embodiment of the invention at least comprises two layers, wherein one layer is a metal wire, the other layer is a protective layer of the metal wire, the protective layer is an alloy, and the alloy is molybdenum nickel titanium.
The clock signal lead and the source-drain metal layer are made of the same material, and the material of the clock signal lead is changed while the material of the protective layer of the source-drain metal layer is changed.
If the source-drain metal layer in the related art is a molybdenum-niobium layer, a copper layer and a molybdenum-niobium layer which are sequentially stacked, the molybdenum-niobium layer on one side of the source-drain metal layer, which is close to the organic layer 5, needs to be changed into a molybdenum-nickel-titanium layer, and the molybdenum-niobium layer on the bottom layer, which is far away from the organic layer 5, can be changed into a molybdenum-nickel-titanium layer, or can be unchanged.
If the source drain metal layer in the related art only comprises a copper layer and a molybdenum-niobium layer, the molybdenum-niobium layer is only required to be changed into a molybdenum-nickel-titanium layer.
The molybdenum nickel titanium material is not easy to be corroded by H or O relative to the molybdenum niobium material, so that the phenomenon that the metal wires (such as the second part of the clock signal wire) of the source and drain metal layers are electrically connected with the first part of the clock signal wire in the overlapped area due to longitudinal growth of water absorption to cause short circuit can be avoided.
It should be noted that the material of the gate metal layer may or may not be changed.
Referring to fig. 5, fig. 5 is a schematic cross-sectional view of a second display substrate according to an embodiment of the present invention, where the display substrate according to the embodiment of the present invention includes:
the liquid crystal display comprises an array substrate, a color film substrate, a liquid crystal layer 7 positioned between the array substrate and the color film substrate, a gate driving circuit and frame sealing glue 6 positioned in the peripheral area of the display substrate, wherein the gate driving circuit comprises a plurality of metal oxide thin film transistors;
the array substrate comprises a substrate 1, wherein the substrate 1 comprises an upper surface and four side surfaces, and the four side surfaces are cut surfaces of a mother board after cutting;
a plurality of clock signal lines located on the substrate 1, each clock signal line including a first portion 11a and a second portion 11b disposed on different layers, the first portion 11a and the second portion 11b being connected by a via hole, the second portion 11b being connected to the metal oxide thin film transistor in the gate driving circuit;
the projections of the first portions 11a and the second portions 11b of the clock signal lines on the substrate 1 are overlapped, and an overlapping area is formed in the overlapping area;
a first inorganic protective layer 3 and a second inorganic protective layer 4 covering the metal oxide thin film transistor, and an organic layer 5 between the first inorganic protective layer 3 and the second inorganic protective layer 4;
wherein the first inorganic protective layer 3 comprises a bottom layer 3a far from the organic layer 5 and a top layer 3b near the organic layer 5;
the first inorganic protective layer 3 and the second inorganic protective layer 4 extend from the area covering the metal oxide thin film transistor to the frame sealing glue area to be flush with one of the side surfaces of the substrate base plate 1;
the first inorganic protective layer 3 and the second inorganic protective layer 4 are continuous whole-surface non-hollowed-out areas at least at the parts of the frame sealing glue areas;
the area between the organic layer 5 and one of the side surfaces of the substrate 1 is a hollowed area, so that the frame sealing glue 6 completely covers the first inorganic protective layer 3 and the second inorganic protective layer 4, and a part of the area covers the organic layer 5 or does not cover the organic layer 5 at all.
Optionally, the metal oxide thin film transistor includes:
a gate metal layer located on the upper surface of the substrate base plate;
a gate insulating layer covering the gate metal layer;
an active layer located on a side of the gate insulating layer away from the substrate base plate;
and the source-drain metal layer is positioned above the active layer.
This embodiment will be described taking a TFT as an example of a bottom gate structure, the TFT including a gate metal layer on a substrate 1;
a first gate insulating layer 2a covering the gate metal layer, the first gate insulating layer 2a being a nitride inorganic material such as silicon nitride;
an active layer which is positioned on one side of the first gate insulating layer 2a far away from the substrate 1, wherein the active layer is made of metal oxide;
a second gate insulating layer 2b covering the active layer, the second gate insulating layer 2b being an oxide inorganic material such as silicon oxide;
the source-drain metal layer is located above the second gate insulating layer 2b, wherein the source-drain metal layer comprises at least two layers, one layer is a metal wire, the other layer is a protective layer of the metal wire, the protective layer is an alloy, the alloy is molybdenum-niobium, the metal wire is a copper wire or an aluminum wire, and the source-drain metal layer and the gate metal layer are made of the same material.
Optionally, a first interval is arranged between the organic layer and one of the side surfaces of the substrate, when the first interval is more than or equal to 600um, the area between the organic layer and one of the side surfaces of the substrate is a hollowed-out area,
the organic layer in the overlapping area is provided with a hollowed-out area, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium.
Wherein, as shown in the display substrate of fig. 5, on the basis of fig. 4, the organic layer 5 has not only been extended to the frame sealing glue area, but has also covered the overlapping area, i.e. the distance between the organic layer and one of the sides of the substrate is further reduced. At this time, the distance between one of the side surfaces of the substrate and the 3 rd clock signal line has not been taken as a reference because the distance between the organic layer and one of the side surfaces of the substrate is closer than the distance between the 3 rd clock signal line and one of the side surfaces of the substrate, and thus, the first pitch L1 between the organic layer and one of the side surfaces of the substrate is taken as a reference.
Further, when L1 is greater than or equal to 600um, the area between the organic layer and one of the sides of the substrate is a hollowed-out area, and the hollowed-out area needs to be set for the organic layer in the overlapping area.
The organic layer 5 in the overlapping area is provided with a hollowed-out area, so that water vapor aggregation can be further prevented, and corrosion of H or O on metal wires in the overlapping area can be prevented.
Further, it is also necessary to change the material of the film layer having poor waterproof performance in the film layer structure, but it is not necessary to change the film layer structure of the display substrate.
Specifically, the material of the protective layer of the source-drain metal layer can be changed into molybdenum nickel titanium. The source-drain metal layer provided by the embodiment of the invention at least comprises two layers, wherein one layer is a metal wire, the other layer is a protective layer of the metal wire, the protective layer is an alloy, and the alloy is molybdenum nickel titanium.
If the source-drain metal layer in the related art is a molybdenum-niobium layer, a copper layer and a molybdenum-niobium layer which are sequentially stacked, the molybdenum-niobium layer on one side of the source-drain metal layer, which is close to the organic layer 5, needs to be changed into a molybdenum-nickel-titanium layer, and the molybdenum-niobium layer on the bottom layer, which is far away from the organic layer 5, can be changed into a molybdenum-nickel-titanium layer, or can be unchanged.
If the source drain metal layer in the related art only comprises a copper layer and a molybdenum-niobium layer, the molybdenum-niobium layer is only required to be changed into a molybdenum-nickel-titanium layer.
The molybdenum nickel titanium material is not easy to be corroded by H or O relative to the molybdenum niobium material, so that the phenomenon that the metal wires (such as the second part of the clock signal wire) of the source and drain metal layers are electrically connected with the first part of the clock signal wire in the overlapped area due to longitudinal growth of water absorption to cause short circuit can be avoided.
It should be noted that the material of the gate metal layer may or may not be changed.
Optionally, a first distance is provided between the organic layer and one of the sides of the substrate, and when the first distance is less than 600um, the area between the organic layer and one of the sides of the substrate is a hollowed-out area,
the organic layer in the overlapping area is provided with a hollowed-out area, the alloy of the protective layer of the clock signal line is molybdenum nickel titanium, the first inorganic protective layer at least comprises two layers, the outer layer close to the organic layer is silicon nitride, the bottom layer far away from the organic layer is silicon oxide, and the second part of the clock signal line is positioned below the silicon oxide layer and is in contact with the silicon oxide layer.
Further, when L1 is smaller than 600um, that is, the distance between the organic layer and one of the sides of the substrate is further reduced, the display substrate needs to further enhance the waterproof capability, and not only needs to set a hollowed-out area for the organic layer in the overlapping area, but also needs to change the material of the protective layer of the source drain metal layer, and also needs to change the material of the first inorganic protective layer.
Optionally, the first inorganic protective layer at least comprises two layers, the outer layer close to the organic layer is silicon nitride, the bottom layer far away from the organic layer is silicon oxide, and the clock signal lead is located below the silicon oxide layer and is in contact with the silicon oxide.
If the material of the first inorganic protective layer near the top layer of the organic layer is an oxide inorganic material in the related art, the oxide inorganic material needs to be changed to a nitride inorganic material, for example, silicon oxide is changed to silicon nitride,
specifically, the top layer is a SiNx layer with a thickness ofThe bottom layer is SiOx with the thickness of->
Alternatively, a nitride inorganic layer may be further stacked on the top layer of the first inorganic protective layer adjacent to the organic layer
A material, specifically, a layer of SiNx with a thickness of 500A was superimposed on the original structure.
The use of the silicon nitride material for the first inorganic protective layer can enhance the vapor-proof capability of the display substrate because the silicon nitride material has better water-proof properties than silicon oxide.
In addition, the molybdenum nickel titanium material is not easy to be corroded by H or O relative to the molybdenum niobium material, so that the phenomenon that the metal wiring (such as the second part of the clock signal wire) of the source and drain metal layers is electrically connected with the first part of the clock signal wire in an overlapped area due to longitudinal growth of water absorption to cause short circuit can be avoided.
The embodiment of the invention also provides a display device which comprises the display substrate.
The display device includes, but is not limited to: the system comprises a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, a power supply and the like. It will be appreciated by those skilled in the art that the structure of the display device described above is not limiting of the display device, and that the display device may include more or less components described above, or may be combined with certain components, or may have different arrangements of components. In an embodiment of the invention, the display device includes, but is not limited to, a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
The display device may be: any product or component with display function such as a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet personal computer and the like, wherein the display device further comprises a flexible circuit board, a printed circuit board and a backboard.
In the method embodiments of the present invention, the serial numbers of the steps are not used to define the sequence of the steps, and it is within the scope of the present invention for those skilled in the art to change the sequence of the steps without performing any creative effort.
In this specification, all embodiments are described in a progressive manner, and identical and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in a different way from other embodiments. In particular, for the embodiments, since they are substantially similar to the product embodiments, the description is relatively simple, and the relevant points are found in the section of the product embodiments.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A display substrate, comprising:
the liquid crystal display comprises an array substrate, a color film substrate, a liquid crystal layer positioned between the array substrate and the color film substrate, a gate driving circuit and frame sealing glue positioned in the peripheral area of the display substrate, wherein the gate driving circuit comprises a plurality of metal oxide thin film transistors; it is characterized in that the method comprises the steps of,
the array substrate comprises a substrate, wherein the substrate comprises an upper surface and four side surfaces;
the plurality of clock signal lines are positioned on the substrate base plate, each clock signal line comprises a first part and a second part which are arranged on different layers, the first part is connected with the second part through a through hole, and the second part is connected with the metal oxide thin film transistor in the grid driving circuit;
the first parts and the second parts of the clock signal lines are overlapped in projection of the substrate, and an overlapping area is formed in the overlapping area;
a first inorganic protective layer and a second inorganic protective layer covering the metal oxide thin film transistor, and an organic layer between the first inorganic protective layer and the second inorganic protective layer;
the first inorganic protective layer and the second inorganic protective layer extend from the area covering the metal oxide thin film transistor to the frame sealing glue area to be flush with one side surface of the substrate base plate;
the first inorganic protective layer and the second inorganic protective layer are at least in the frame sealing glue area, and the whole surface of the first inorganic protective layer and the second inorganic protective layer is continuous and has no hollowed-out area;
the region between the organic layer and one of the side surfaces of the substrate is a hollowed-out region, so that the frame sealing glue completely covers the first inorganic protective layer and the second inorganic protective layer, and a part of the region covers the organic layer or does not cover the organic layer at all.
2. The display substrate of claim 1, wherein the display substrate comprises a transparent substrate,
the second portion of the clock signal line is located above the first portion of the clock signal line closer to the organic layer.
3. The display substrate according to claim 2, wherein,
the clock signal line comprises at least two layers, wherein one layer is a metal line, the other layer is a protective layer of the metal line, and the protective layer is an alloy.
4. The display substrate according to claim 1, wherein a second pitch is provided between an overlap nearest to one of the sides of the substrate and one of the sides of the substrate, and when the second pitch is 1000um or more, the overlap region and a region between the overlap region and one of the sides of the substrate are hollowed out regions.
5. A display substrate according to claim 3, wherein the overlap closest to one of the sides of the substrate and one of the sides of the substrate have a second spacing therebetween, and when the second spacing is less than 1000um, the overlap region and the region between the overlap region and one of the sides of the substrate are hollowed-out regions, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium.
6. The display substrate according to claim 3, wherein a first space is provided between the organic layer and one of the side surfaces of the substrate, when the first space is 600um or more, a region between the organic layer and one of the side surfaces of the substrate is a hollowed-out region, the organic layer in the overlapped region is provided with a hollowed-out region, and an alloy of a protective layer of the clock signal line is molybdenum nickel titanium.
7. The display substrate of claim 3, wherein the organic layer has a first spacing from one of the sides of the substrate, and wherein the area between the organic layer and one of the sides of the substrate is a hollowed-out area when the first spacing is less than 600um,
the organic layer in the overlapping area is provided with a hollowed-out area, the alloy of the protective layer of the clock signal line is molybdenum nickel titanium, the first inorganic protective layer at least comprises two layers, the outer layer close to the organic layer is silicon nitride, the bottom layer far away from the organic layer is silicon oxide, and the second part of the clock signal line is positioned below the silicon oxide layer and is in contact with the silicon oxide layer.
8. The display substrate according to claim 1, wherein the metal oxide thin film transistor comprises:
a gate metal layer located on the upper surface of the substrate base plate;
a gate insulating layer covering the gate metal layer;
an active layer located on a side of the gate insulating layer away from the substrate base plate;
and the source-drain metal layer is positioned above the active layer.
9. The display substrate according to claim 8, wherein the clock signal line and the source-drain metal layer are provided with the same material.
10. A display device comprising the display substrate according to any one of claims 1 to 9.
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