CN114005675A

CN114005675A - Multilayer ceramic capacitor

Info

Publication number: CN114005675A
Application number: CN202111331144.1A
Authority: CN
Inventors: 陆亨; 卓金丽; 刘伟峰; 田述仁; 何彦颖
Original assignee: Guangdong Fenghua Advanced Tech Holding Co Ltd
Current assignee: Guangdong Fenghua Advanced Tech Holding Co Ltd
Priority date: 2021-11-10
Filing date: 2021-11-10
Publication date: 2022-02-01

Abstract

The invention discloses a multilayer ceramic capacitor, comprising: a ceramic body, a first terminal electrode and a second terminal electrode; the ceramic body has an upper surface, a lower surface, a first end surface, a second end surface, a first side surface, and a second side surface formed by side surfaces of a plurality of laminated dielectric layers, the upper surface and the lower surface being disposed oppositely, the first end surface and the second end surface being disposed oppositely, the first side surface and the second side surface being disposed oppositely; the first terminal electrode is positioned on the first end face and covers partial surfaces of the upper surface, the lower surface, the first side face and the second side face, and the second terminal electrode is positioned on the second end face and covers partial surfaces of the upper surface, the lower surface, the first side face and the second side face; the internal electrodes include a first internal electrode connected to the first terminal electrode, a second internal electrode connected to the second terminal electrode, and a third internal electrode separated from the first and second internal electrodes by at least one dielectric layer, respectively. The voltage resistance of the multilayer ceramic capacitor is improved.

Description

Multilayer ceramic capacitor

Technical Field

The invention relates to the technical field of electronic components, in particular to a multilayer ceramic capacitor.

Background

In order to increase the voltage resistance of the multilayer ceramic capacitor, the series design is one of the commonly used design methods of the high-voltage multilayer ceramic capacitor, the length and width of the first internal electrode and the second internal electrode in the capacitor are respectively and correspondingly equal in the prior art, the first internal electrode and the second internal electrode are positioned on the same layer and directly opposite to each other, and the electric field intensity of the opposite end surfaces is highly concentrated due to the uniformly distributed structure of the first internal electrode and the second internal electrode, so that the breakdown and burning are easy to occur.

Disclosure of Invention

The invention aims to provide a multilayer ceramic capacitor, which takes the problem that the distance between corner positions is small due to the fact that a first inner electrode and a second inner electrode are directly arranged oppositely in the capacitor in the prior art into consideration, improves the opposite distance between the first inner electrode and the second inner electrode, achieves the purpose of increasing the distance between the corner positions, can bear higher voltage and improves the voltage resistance of the capacitor.

To achieve the above object, the present invention provides a multilayer ceramic capacitor comprising: a ceramic body, a first terminal electrode and a second terminal electrode;

the ceramic body is formed by alternately laminating a plurality of dielectric layers and a plurality of internal electrodes, and has an upper surface, a lower surface, a first end surface, a second end surface, a first side surface and a second side surface, which are formed by side surfaces of the plurality of laminated dielectric layers, the upper surface and the lower surface being oppositely disposed, the first end surface and the second end surface being oppositely disposed, the first side surface and the second side surface being oppositely disposed;

the first terminal electrode is positioned on the first end face and covers partial surfaces of the upper surface, the lower surface, the first side face and the second side face, and the second terminal electrode is positioned on the second end face and covers partial surfaces of the upper surface, the lower surface, the first side face and the second side face;

the inner electrode comprises a first inner electrode, a second inner electrode and a third inner electrode, the first inner electrode is connected with the first end electrode, the second inner electrode is connected with the second end electrode, the third inner electrode is respectively separated from the first inner electrode and the second inner electrode by at least one dielectric layer, the first inner electrode is flush with at least one part of the first end surface and the second end surface to form a first leading-out edge, the second inner electrode is flush with at least one part of the first end surface and the second end surface to form a second leading-out edge, and the length of the first leading-out edge is greater than that of the second leading-out edge.

In one embodiment, a gap is formed between the first internal electrode and the first and second side surfaces.

In one embodiment, a gap is formed between the second internal electrode and the first side surface and the second side surface.

In one embodiment, a gap distance formed between the first internal electrode and the first and second side surfaces is smaller than a gap distance formed between the second internal electrode and the first and second side surfaces.

In one embodiment, the orthographic projection of the first inner electrode on the third inner electrode is partially overlapped with the third inner electrode.

In one embodiment, the orthographic projection of the second inner electrode on the third inner electrode is partially overlapped with the third inner electrode.

In one embodiment, the opposing area generated by the orthographic projection of the first inner electrode on the third inner electrode is equal to the opposing area generated by the orthographic projection of the second inner electrode on the third inner electrode.

In one embodiment, a first capacitor is formed between the first internal electrode and the third internal electrode, a second capacitor is formed between the second internal electrode and the third internal electrode, and the first capacitor and the second capacitor are connected in series.

In one embodiment, the first internal electrode and the second internal electrode are stacked on the same dielectric layer.

In one embodiment, a gap is formed between each of the third inner electrodes and the first end surface and the second end surface.

Compared with the prior art, the invention has the beneficial effects that:

the first inner electrode is flush with at least one part of the first end surface and the second end surface to form a first leading-out edge, the second inner electrode is flush with at least one part of the first end surface and the second end surface to form a second leading-out edge, and the length of the first leading-out edge is greater than that of the second leading-out edge. The corner distance between the first leading-out edge and the second leading-out edge in the first inner electrode and the second inner electrode is increased, the concentration degree of an electric field is reduced, and breakdown and burning are prevented.

Furthermore, the opposing area generated by the orthographic projection of the first inner electrode on the third inner electrode is equal to the opposing area generated by the orthographic projection of the second inner electrode on the third inner electrode, so that the first capacitor is equal to the second capacitor, and the function of evenly distributing voltage is achieved.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention;

FIG. 2 is a schematic cross-sectional view of a multilayer ceramic capacitor according to another embodiment of the present invention;

FIG. 3 is a schematic sectional view of a multilayer ceramic capacitor according to still another embodiment of the present invention;

FIG. 4 is a schematic structural view of a multilayer ceramic capacitor according to an embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of a conventional series-designed multilayer ceramic capacitor;

FIG. 6 is an equivalent circuit of a conventional series-designed multilayer ceramic capacitor;

FIG. 7 is another schematic cross-sectional view of a conventional series-designed multilayer ceramic capacitor;

fig. 8 is still another schematic sectional view of a conventional series-designed multilayer ceramic capacitor.

Description of the main elements and symbols:

100. 200, a multilayer ceramic capacitor; 10. 20, a ceramic body; s1, an upper surface; s2, lower surface; s3, a first end surface; s4, a second end face; s5, a first side face; s6, a second side surface; 12A, 22A, a first internal electrode; 12B, 22B, a second inner electrode; 12C, 22C, a third inner electrode; 13. 23, a dielectric layer; 14A, 24A, a first terminal electrode; 14B, 24B, a second terminal electrode; a. c, d, the position of the end corner of the first internal electrode; b. e, f, the position of the end corner of the second inner electrode; x1, length of first inner electrode; y1, width of first inner electrode; x2, length of second inner electrode; y2, width of the second inner electrode.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be understood that the step numbers used herein are for convenience of description only and are not intended as limitations on the order in which the steps are performed.

It is to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

The terms "comprises" and "comprising" indicate the presence of the described features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The term "and/or" refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to fig. 1 to 4, a multilayer ceramic capacitor according to an embodiment of the present invention includes: a ceramic body 20, a first terminal electrode 24A and a second terminal electrode 24B.

The ceramic body 20 is formed by alternately laminating a plurality of dielectric layers 23 and a plurality of internal electrodes, the ceramic body 20 has an upper surface S1 formed by side surfaces of the plurality of laminated dielectric layers 23, a lower surface S2, a first end surface S3, a second end surface S4, a first side surface S5, and a second side surface S6, the upper surface S1 and the lower surface S2 are oppositely disposed, the first end surface S3 and the second end surface S4 are oppositely disposed, and the first side surface S5 and the second side surface S6 are oppositely disposed. The first terminal electrode 24A is located at the first end surface S3 and covers a portion of the surfaces of the upper surface S1, the lower surface S2, the first side surface S5, and the second side surface S6, and the second terminal electrode 24B is located at the second end surface S4 and covers a portion of the surfaces of the upper surface S1, the lower surface S2, the first side surface S5, and the second side surface S6. The internal electrodes include a first internal electrode 22A, a second internal electrode 22B and a third internal electrode 22C, the first internal electrode 22A is connected to the first terminal electrode 24A, the second internal electrode 22B is connected to the second terminal electrode 24B, the third internal electrode 22C is separated from the first internal electrode 22A and the second internal electrode 22B by at least one dielectric layer 23, the first internal electrode 22A is flush with at least a portion of the first end surface S3 and the second end surface S4 to form a first lead-out edge, the second internal electrode 22B is flush with at least a portion of the first end surface S3 and the second end surface S4 to form a second lead-out edge, and the length of the first lead-out edge is greater than that of the second lead-out edge.

Referring to fig. 4, the ceramic body 20 is formed of a rectangular parallelepiped having six faces, a length of 0.4mm to 5.6mm, a width of 0.2mm to 5.0mm, and a thickness of 0.2mm to 2.5mm, in which a plurality of dielectric layers 23 and internal electrodes are alternately laminated, and the upper face S1 and the lower face S2 are opposite to each other and perpendicular to a lamination direction of the dielectric layers 23 and the internal electrodes, that is, to a thickness direction of the multilayer ceramic capacitor 200. The first end surface S3 and the second end surface S4 are opposed to each other and perpendicular to the longitudinal direction of the multilayer ceramic capacitor 200, and the first side surface S5 and the second side surface S6 are opposed to each other and perpendicular to the width direction of the multilayer ceramic capacitor 200. The first terminal electrode 24A completely covers the first end surface S3 and extends over a portion of each of the upper surface S1, the lower surface S2, the first side surface S5, and the second side surface S6. The second terminal electrode 24B completely covers the second end face S4 and extends over a portion of each of the upper surface S1, the lower surface S2, the first side face S5, and the second side face S6. The first terminal electrode 24A and the second terminal electrode 24B are spaced apart from each other and insulated from each other.

The shape of the internal electrode is not particularly limited, but a rectangular thin layer is preferable in order to obtain a large volume utilization rate and to facilitate production. The thickness of the internal electrode is preferably 1 μm to 3 μm. The internal electrodes are laminated in a predetermined number inside the ceramic body 20 in parallel to the upper surface S1 and the lower surface S2. The internal electrodes include a first internal electrode 22A, a second internal electrode 22B, and a third internal electrode 22C. The first and second

internal electrodes

22A and 22B and the third internal electrodes 22C are shown in fig. 1 as 5 in number, respectively, and are shown as 4 in number by way of example only, and the number thereof is not limited in practice and may be adjusted according to the actual application, but the number of the first, second and third

internal electrodes

22A, 22B and 22C is preferably at least 1.

The first inner electrode 22A is flush with at least a portion of the first end surface S3 and the second end surface S4 to form a first lead-out edge, the second inner electrode 22B is flush with at least a portion of the first end surface S3 and the second end surface S4 to form a second lead-out edge, and the length of the first lead-out edge is greater than that of the second lead-out edge. A gap distance formed between the first internal electrode 22A and the first and second side surfaces S5 and S6 is smaller than a gap distance formed between the second internal electrode 22B and the first and second side surfaces S5 and S6. Specifically, the length of the first internal electrode 22A is x1, the width of the first internal electrode 22A is y1, the length of the second internal electrode 22B is x2, and the width of the second internal electrode 22B is y2, then x1 < x2, and y1 > y 2.

Referring to fig. 5 to 8, in the conventional multilayer ceramic capacitor 100 of the series design, the first internal electrode 12A and the second internal electrode 12B are stacked on the same dielectric layer 13 and symmetrically arranged side by side in the length direction of the multilayer ceramic capacitor 100, and the length and width of the first internal electrode 12A and the second internal electrode 12B are respectively equal to each other, so that the distance between the point a and the point B is small. In the present embodiment, although the first internal electrode 22A and the second internal electrode 22B are also laminated on the same dielectric layer 23, unlike the conventional series-designed multilayer ceramic capacitor 100, the first internal electrode 22A and the second internal electrode 22B are asymmetrically arranged side by side in the length direction of the multilayer ceramic capacitor 200, and x1 < x2, y1 > y2, so that the distance between the end of the first internal electrode 22A and the end of the second internal electrode 22B is large, and particularly, the distance between the point c and the point e and the distance between the point d and the point f are large, thereby significantly reducing the degree of electric field concentration, preventing breakdown and burning, and further improving the voltage resistance of the multilayer ceramic capacitor 200.

In one embodiment, a gap is formed between the first inner electrode 22A and the first and second side surfaces S5 and S6. Gaps are formed between the second inner electrodes 22B and the first and second side surfaces S5 and S6. A gap distance formed between the first internal electrode 22A and the first and second side surfaces S5 and S6 is smaller than a gap distance formed between the second internal electrode 22B and the first and second side surfaces S5 and S6.

In the present embodiment, the first internal electrode 22A, the second internal electrode 22B, and the third internal electrode 22C are all rectangular. The first internal electrode 22A and the second internal electrode 22B are laminated on the same dielectric layer 23 and are arranged side by side in the longitudinal direction of the multilayer ceramic capacitor 200. One end of the first internal electrode 22A extends to the first end surface S3 and is connected to the first terminal electrode 24A, and the other end of the first internal electrode 22A extends to a position spaced apart from the second terminal electrode 24B to ensure insulation from the second terminal electrode 24B. One end of the second internal electrode 22B extends to the second end face S4 and is connected to the second terminal electrode 24B, and the other end of the second internal electrode 22B extends to a position spaced apart from the first terminal electrode 24A so as to ensure insulation from the first terminal electrode 24A. An end of the first internal electrode 22A facing the second terminal electrode 24B is referred to as a distal end of the first internal electrode 22A, and an end of the second internal electrode 22B facing the first terminal electrode 24A is referred to as a distal end of the second internal electrode 22B, and the distal ends of the first internal electrode 22A and the second internal electrode 22B are spaced apart by a certain distance to ensure that the first internal electrode 22A and the second internal electrode 22B are insulated from each other.

The length of the first internal electrode 22A is x1, the width of the first internal electrode 22A is y1, the length of the second internal electrode 22B is x2, and the width of the second internal electrode 22B is y2, then x1 < x2, and y1 > y 2. The end corner positions of the first internal electrode 22A are point c and point d, and the end corner positions of the second internal electrode 22B are point e and point f. Since the gap distance formed between the first internal electrode 22A and the first and second side surfaces S5 and S6 is smaller than the gap distance formed between the second internal electrode 22B and the first and second side surfaces S5 and S6, the distance between the point c and the point e at the corner position increases, and the distance between the point d and the point f at the corner position increases. It is preferable that m represents the length of the ceramic body 20 and n represents the width of the

ceramic body

20, and 1/5m < x1 < 1/3m, 1/4m < x2 < 1/2m, 1/2n < y1 < 9/10n, and 1/3n < y2 < 3/4n are used, so that the distance between the end of the first internal electrode 22A and the end of the second internal electrode 22B can be made large, and a large capacitance can be easily obtained.

Referring to fig. 6, in an embodiment, an orthographic projection of the first inner electrode 22A on the third inner electrode 22C partially overlaps the third inner electrode 22C. The orthographic projection of the second internal electrode 22B on the third internal electrode 22C partially overlaps the third internal electrode 22C. The opposing area by the orthographic projection of the first internal electrode 22A on the third internal electrode 22C is equal to the opposing area by the orthographic projection of the second internal electrode 22B on the third internal electrode 22C. A first capacitance C1 is formed between the first and third internal electrodes 22A and 22C, a second capacitance C2 is formed between the second and third internal electrodes 22B and 22C, and the first capacitance C1 and the second capacitance C2 are connected in series.

The third internal electrode 22C is a floating electrode, and is spaced apart from both the first end surface S3 and the second end surface S4 by a certain distance, so the third internal electrode 22C is not connected to any one of the first terminal electrode 24A and the second terminal electrode 24B. The third internal electrode 22C is separated from the first internal electrode 22A by a dielectric layer 23, and the third internal electrode 22C is separated from the second internal electrode 22B by a dielectric layer 23. Orthographic projections of the first internal electrode 22A and the second internal electrode 22B on the third internal electrode 22C are respectively partially overlapped with the third internal electrode 22C, that is, the first internal electrode 22A and the second internal electrode 22B are respectively opposite to the third internal electrode 22C, so that a first capacitance C1 can be formed between the first internal electrode 22A and the third internal electrode 22C, a second capacitance C2 can be formed between the second internal electrode 22B and the third internal electrode 22C, and the first capacitance C1 and the second capacitance C2 are connected in series, which can play a role in distributing voltage and improve the voltage-resistant performance of the multilayer ceramic capacitor 200. The opposing area of the first internal electrode 22A and the third internal electrode 22C is equal to the opposing area of the second internal electrode 22B and the third internal electrode 22C, so that C1 ═ C2 may equally divide the voltage, and in other embodiments, the opposing areas may not be equal.

The capacitance of the multilayer ceramic capacitor 200 can be increased by forming an equivalent circuit as shown in fig. 6 by alternately arranging a plurality of first electrode units and a plurality of second electrode units in the stacking direction of the dielectric layers 23 and the internal electrodes, which is equivalent to connecting a plurality of series combinations of C1 and C2 in parallel, with the first internal electrodes 22A and the second internal electrodes 22B stacked on the same dielectric layer 23 as a first electrode unit and the third internal electrodes 22C as a second electrode unit, that is, the larger the number of first electrode units and second electrode units, the larger the capacitance of the multilayer ceramic capacitor 200.

Illustratively, by rounding each corner of the internal electrode, the charge concentration can be reduced, and the withstand voltage performance of the multilayer ceramic capacitor 200 can be further improved. By setting x1, x2, y1, and y2 to appropriate values, the opposing areas of the first internal electrode 22A and the third internal electrode 22C can be made equal to the opposing areas of the second internal electrode 22B and the third internal electrode 22C, so that the voltages are evenly distributed.

In one embodiment, the first internal electrode 22A and the second internal electrode 22B are laminated on the same dielectric layer 23.

In one embodiment, the first internal electrode 22A and the second internal electrode 22B may also be stacked on different dielectric layers 23, i.e., the first internal electrode 22A and the second internal electrode 22B are separated by one dielectric layer 23. In this case, the values of x1, x2, y1, and y2 may be adjusted to compensate for the capacitance difference caused by the difference in the thickness of the dielectric layers, maintaining C1 — C2. The first, second and third

internal electrodes

22A, 22B and 22C are spaced apart from the first and second side faces S5 and S6 to improve the moisture resistance of the multilayer ceramic capacitor 200.

In one embodiment, gaps are formed between the third inner electrodes 22C and the first and second end surfaces S3 and S4, respectively.

The third internal electrode 22C is a floating electrode, and is spaced apart from both the first end surface S3 and the second end surface S4 by a certain distance, so the third internal electrode 22C is not connected to any one of the first terminal electrode 24A and the second terminal electrode 24B. The third internal electrode 22C is separated from the first internal electrode 22A by a dielectric layer 23, and the third internal electrode 22C is separated from the second internal electrode 22B by a dielectric layer 23.

The first inner electrode 22A is flush with at least one part of the first end surface S3 and the second end surface S4 to form a first lead-out edge, the second inner electrode 22B is flush with at least one part of the first end surface S3 and the second end surface S4 to form a second lead-out edge, and the length of the first lead-out edge is greater than that of the second lead-out edge. The corner distance between the first leading-out edge and the second leading-out edge in the first internal electrode 22A and the second internal electrode 22B is increased, meanwhile, the length of the first internal electrode 22A is smaller than that of the second internal electrode 22B, the width of the first internal electrode 22A is larger than that of the second internal electrode 22B, and then the distance of the corner position is increased, so that the concentration degree of an electric field is reduced, and breakdown and burnout are prevented.

Further, the opposing area generated by the orthographic projection of the first inner electrode 22A on the third inner electrode 22C is equal to the opposing area generated by the orthographic projection of the second inner electrode 22B on the third inner electrode 22C, so that the first capacitor C1 is equal to the second capacitor C2, and the function of distributing the voltage is achieved.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.

Claims

1. A multilayer ceramic capacitor, comprising: a ceramic body, a first terminal electrode and a second terminal electrode;

2. The multilayer ceramic capacitor according to claim 1, wherein a gap is formed between the first internal electrode and the first and second side faces.

3. The multilayer ceramic capacitor according to claim 1, wherein a gap is formed between the second internal electrode and the first and second side faces.

4. The multilayer ceramic capacitor according to claims 2 and 3, wherein a gap distance formed between the first internal electrode and the first and second side faces is smaller than a gap distance formed between the second internal electrode and the first and second side faces.

5. The multilayer ceramic capacitor according to claim 1, wherein an orthographic projection of the first internal electrode on the third internal electrode partially overlaps the third internal electrode.

6. The multilayer ceramic capacitor according to claim 1, wherein an orthographic projection of the second internal electrode on the third internal electrode partially overlaps the third internal electrode.

7. The multilayer ceramic capacitor according to claims 5 and 6, wherein an opposing area resulting from an orthographic projection of the first internal electrode on the third internal electrode is equal to an opposing area resulting from an orthographic projection of the second internal electrode on the third internal electrode.

8. The multilayer ceramic capacitor according to claim 7, wherein a first capacitance is formed between the first internal electrode and the third internal electrode, a second capacitance is formed between the second internal electrode and the third internal electrode, and the first capacitance and the second capacitance are connected in series.

9. The multilayer ceramic capacitor according to claim 1, wherein the first internal electrode and the second internal electrode are laminated on the same dielectric layer.

10. The multilayer ceramic capacitor according to claim 1, wherein gaps are formed between the third inner electrodes and the first end face and the second end face, respectively.