CN114005407A - Display panel and display device - Google Patents
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- CN114005407A CN114005407A CN202111285850.7A CN202111285850A CN114005407A CN 114005407 A CN114005407 A CN 114005407A CN 202111285850 A CN202111285850 A CN 202111285850A CN 114005407 A CN114005407 A CN 114005407A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
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- 230000001808 coupling effect Effects 0.000 description 8
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The embodiment of the invention provides a display panel and a display device. The display panel comprises a substrate and a pixel circuit positioned on one side of the substrate; the pixel circuit comprises a driving transistor, wherein the control end of the driving transistor is electrically connected with a first node, and the driving transistor is used for generating driving current under the potential control of the first node; the pixel circuit includes a potential adjustment module electrically connected to the first node, the potential adjustment module being configured to compensate for a potential of the first node after writing the data signal to the first node. The invention can reduce the power consumption of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
Organic Light-Emitting diodes (OLEDs) have the advantages of fast response, high brightness, high contrast, low power consumption, and easy implementation of flexibility, and are considered as the mainstream display technology of the next generation. With the continuous development of display technologies, the refresh frequency of the display panel is higher and higher, the driving power consumption of the display screen is increased, and the time for scanning one frame of image is shorter as the refresh rate is higher, so that the threshold compensation time of the pixel compensation circuit for the driving transistor is insufficient, and the driving power consumption is further increased. Excessive power consumption of the display panel driver can cause heat generation of the driver and further affect performance.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, and aims to solve the problem that the power consumption of the display panel is higher in the related art.
In a first aspect, an embodiment of the present invention provides a display panel, including:
the pixel circuit comprises a substrate and a pixel circuit positioned on one side of the substrate;
the pixel circuit comprises a driving transistor, wherein the control end of the driving transistor is electrically connected with a first node, and the driving transistor is used for generating driving current under the potential control of the first node;
the pixel circuit includes a potential adjustment module electrically connected to the first node, the potential adjustment module being configured to compensate for a potential of the first node after writing the data signal to the first node.
In a second aspect, an embodiment of the present invention further provides a display device, including the display panel provided in any embodiment of the present invention.
The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: the pixel circuit is additionally provided with a potential adjusting module which is connected with the control end of the driving transistor, and after the data signal is written into the control end of the driving transistor, the influence of insufficient threshold compensation time on the control end voltage of the driving transistor is compensated by the potential adjusting module, so that the influence on dark state voltage under high refresh rate is improved, and the power consumption of the display panel is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings needed to be used in the description of the embodiments or the related art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic diagram of a pixel circuit according to an embodiment of the invention;
FIG. 2 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of the pixel circuit of the embodiment of FIG. 3;
FIG. 5 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;
fig. 8 is a schematic view of a display device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. It should be noted that the embodiments provided in the embodiments of the present invention can be combined with each other without contradiction.
In the related art, the duty cycle of the pixel circuit includes at least a data writing phase and a light emitting phase. In a data writing stage, writing a data voltage signal into the control end of the driving transistor and compensating the threshold voltage of the driving transistor; in the light emitting stage, the driving transistor generates a driving current under control of a control terminal voltage thereof and supplies the driving current to the light emitting device to control the light emitting device to emit light. The higher the display refresh rate, the shorter the time to scan one frame of image, causing the pixel compensation circuit to have insufficient threshold compensation time for the drive transistor, thereby affecting the voltage at the control terminal of the drive transistor.
When the driving transistor is a p-type transistor, the higher the display refresh rate is, the lower the control end potential of the driving transistor due to insufficient threshold compensation time, the higher the driving current is, the higher the light emitting brightness of the OLED device is, the higher the dark state voltage of the light emitting device is, and thus the driving power consumption is increased. When the driving transistor is an n-type transistor, the data voltage is a negative voltage, and the threshold compensation time is insufficient, so that the potential of the control terminal of the driving transistor is higher, the driving current is larger, the luminance of the OLED device is higher, the dark-state voltage of the OLED device is more negative, that is, the absolute value of the difference between the dark-state voltage and the 0V voltage is increased, and the driving power consumption is also increased.
The embodiment of the invention provides a display panel, wherein a potential adjusting module is added in a pixel circuit, the potential adjusting module is connected with a control end of a driving transistor, and after a data signal is written into the control end of the driving transistor, the potential adjusting module is used for compensating the influence of insufficient threshold compensation time on the voltage at the control end of the driving transistor, so that the influence on dark state voltage under high refresh rate is improved, and the power consumption of the display panel is reduced.
The display panel provided by the embodiment of the invention comprises a substrate and a pixel circuit positioned on one side of the substrate, wherein the pixel circuit further comprises a light-emitting device on one side far away from the substrate, the pixel circuit is used for driving the light-emitting device to emit light, and the light-emitting device can be an organic light-emitting diode or an inorganic light-emitting diode.
Fig. 1 is a schematic diagram of a pixel circuit according to an embodiment of the invention, as shown in fig. 1, the pixel circuit includes a driving transistor Tm, a control terminal of the driving transistor Tm is electrically connected to a first node N1, a first pole of the driving transistor Tm is electrically connected to a second node N2, and a second pole of the driving transistor Tm is electrically connected to a third node N3. The driving transistor Tm is used to generate a driving current under the potential control of the first node N1. The pixel circuit may further include a data write transistor T1, a threshold compensation transistor T2, the data write transistor T1 may be connected to the third node N2, and the threshold compensation transistor T2 may be connected in series between the first pole of the driving transistor Tm and the control pole of the driving transistor Tm; the threshold compensation transistor T2 may be used to compensate for the threshold voltage of the driving transistor Tm. The first and second electrodes of the driving transistor Tm are respectively a source electrode and a drain electrode. The control terminals of the Data write transistor T1 and the threshold compensation transistor T2 may be connected to the first scan signal terminal S1, the Data write transistor T1 is connected to the Data signal terminal Data, and the Data write transistor T1 is configured to receive and write a Data signal to the first node N1.
The pixel circuit may further include a light emission control module 10, and the light emission control module 10 may include a first control transistor T3 and a second control transistor T4, and the driving transistor Tm is connected in series between the first control transistor T3 and the second control transistor T4. The driving transistor Tm is electrically connected to the light emitting device 20 through the second control transistor T4. The first and second control transistors T3 and T4 supply a driving current to the light emitting device 20 when turned on simultaneously to control the light emitting device 20 to emit light. Wherein the control terminals of the first control transistor T3 and the second control transistor T4 are both connected to the light emission control signal terminal E, and the first control transistor T3 is connected to the power supply voltage signal terminal P. The pixel circuit further includes a storage capacitor Cst having one electrode plate connected to the power supply voltage signal terminal P and the other electrode plate connected to the first node N1.
The pixel circuit includes a potential adjusting block 30, the potential adjusting block 30 is electrically connected to the first node N1, and the potential adjusting block 30 is configured to compensate for a potential of the first node N1 after writing the data signal to the first node N1.
The working cycle of the pixel circuit in the embodiment of the invention at least comprises a data writing phase and a light emitting phase. In the data writing phase: the data writing transistor T1 and the threshold compensating transistor T2 are both turned on, write a data signal to the first node N1, and perform self-test and compensation for the threshold voltage of the driving transistor Tm. In the light emitting stage: the first and second control transistors T3 and T4 are turned on, and the driving transistor Tm generates a driving current under the voltage control of the first node N1 and supplies the driving current to the light emitting device 20 at this stage.
The higher the display refresh rate, the shorter the time to scan one frame of image, and the shorter the time allotted to the data writing phase during the operation of the pixel circuit. If the data writing period is too short, the threshold compensation time for the driving transistor Tm is insufficient, and the magnitude of the data signal written to the first node N1 is affected.
Taking the driving transistor Tm in the pixel circuit illustrated in fig. 1 as a p-type transistor as an example, the time of the data writing phase is too short, which results in a low potential of the first node N1 after the data writing phase, and in the subsequent light emitting phase, the low potential of the first node N1 results in a large driving current, which results in a high light emitting luminance of the light emitting device, so that the dark state voltage of the light emitting device increases, thereby increasing the driving power consumption. In the embodiment of the present invention, the potential adjustment module 30 can compensate the potential of the first node N1 after writing the data signal into the first node N1, and when the driving transistor Tm is a p-type transistor, the potential adjustment module 30 can be configured to pull up the potential of the first node N1 after writing the data signal into the first node N1, so that the driving current generated by the driving transistor Tm in the light emitting phase becomes smaller, and the brightness of the corresponding light emitting device is reduced, thereby meeting the dark state requirement under a smaller dark state voltage, and reducing the dark state voltage. In the embodiment of the present invention, the potential adjusting module 30 can compensate the influence of the insufficient threshold compensation time on the voltage at the control terminal of the driving transistor, so as to improve the influence on the dark state voltage at a high refresh rate and reduce the power consumption of the display panel.
In other embodiments, if the driving transistor Tm in the pixel circuit is an N-type transistor, the data writing period is too short, which results in a high potential of the first node N1 after the data writing period, and in the subsequent light emitting period, the high potential of the first node N1 results in a high driving current, which results in a high light emitting luminance of the light emitting device, so that the absolute value of the difference between the dark state voltage of the light emitting device and the 0V voltage is increased, which also increases the driving power consumption. In the embodiment of the present invention, the potential adjustment module 30 can compensate the potential of the first node N1 after writing the data signal into the first node N1, and when the driving transistor Tm is an N-type transistor, the potential adjustment module 30 can be configured to pull down the potential of the first node N1 after writing the data signal into the first node N1, so that the driving current generated by the driving transistor Tm in the light emitting phase becomes smaller, and the luminance of the corresponding light emitting device is reduced, thereby reducing the absolute value of the difference between the dark state voltage and the 0V voltage. In the embodiment of the present invention, the potential adjusting module 30 can compensate the influence of the insufficient threshold compensation time on the voltage at the control terminal of the driving transistor, so as to improve the influence on the dark state voltage at a high refresh rate and reduce the power consumption of the display panel.
In some embodiments, fig. 2 is a schematic diagram of another pixel circuit provided in an embodiment of the invention. As shown in fig. 2, the voltage adjusting module 30 includes a voltage adjusting capacitor Cv, a first plate of the voltage adjusting capacitor Cv is electrically connected to the first node N1, and a second plate of the voltage adjusting capacitor Cv is electrically connected to the first voltage signal terminal V1. Wherein, in the working phase of the pixel circuit: after writing the data signal to the first node N1, the voltage signal provided by the first voltage signal terminal V1 includes a process of transitioning between a high level and a low level. Wherein, in some embodiments, after writing the data signal to the first node N1, the voltage signal provided by the first voltage signal terminal V1 includes a transition process from a high level to a low level; in other embodiments, the voltage signal provided by the first voltage signal terminal V1 includes a transition from a low level to a high level after writing the data signal to the first node N1.
In some embodiments, the driving transistor Tm is a p-type transistor. In the working phase of the pixel circuit: after writing the data signal to the first node N1, the voltage signal provided by the first voltage signal terminal V1 transitions from a low level to a high level. Due to the coupling effect of the potential adjusting capacitor Cv, the potential of the first node N1 can be pulled high, so that the potential of the first node N1 is compensated after the data signal is written into the first node N1, the problem that the potential of the first node N1 is low due to insufficient threshold compensation time is solved, the dark state voltage under a high refresh rate can be reduced, and the power consumption of the display panel is reduced.
In other embodiments, the driving transistor Tm is an n-type transistor. In the working phase of the pixel circuit: after writing the data signal to the first node N1, the voltage signal provided by the first voltage signal terminal V1 transitions from a high level to a low level. Due to the coupling effect of the potential adjusting capacitor Cv, the potential of the first node N1 can be pulled down, so that the potential of the first node N1 is compensated after the data signal is written into the first node N1, the problem that the potential of the first node N1 is higher due to insufficient threshold compensation time is solved, the absolute value of the difference between the dark state voltage and the 0V voltage under the high refresh rate can be reduced, and the power consumption of the display panel is reduced.
In some embodiments, a first voltage signal line is provided in the display panel, and one plate of the potential adjustment capacitor Cv is connected to the first voltage signal line as a first voltage signal terminal V1. The first voltage signal line is not connected with each transistor in the pixel circuit, and the first voltage signal line is wired in the display panel and then connected to an output port of the display driving chip. In this embodiment mode, a first voltage signal line is provided in the display panel so as to be connected to one plate of the potential adjustment capacitor Cv. The potential of the first node N1 is compensated by controlling the potential adjusting module 30 through the display driving chip to match with the duty cycle of the pixel circuit, and the setting of the potential adjusting module 30 does not affect the connection relationship of the transistors in the pixel circuit, the types of the transistors, and the scanning signals for driving the pixel circuit to operate.
In some embodiments, a scanning signal line provided in the display panel, which supplies a scanning signal for driving the pixel circuit to operate, one end of which is connected to a shift driving circuit in the display panel, is multiplexed into the first voltage signal terminal V1. In this embodiment, one plate of the potential adjusting capacitor Cv is electrically connected to the control terminal of the first transistor in the pixel circuit, that is, the control terminal of the first transistor and one plate of the potential adjusting capacitor Cv are both connected to the first voltage signal terminal V1. In the duty cycle of the pixel circuit: after writing the data signal to the first node N1, the voltage signal provided by the first voltage signal terminal V1 includes a process of transitioning between a non-enable level and an enable level. The enabling level is a signal for controlling the first transistor to be started, and the control end of the first transistor receives the enabling level and then the first transistor is started; the control end of the first transistor receives the non-enabling level, and then the first transistor is closed. In this embodiment, the potential adjustment module 30 is controlled by the scanning signal for driving the pixel circuit, so that the number of wirings in the display panel can be reduced, the wiring space in the display panel can be saved, and the number of output ports of the display driver chip can be reduced.
In one embodiment, the light emitting control terminal is multiplexed as the first voltage signal terminal V1. Fig. 3 is a schematic diagram of another pixel circuit according to an embodiment of the invention, and as shown in fig. 3, the first transistor M1 includes a first control transistor T3 and a second control transistor T4, and a control terminal of the first control transistor T3 and a control terminal of the second control transistor T4 are both electrically connected to the first voltage signal terminal V1. The light emitting phase is located after the data writing phase in the duty cycle of the pixel circuit. When the data signal is written to the first node N1 in the data writing phase, the first voltage signal terminal V1 provides a disable level to control both the first control transistor T3 and the second control transistor T4 to be turned off. After writing the data signal to the first node N1, when the light emitting phase is entered, the first voltage signal terminal V1 provides an enable level to control both the first control transistor T3 and the second control transistor T4 to be turned on. The signal provided from the first voltage signal terminal V1 includes a process of transitioning from the disable level to the disable level after writing the data signal to the first node N1. When the signal provided by the first voltage signal terminal V1 jumps, the coupling effect of the potential adjusting capacitor Cv can affect the potential of the first node N1, so as to compensate the potential of the first node N1, thereby improving the influence of insufficient threshold compensation time on the dark state voltage under the high refresh rate, and reducing the power consumption of the display panel.
As shown in fig. 3, the pixel circuit further includes a node reset transistor T5, a control terminal of the node reset transistor T5 is connected to the second scan signal terminal S2, a first pole of the node reset transistor T5 is connected to the reset signal terminal Ref, and a second pole of the node reset transistor T5 is electrically connected to the first node N1. The node reset transistor T5 is used to reset the first node N1 during a reset phase.
In one embodiment, as shown in fig. 3, the driving transistor Tm is a p-type transistor, and the first control transistor T3 and the second control transistor T4 are both n-type transistors, i.e., the first transistor M1 electrically connected to the first voltage signal terminal V1 is an n-type transistor.
Fig. 4 is a timing diagram of the pixel circuit in the embodiment of fig. 3. As shown in fig. 4, the duty cycle of the pixel circuit includes a reset phase t1, a data write phase t2, and a light emission phase t 3.
At the reset phase t 1: the second scan signal terminal S2 provides an enable level to control the node reset crystal T5 to be turned on, and writes a reset signal provided from the reset signal terminal Ref to the first node N1 to reset the first node N1.
At the data writing stage t 2: the first scan signal terminal S1 provides an enable level to control the data writing transistor T1 and the threshold compensating transistor T2 to be turned on, write a data signal to the first node N1, and perform self-test and compensation for the threshold voltage of the driving transistor Tm.
During the reset period T1 and the data write period T2, the first voltage signal terminal V1 provides a disable level to ensure that the first control transistor T3 and the second control transistor T4 are both turned off.
In the light emission phase t 3: the signal provided by the first voltage signal terminal V1 jumps from the disable level to the enable level to control both the first control transistor T3 and the second control transistor T4 to be turned on. Fig. 4 illustrates that the signal provided by the first voltage signal terminal V1 transitions from a low level to a high level signal. The driving transistor Tm generates a driving current under the control of the potential of the first node N1 at this stage.
After the data signal is written to the first node N1 at a high refresh rate, the potential of the first node N1 is low due to the short data writing time. When the lighting period T3 is entered after the data writing period T2, the signal provided by the first voltage signal terminal V1 jumps from a low level (corresponding to the disable level of the first transistor M1 in this scheme) to a high level (corresponding to the enable level of the first transistor M1 in this scheme) to control the first control transistor T3 and the second control transistor T4 to be turned on. Meanwhile, when the signal provided by the first voltage signal terminal V1 jumps, the coupling effect of the potential adjustment capacitor Cv pulls the potential of the first node N1 high (as shown in fig. 4) to compensate the influence of insufficient threshold compensation time on the potential of the first node N1, so that the influence on the dark state voltage under a high refresh rate can be improved, and the power consumption of the display panel is reduced.
In some embodiments, the driving transistor Tm is an n-type transistor, and the first and second control transistors T3 and T4 are both p-type transistors, i.e., the first transistor M1 electrically connected to the first voltage signal terminal V1 is a p-type transistor. After the data signal is written into the first node N1 at a high refresh rate, since the data writing time is short, which causes the potential of the first node N1 to be high, when the lighting phase is entered after the data writing phase, the signal provided by the first voltage signal terminal V1 jumps from a high level (corresponding to the disable level of the first transistor M1 in this scheme) to a low level (corresponding to the enable level of the first transistor M1 in this scheme) to control the first control transistor T3 and the second control transistor T4 to be turned on. Meanwhile, when the signal provided by the first voltage signal terminal V1 jumps, the coupling effect of the potential adjusting capacitor Cv pulls down the potential of the first node N1 to compensate the influence of insufficient threshold compensation time on the potential of the first node N1, so that the influence on the dark state voltage under a high refresh rate can be improved, and the power consumption of the display panel is reduced.
Fig. 3 shows that the control terminal of the first control transistor T3 and the control terminal of the second control transistor T4 are both electrically connected to the first voltage signal terminal V1, and the first control transistor T3 and the second control transistor T4 can be controlled by using the same control line, which is beneficial to reducing the wiring in the display panel, and can also reduce the number of shift driving circuits in the display panel, and save the space of the non-display area of the display panel.
In some embodiments, a control terminal of only one of the first control transistor T3 and the second control transistor T4 is connected to the first voltage signal terminal. That is, the first transistor M1 includes one of the first control transistor T3 and the second control transistor T4.
In an embodiment, fig. 5 is a schematic diagram of another pixel circuit provided by the embodiment of the invention, as shown in fig. 5, a control terminal of the first control transistor T3 and a plate of the potential adjusting capacitor Cv are both connected to the first voltage signal terminal V1, and a control terminal of the second control transistor T4 is connected to the light emitting control terminal E. The driving transistor Tm is a p-type transistor, the first control transistor T3 is an n-type transistor, and the second control transistor T4 is a p-type transistor. In this embodiment, after writing the data signal to the first node N1, the voltage level of the first node N1 is pulled high by the transition process from the disable level to the enable level of the signal of the first voltage signal terminal V1 to compensate for the effect of the insufficient threshold compensation time on the voltage level of the first node N1. In this embodiment, the enable level of the first control transistor T3 is a high level signal, and the enable level of the second control transistor T4 is a low level signal. When the light-emitting period is entered after the data writing period, the signal provided by the first voltage signal terminal V1 transitions from low level to high level, and the signal provided by the light-emitting control terminal E transitions from high level to low level.
In another embodiment, the control terminal of the second control transistor T4 and one plate of the potential adjusting capacitor Cv are both connected to the first voltage signal terminal V1, and the control terminal of the first control transistor T3 is connected to the light emission control terminal E. Which are not illustrated in the drawings.
In some embodiments, a display panel provided by an embodiment of the present invention includes a metal oxide semiconductor layer and a silicon semiconductor layer on one side of a substrate; the active layer of the first transistor M1 is located on the metal oxide semiconductor layer, and the active layer of the driving transistor Tm is located on the silicon semiconductor layer, for example, the silicon semiconductor layer is a low temperature polysilicon semiconductor layer. The first transistor M1 is an n-type transistor, the driving transistor Tm is a p-type transistor, and the driving transistor Tm can have high electron mobility and small device size, so that the driving performance of the pixel circuit can be improved, and the space occupied by the whole pixel circuit can be reduced to a certain extent.
In another embodiment, the active layers of the threshold compensation transistor T2 and the node reset transistor T5 are located on the metal oxide semiconductor layer. Fig. 6 is a schematic diagram of another pixel circuit according to an embodiment of the invention, and as shown in fig. 6, the threshold compensation transistor T2 and the node reset transistor T5 are both n-type transistors. After the data signal is written into the first node N1, the threshold compensation transistor T2 and the node reset transistor T5 are both in an off state, and the active layers of the threshold compensation transistor T2 and the node reset transistor T5 are disposed on the metal oxide semiconductor layer, so that the leakage current of the threshold compensation transistor T2 and the node reset transistor T5 to the first node N1 in the off state can be reduced, the potential of the first node N1 can be stabilized, the operation stability of the driving transistor Tm can be improved, the potential of the first node N1 can be maintained for a long time when the display is performed at a low refresh rate, the flicker phenomenon at a low refresh rate can be improved, and the display effect can be improved.
In addition, the active layer of the driving transistor Tm is located on the silicon semiconductor layer, and the active layers of the first and second control transistors T3 and T4 are located on the metal oxide semiconductor layer. A control terminal of the first control transistor T3 and a control terminal of the second control transistor T4 are both connected to the first voltage signal terminal V1. In the operation of the pixel circuit, after the data signal is written into the first node N1, the signal provided by the first voltage signal terminal V1 includes a transition from the disable level to the disable level. When the signal provided by the first voltage signal end V1 jumps, the coupling effect of the potential adjusting capacitor Cv compensates the potential of the first node N1, the influence of insufficient threshold compensation time on dark state voltage under high refresh rate is improved, and therefore the power consumption of the display panel is reduced.
The first control transistor T3, the second control transistor T4, the threshold compensation transistor T2 and the node reset transistor T5 are arranged in the same transistor type, and the active layer of each transistor is located in the metal oxide semiconductor layer. By disposing the active layers of the threshold compensation transistor T2 and the node reset transistor T5 on the metal oxide semiconductor layer, the leakage current of the threshold compensation transistor T2 and the node reset transistor T5 in the off state can be reduced, so that the potential of the first node N1 can be stabilized, and the operation stability of the driving transistor Tm can be improved. The active layer of the driving transistor Tm is disposed on the silicon semiconductor layer, and the driving transistor Tm is different from the transistor types of the first control transistor T3 and the second control transistor T4, and the transition of the scan signal at the control end of the first control transistor T3 and the control end of the second control transistor T4 can be utilized to control the operation of the potential adjusting module 30 to compensate the influence of the insufficient threshold compensation time on the potential of the first node N1, so as to improve the influence of the insufficient threshold compensation time on the dark state voltage under the high refresh rate and reduce the power consumption of the display panel. In addition, the first control transistor T3 and the second control transistor T4 have the same transistor type, and the first control transistor T3 and the second control transistor T4 can be controlled by the same control line, which is advantageous in reducing wiring in the display panel.
In another embodiment, the active layer of one of the threshold compensation transistor T2 and the node reset transistor T5 is located on the metal oxide semiconductor layer, i.e., one of the threshold compensation transistor T2 and the node reset transistor T5 is an n-type transistor. In addition, the driving transistor Tm is a p-type transistor, at least one of the first control transistor T3 and the second control transistor T4 is an n-type transistor, and one plate of the potential adjusting capacitor Cv is connected to the first voltage signal terminal V1.
In another embodiment, fig. 7 is a schematic diagram of another pixel circuit provided by the embodiment of the invention, as shown in fig. 7, the data writing transistor T1 and the driving transistor Tm are of the same type, and the first transistor M1 includes a data writing transistor T1, that is, the control terminal of the data writing transistor T1 and one plate of the potential adjusting capacitor Cv are both connected to the first voltage signal terminal V1. This embodiment compensates the potential of the first node N1 by the coupling effect of the potential adjusting capacitor Cv when the first voltage signal terminal V1 transits from the enable level to the disable level after writing the data signal to the first node N1.
The case where the data writing transistor T1 and the driving transistor Tm illustrated in fig. 7 are both p-type transistors will be described. In the data writing phase, the first voltage signal terminal V1 provides a low level (an enable level corresponding to the data writing transistor T1 in this embodiment) to control the data writing transistor T1 and the threshold compensation transistor T2 to be turned on, so as to write the data signal into the first node N1. After writing the data signal to the first node N1, the signal of the first voltage signal terminal V1 transits from the low level to the high level to control the data writing transistor T1 and the threshold compensating transistor T2 to be turned off. When the signal of the first voltage signal terminal V1 jumps from a low level to a high level, the potential of the first node N1 can be pulled high due to the coupling effect of the potential adjusting capacitor Cv, so as to improve the problem that the potential of the first node N1 is low due to insufficient threshold compensation time, thereby reducing the dark state voltage at a high refresh rate and reducing the power consumption of the display panel.
In some embodiments, the pixel circuit further includes an electrode reset transistor for resetting an electrode of the light emitting device 20.
Fig. 8 is a schematic view of a display device according to an embodiment of the present invention, and as shown in fig. 8, the display device includes a display panel 100 according to any embodiment of the present invention. The structure of the display panel has been described in the above embodiments, and is not described herein again. The display device in the embodiment of the invention can be any equipment with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a television, an intelligent watch and the like.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A display panel, comprising:
the pixel circuit comprises a substrate and a pixel circuit positioned on one side of the substrate;
the pixel circuit comprises a driving transistor, wherein the control end of the driving transistor is electrically connected with a first node, and the driving transistor is used for generating driving current under the control of the potential of the first node;
the pixel circuit includes a potential adjustment module electrically connected to the first node, the potential adjustment module being configured to compensate for a potential of the first node after writing a data signal to the first node.
2. The display panel according to claim 1, characterized in that:
the potential adjusting module comprises a potential adjusting capacitor, a first electrode plate of the potential adjusting capacitor is electrically connected with the first node, and a second electrode plate of the potential adjusting capacitor is electrically connected with the first voltage signal end.
3. The display panel according to claim 2,
the pixel circuit comprises a first transistor, and the control end of the first transistor is electrically connected with the first voltage signal end;
during an operating period of the pixel circuit: the voltage signal provided by the first voltage signal terminal includes a process of jumping between a non-enable level and an enable level after writing the data signal to the first node.
4. The display panel according to claim 3,
the pixel circuit comprises a light-emitting control module, wherein the light-emitting control module comprises a first control transistor and a second control transistor, and the driving transistor is connected between the first control transistor and the second control transistor in series;
the duty cycle of the pixel circuit comprises a light emission phase during which: the first control transistor and the second control transistor are simultaneously turned on to supply the driving current generated by the driving transistor to the light emitting device;
wherein the first transistor includes at least one of the first control transistor and the second control transistor.
5. The display panel according to claim 4,
one of the driving transistor and the first transistor is a p-type transistor, and the other is an n-type transistor.
6. The display panel according to claim 5, comprising:
a metal oxide semiconductor layer on one side of the substrate;
the active layer of the first transistor is located on the metal oxide semiconductor layer.
7. The display panel according to claim 6,
the pixel circuit further includes a threshold compensation transistor and a node reset transistor;
the threshold compensation transistor is connected in series between the first pole of the driving transistor and the control pole of the driving transistor; the threshold compensation transistor is used for compensating the threshold voltage of the driving transistor;
the node reset transistor is electrically connected with the first node and is used for resetting the first node;
an active layer of at least one of the threshold compensation transistor and the node reset transistor is located on the metal oxide semiconductor layer.
8. The display panel according to claim 3,
the pixel circuit includes a data writing transistor for writing a data signal to the first node; the data writing transistor and the driving transistor are of the same type;
the first transistor includes the data write transistor.
9. The display panel according to claim 1,
the display panel includes a silicon semiconductor layer over the substrate;
the active layer of the driving transistor is located on the silicon semiconductor layer.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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| CN202111285850.7A CN114005407A (en) | 2021-11-02 | 2021-11-02 | Display panel and display device |
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| CN202111285850.7A CN114005407A (en) | 2021-11-02 | 2021-11-02 | Display panel and display device |
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