CN114005400B

CN114005400B - Pixel circuit and display panel

Info

Publication number: CN114005400B
Application number: CN202111272606.7A
Authority: CN
Inventors: 朱正勇; 贾溪洋; 赵欣; 孙光远; 段培; 何国冰; 马志丽
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2024-02-27
Anticipated expiration: 2041-10-29
Also published as: CN114005400A

Abstract

The embodiment of the invention discloses a pixel circuit and a display panel, wherein the pixel circuit comprises a driving transistor, a data writing module, a first initializing module and a first leakage suppressing module, wherein the first leakage suppressing module is used for coupling the grid voltage variation of the driving transistor to a first middle node connected with the first leakage suppressing module in a positive correlation manner, so that after the data writing stage, the potential of the first middle node of the first leakage suppressing module is the sum of the first initializing voltage and the coupling quantity (namely, the voltage positively correlated with the grid voltage variation of the driving transistor), and further, compared with the prior art, the voltage difference between the grid of the driving transistor and the first middle node in the first initializing module is reduced, the leakage of the first initializing module is reduced, the grid voltage of the driving transistor can be well maintained during the light emitting stage, the stability of the driving current generated by the driving transistor is further ensured, and the screen flicker phenomenon is improved.

Description

Pixel circuit and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit and a display panel.

Background

With the development of display technology, the requirements of people on display quality are also increasing.

The display panel includes a pixel circuit, and the existing pixel circuit includes a driving transistor and an initializing transistor for initializing the driving transistor, and in the display panel prepared by the low-temperature polysilicon process, the electric leakage of the initializing transistor is large, and in the prior art, the initializing transistor is generally set to be a double-gate transistor.

However, when the light emitting device emits light, the potential difference between the intermediate node of the initializing transistor and the gate of the driving transistor is larger, so that the electric leakage of the initializing transistor is still larger, and the gate potential of the driving transistor cannot be well maintained, thereby causing the flicker of the screen.

Disclosure of Invention

The invention provides a pixel circuit and a display panel, which are used for reducing electric leakage of a first initialization module in the pixel circuit of the low-temperature polysilicon process display panel and reducing screen flicker.

In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the device comprises a driving transistor, a data writing module, a storage module, a first initialization module and a first leakage suppression module;

the first initialization module is used for writing a first initialization voltage to the grid electrode of the driving transistor in an initialization stage; the first initialization module comprises at least two first sub-transistors connected in series, wherein adjacent first sub-transistors are electrically connected through a first intermediate node between the first sub-transistors, the first leakage suppression module is electrically connected with at least one first intermediate node, and the first leakage suppression module is used for coupling the grid potential variation of the driving transistor to the first intermediate node connected with the first leakage suppression module in a positive correlation manner;

The data writing module is used for writing the voltage of the data to the grid electrode of the driving transistor in the data writing stage; the memory module is used for storing the gate voltage of the driving transistor.

Optionally, the first leakage suppression module includes a first capacitor, a first plate of the first capacitor is electrically connected to the gate of the driving transistor, and a second plate of the first capacitor is electrically connected to at least one first intermediate node.

Optionally, in the first initialization module, a channel width-to-length ratio of the first sub-transistor between the first intermediate node connected to the first leakage suppression module and the first end of the first initialization module is smaller than a channel width-to-length ratio of the first sub-transistor between the first intermediate node connected to the first leakage suppression module and the second end of the first initialization module; the first end of the first initialization module is connected with a first initialization voltage, and the second end of the first initialization module is connected with the grid electrode of the driving transistor;

optionally, a channel width of the first sub-transistor between the first intermediate node connected to the first leakage suppression module and the first end of the first initialization module is less than or equal to 1.8 micrometers, and a channel length is greater than or equal to 4 micrometers.

Optionally, the pixel circuit further includes a compensation module for writing information including a threshold voltage of the driving transistor to a gate of the driving transistor in a data writing phase;

The compensation module comprises at least two second sub-transistors connected in series, and adjacent second sub-transistors are electrically connected through a second intermediate node between the two second sub-transistors;

optionally, a control end of the first initialization module is connected to a first scanning signal, a first end of the first initialization module is connected to a first initialization voltage, and a second end of the first initialization module is electrically connected with a gate of the driving transistor;

optionally, the control end of the data writing module is connected with a second scanning signal, the first end of the data writing module is connected with a data voltage, and the second end of the data writing module is electrically connected with the first electrode of the driving transistor; the control end of the compensation module is connected with a second scanning signal, the first end of the compensation module is electrically connected with the second electrode of the driving transistor, and the second end of the compensation module is electrically connected with the grid electrode of the driving transistor;

optionally, the pixel circuit further includes a first light emitting control module and a second light emitting control module, the first light emitting control module is used for controlling a conducting state between the first power voltage input end and the first pole of the driving transistor according to a first light emitting control signal connected to the control end of the pixel circuit, the second light emitting control module is used for controlling a conducting state between the second pole of the driving transistor and the first pole of the light emitting device according to a second light emitting control signal connected to the control end of the pixel circuit, and the second pole of the light emitting device is connected with the second power voltage input end.

Optionally, the first leakage suppression module includes a connection line connecting the at least one second intermediate node and the at least one first intermediate node.

Optionally, the first leakage suppression module further includes a second capacitor, one end of the second capacitor is connected to a fixed voltage, and the other end of the second capacitor is electrically connected to the connecting line.

Optionally, the pixel circuit further includes a second leakage suppression module, the second leakage suppression module includes a third capacitor, a first end of the third capacitor is connected to a fixed voltage, and a second end of the third capacitor is electrically connected to at least one second intermediate node;

optionally, in the compensation module, a channel width-to-length ratio of a second sub-transistor between a second intermediate node connected to the second leakage suppression module and a second pole of the driving transistor is smaller than a channel width-to-length ratio of a second sub-transistor between the second intermediate node connected to the second leakage suppression module and a gate of the driving transistor;

optionally, a channel width of the second sub-transistor between the second intermediate node connected to the second leakage suppression module and the second pole of the driving transistor is less than or equal to 1.8 micrometers, and a channel length of the second sub-transistor between the second intermediate node connected to the second leakage suppression module and the second pole of the driving transistor is greater than or equal to 4 micrometers.

Optionally, the pixel circuit further includes a second leakage suppression module, where the second leakage suppression module includes a fourth capacitor and a first control transistor;

the grid electrode of the first control transistor is connected with a second scanning signal, the first electrode of the first control transistor is connected with a first fixed voltage, the second electrode of the first control transistor is electrically connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is electrically connected with at least one second intermediate node;

optionally, the second leakage suppression module further includes a second control transistor, a gate of the second control transistor is connected to the first light emitting control signal or the second light emitting control signal, a first electrode of the second control transistor is connected to a second fixed voltage, and a second electrode of the second control transistor is electrically connected to a first end of the fourth capacitor; wherein the second fixed voltage is less than the first fixed voltage;

optionally, the capacitance value of the fourth capacitor is smaller than the capacitance value of the storage capacitor included in the storage module.

Optionally, the first light-emitting control module and the second light-emitting control module are used for conducting in a plurality of included light-emitting sub-phases of the light-emitting phase, and the driving transistor is used for driving the light-emitting module to emit light in the light-emitting sub-phases;

The pixel circuit further comprises a second initialization module and a third initialization module, wherein the control end of the second initialization module and the control end of the third initialization module are connected with reset control signals, the second initialization module is used for writing second initialization voltage to the first pole of the driving transistor in a plurality of reset sub-phases included in the light-emitting phase, and the third initialization module is used for writing third initialization voltage to the second pole of the driving transistor and the first pole of the light-emitting device in the reset sub-phases, wherein each reset phase corresponds to one light-emitting sub-phase, and the reset sub-phase is before the corresponding light-emitting sub-phase;

optionally, the first end of the third initialization module is connected to a third initialization voltage, and the second end of the third initialization module is electrically connected to the first pole of the light emitting device or the second end of the third initialization module is electrically connected to the second pole of the driving transistor; wherein, the reset control signal overlaps with the effective level of the second light emitting control signal, the effective level of the first light emitting control signal overlaps with the effective level of the second light emitting control signal, and the effective level of the reset control signal is before the effective level of the first light emitting control signal.

In a second aspect, an embodiment of the present invention further provides a display panel, including the pixel circuit provided in the first aspect.

The embodiment of the invention provides a pixel circuit and a display panel, wherein the pixel circuit comprises a driving transistor, a data writing module, a first initializing module and a first leakage suppressing module, wherein the first leakage suppressing module is used for coupling the grid voltage variation of the driving transistor to a first intermediate node connected with the first leakage suppressing module in a positive correlation manner, so that after the data writing stage, the potential of the first intermediate node of the first leakage suppressing module is the sum of the first initializing voltage and the coupling quantity (namely, the voltage positively correlated with the grid voltage variation of the driving transistor), and further, compared with the prior art, the voltage difference between the grid of the driving transistor and the first intermediate node in the first initializing module is reduced, the leakage of the first initializing module is further reduced, the grid voltage of the driving transistor can be well maintained during the light emitting stage, the stability of the driving current generated by the driving transistor is further ensured, and the screen flicker phenomenon is improved.

Drawings

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

fig. 5 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 11 is a driving timing diagram of another pixel circuit according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

As described in the background art, in the display panel manufactured by the low-temperature polysilicon process, the electric leakage of the initialization transistor is large, and when the light emitting device emits light after the initialization transistor is set as the double-gate transistor, the potential difference between the intermediate node of the double-gate initialization transistor and the gate of the driving transistor is large, which causes the screen to flicker. The inventors have found that the above problems occur because the operation of the existing pixel circuit includes an initialization phase, a data writing phase, and a light emitting phase. In the initialization phase, the initialization transistor writes an initialization voltage to the gate of the drive transistor, and the intermediate node potential of the initialization transistor is also equal to the initialization voltage. In the data writing stage, the data voltage is written to the gate of the driving transistor, but the potential of the intermediate node of the initializing transistor does not change greatly and is still close to the initializing voltage. In the light-emitting stage, the driving transistor drives the light-emitting device to emit light according to the data voltage written into the grid electrode of the driving transistor, and the voltage difference between the data voltage and the initializing voltage is larger, so that the voltage difference between the grid electrode of the driving transistor and the middle node of the initializing transistor is larger in the light-emitting stage, the electric leakage of the initializing transistor is still larger, the data voltage written into the grid electrode of the driving transistor cannot be well maintained, the driving current generated by the driving transistor is related to the voltage of the grid electrode of the driving transistor, and therefore the driving current generated by the driving transistor of the light-emitting device is unstable, the brightness of the light-emitting device is changed, and finally the screen body is enabled to flicker.

For the above reasons, an embodiment of the present invention provides a pixel circuit, and fig. 1 is a schematic structural diagram of the pixel circuit provided in the embodiment of the present invention, and referring to fig. 1, the pixel circuit includes: a driving transistor DT, a data writing module 110, a storage module 120, a first initializing module 130, and a first leakage suppressing module 140;

the first initialization module 130 is configured to write a first initialization voltage Vref1 to the gate of the driving transistor DT during an initialization phase; the first initialization module 130 includes at least two first sub-transistors T01 connected in series, adjacent first sub-transistors T01 are electrically connected through a first intermediate node N1 therebetween, the first leakage suppression module 140 is electrically connected with at least one first intermediate node N1, and the first leakage suppression module 140 is configured to couple the gate potential variation of the driving transistor DT to the first intermediate node N1 connected by the first leakage suppression module 140 in positive correlation;

the data writing module 110 is configured to write a data voltage Vdata to the gate of the driving transistor DT during a data writing phase; the storage module 120 is used for storing the gate voltage of the driving transistor DT.

The pixel circuit further includes a light emitting device D1, and the driving transistor DT and the light emitting device D1 are connected between the first power supply voltage input terminal VDD and the second power supply voltage input terminal VSS. Also, fig. 1 exemplarily illustrates that the control terminal of the first initialization module 130 is connected to the first Scan signal Scan1, and the control terminal of the data writing module 110 is connected to the second Scan signal Scan2.

Optionally, the data writing module 110 includes a data writing transistor. As shown in fig. 1, the data writing module 110 may be directly electrically connected to the gate of the driving transistor DT, and the data writing module 110 directly writes the data voltage Vdata to the gate of the driving transistor DT. In other alternative embodiments of the present invention, the data writing module 110 may be electrically connected to the first electrode of the driving transistor DT, and when the data writing module 110 is electrically connected to the first electrode of the driving transistor DT, the pixel circuit may further include a compensation module, and the data writing module 110 writes the data voltage Vdata to the gate of the driving transistor DT through the driving transistor DT and the compensation module.

Specifically, the first initialization module 130 includes at least two first sub-transistors T01 connected in series, that is, the first initialization module 130 includes multiple gate transistors, where the number of gates of the multiple gate transistors is determined by the number of first sub-transistors T01 connected in series included in the first initialization module 130. Specifically, when the first initialization module 130 includes n (n is greater than or equal to 2) first sub-transistors T01 connected in series, the multi-gate transistors included in the first initialization module 130 are n-gate transistors. Optionally, in this embodiment, the transistors included in each module in the pixel circuit are low-temperature polysilicon transistors prepared by using a low-temperature polysilicon process.

The operation of the pixel circuit of the present embodiment may include an initialization phase, a data writing phase, and a light emitting phase.

In the initialization phase, the first initialization module 130 writes the first initialization voltage Vref1 to the gate of the driving transistor DT, and in the initialization phase, the gate voltage of the driving transistor DT is equal to the first initialization voltage Vref1, and the voltage of the first intermediate node N1 between the adjacent first sub-transistors T01 of the first initialization module is also equal to the initialization voltage. In the data writing stage, the data writing module 110 writes the data voltage Vdata to the gate of the driving transistor DT, and thus the gate voltage of the driving transistor DT is changed from the initialization stage to the data writing stage, i.e., from the initialization voltage to the data voltage Vdata. In the light emitting stage, the driving transistor DT generates a driving current according to its gate voltage to drive the light emitting device D1 to emit light.

In this embodiment, since the first leakage suppression module 140 is disposed in the pixel circuit, the first leakage suppression module 140 is configured to couple the gate voltage variation of the driving transistor DT to the first intermediate node N1 connected to the first leakage suppression module 140 in a positive correlation, so that after the data writing stage, the potential of the first intermediate node N1 of the first leakage suppression module 140 is the sum of the first initialization voltage Vref1 and the coupling amount (i.e., the voltage that is in positive correlation with the gate voltage variation of the driving transistor DT), and thus, compared with the prior art, the voltage difference between the gate of the driving transistor DT and the first intermediate node N1 in the first initialization module 130 is reduced after the data writing stage, and thus, the leakage of the first initialization module 130 is reduced, and the gate voltage of the driving transistor DT can be well maintained during the light emitting stage, thereby ensuring the stability of the driving current generated by the driving transistor DT and improving the screen flicker phenomenon. In addition, in the pixel circuit of the embodiment, no matter which gray scale the data voltage Vdata corresponding to is written into the gate of the driving transistor DT during the data writing phase, due to the effect of the first leakage suppression module 140, after the data writing phase, the variation of the gate voltage of the driving transistor DT (for example, for the pixel circuit shown in fig. 1, the variation of the gate voltage of the driving transistor DT is equal to the difference between the data voltage Vdata and the first initialization voltage Vref 1) is positively coupled to the first intermediate node N1 in the first initialization module 130 connected to the first leakage suppression module 140, so that the voltage difference between the gate voltage of the driving transistor DT and the voltage of the first intermediate node N1 of the first initialization module 130 is reduced during the data writing phase, and the leakage of the screen can be improved during any display gray scale compared with the prior art.

In the prior art, the initializing transistor corresponding to the first initializing module 130 is set as an oxide transistor in a part of the pixel circuits to reduce the leakage current, but the manufacturing process of the oxide transistor is complex, and the size of the oxide transistor is large, which is not beneficial to the realization of high pixel density. And because the channel type of the oxide transistor is different from that of the low-temperature polysilicon transistor in the pixel circuit, a new gate driving circuit is required to be added in the frame area of the display panel, which is not beneficial to the realization of a narrow frame. The pixel circuit of the embodiment does not need to set the initialization transistor included in the first initialization module 130 to be an oxide transistor, and the pixel circuit is prepared by adopting a low-temperature polysilicon process, which is beneficial to simplifying the preparation process and realizing a display panel with high pixel density and a narrow frame.

The pixel circuit of the embodiment includes a driving transistor, a data writing module, a first initializing module and a first leakage suppressing module, where the first leakage suppressing module is configured to couple a gate voltage variation of the driving transistor to a first intermediate node connected to the first leakage suppressing module in a positive correlation, so that after the data writing stage, a potential of the first intermediate node of the first leakage suppressing module is a sum of a first initializing voltage and a coupling amount (i.e., a voltage directly related to the gate voltage variation of the driving transistor), and further, compared with the prior art, a voltage difference between a gate of the driving transistor and the first intermediate node in the first initializing module is reduced after the data writing stage, so as to reduce leakage of the first initializing module, so that a gate voltage of the driving transistor can be well maintained during a light emitting stage, further, stability of a driving current generated by the driving transistor is ensured, and a screen flicker phenomenon is improved.

Fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 2, optionally, the first leakage suppression module 140 includes a first capacitor C1, a first plate of the first capacitor C1 is electrically connected to a gate of the driving transistor DT, and a second plate of the first capacitor C1 is electrically connected to at least one first intermediate node N1.

Specifically, the capacitor has a coupling effect, and the first leakage suppression module 140 includes a first capacitor C1, where the first capacitor C1 is connected to the gate of the driving transistor DT and at least one first intermediate node N1 of the first initialization module 130, so that after the data writing phase, the first capacitor C1 can couple the voltage variation of the gate of the driving transistor DT to the first intermediate node N1 connected to the first leakage suppression module 140 in a positive correlation, and thus, compared with the prior art, the voltage difference between the gate of the driving transistor DT and the first intermediate node N1 in the first initialization module 130 is reduced after the data writing phase, and thus, the leakage of the first initialization module 130 is reduced.

It should be noted that, a person skilled in the art can reasonably set the capacitance of the first capacitor according to the voltage coupling amount of the gate voltage of the driving transistor to the voltage coupling amount of the first intermediate node, and the capacitance of the first capacitor is not particularly limited, so that compared with the prior art, the voltage difference between the gate voltage of the driving transistor and the first intermediate node is reduced after the data writing stage.

Specifically, in the above embodiment, after the data writing stage, the voltage difference between the gate of the driving transistor DT and the first intermediate node N1 connected to the first leakage suppressing module 140 in the first initializing module 130 is reduced, so that the leakage of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppressing module 140 and the gate of the driving transistor DT is reduced.

On the basis of the above technical solution, optionally, in the first initialization module 130, a channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 is smaller than a channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the second end of the first initialization module 130; the first end of the first initialization module 130 is connected to the first initialization voltage Vref1, and the second end of the first initialization module 130 is connected to the gate of the driving transistor DT.

Specifically, the smaller the width-to-length ratio of the first sub-transistor T01, the smaller the leakage of the first sub-transistor T01. In this embodiment, by setting the channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 to be smaller than the channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the second end of the first initialization module 130, the leakage current of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 can be smaller, thereby further reducing the leakage current of the first initialization module 130.

Optionally, a channel width of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 is less than or equal to 1.8 micrometers, and a channel length of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 is greater than or equal to 4 micrometers, so that a channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 in the first initialization module 130 may be smaller.

Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 3, optionally, the pixel circuit further includes a compensation module 150, where the compensation module 150 is configured to write information including a threshold voltage of the driving transistor DT to a gate of the driving transistor DT during a data writing phase; the compensation module 150 includes at least two serially connected second sub-transistors T02, and adjacent second sub-transistors T02 are electrically connected through a second intermediate node N2 therebetween.

Specifically, the first end of the compensation module 150 is electrically connected to the second pole of the driving transistor DT, and the second end of the compensation module 150 is electrically connected to the gate of the driving transistor DT. Since the compensation module 150 is connected to the gate of the driving transistor DT, the leakage of the compensation module 150 also makes the gate voltage of the driving transistor DT not well maintained in the light emitting stage. In this embodiment, the compensation module 150 includes at least two second sub-transistors T02 connected in series, that is, the compensation module 150 is also configured as a multi-gate transistor, so that the leakage current of the compensation module 150 is smaller, and further the gate potential of the driving transistor DT in the light-emitting stage can be better maintained, so as to ensure that the light-emitting brightness of the light-emitting device D1 is more stable, and improve the flicker phenomenon of the display panel.

With continued reference to fig. 3, optionally, the control terminal of the first initialization module 130 is connected to the first Scan signal Scan1, the first terminal of the first initialization module 130 is connected to the first initialization voltage Vref1, and the second terminal of the first initialization module 130 is electrically connected to the gate of the driving transistor DT. Optionally, the first initialization module 130 includes a first initialization transistor T1, a gate of the first initialization transistor T1 is used as a control terminal of the first initialization module 130, a first pole of the first initialization transistor T1 is used as a first terminal of the first initialization module 130, and a second pole of the first initialization transistor T1 is used as a second terminal of the first initialization module 130.

Fig. 3 also illustrates that the first leakage suppression module 140 includes a first capacitor C1.

Optionally, the control end of the data writing module 110 is connected to the second Scan signal Scan2, the first end of the data writing module 110 is connected to the data voltage Vdata, and the second end of the data writing module 110 is electrically connected to the first pole of the driving transistor DT; the control end of the compensation module 150 is connected to the second Scan signal Scan2, the first end of the compensation module 150 is electrically connected to the second pole of the driving transistor DT, and the second end of the compensation module 150 is electrically connected to the gate of the driving transistor DT. Optionally, the data writing module 110 includes a data writing transistor T2, a gate of the data writing transistor T2 is used as a control terminal of the data writing module 110, a first pole of the data writing transistor T2 is used as a first terminal of the data writing module 110, and a second pole of the data writing transistor T2 is used as a second terminal of the data writing module 110. Optionally, the compensation module 150 includes a compensation transistor T3, a gate of the compensation transistor T3 is used as a control terminal of the compensation module 150, a first pole of the compensation transistor T3 is used as a first terminal of the compensation module 150, and a second pole of the compensation transistor T3 is used as a second terminal of the compensation module 150.

Optionally, the pixel circuit further includes a first light emitting control module 160 and a second light emitting control module 170, where the first light emitting control module 160 is configured to control a conducting state between the first power voltage input terminal VDD and the first pole of the driving transistor DT according to a first light emitting control signal EM1 connected to the control terminal thereof, and the second light emitting control module 170 is configured to control a conducting state between the second pole of the driving transistor DT and the first pole of the light emitting device D1 according to a second light emitting control signal EM2 connected to the control terminal thereof, and the second pole of the light emitting device D1 is connected to the second power voltage input terminal VSS.

The control end of the first light emitting control module 160 is connected to the first light emitting control signal EM1, the first end of the first light emitting control module 160 is electrically connected to the first power voltage input end VDD, and the second end of the first light emitting control module 160 is electrically connected to the first electrode of the driving transistor DT. Optionally, the first light emitting control module 160 includes a first light emitting control transistor T4, a gate of the first light emitting control transistor T4 is used as a control terminal of the first light emitting control module 160, a first pole of the first light emitting control transistor T4 is used as a first terminal of the first light emitting control module 160, and a second pole of the first light emitting control transistor T4 is used as a second terminal of the first light emitting control module 160.

The control end of the second light emitting control module 170 is connected to the second light emitting control signal EM2, the first end of the second light emitting control module 170 is electrically connected to the first pole of the driving transistor DT, the second end of the second light emitting control module 170 is electrically connected to the first pole of the light emitting device D1, and the second pole of the light emitting device D1 is electrically connected to the second power voltage input end VSS. Optionally, the second light-emitting control module 170 includes a second light-emitting control transistor T5, a gate of the second light-emitting control transistor T5 is used as a control terminal of the second light-emitting control module 170, a first pole of the second light-emitting control transistor T5 is used as a first terminal of the second light-emitting control module 170, and a second pole of the second light-emitting control transistor T5 is used as a second terminal of the second light-emitting control module 170.

Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 4, optionally, the first leakage suppression module 140 includes a connection line 141 connecting at least one second intermediate node N2 and at least one first intermediate node N1.

Fig. 5 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention, where the driving timing diagram may be used to drive the pixel circuit shown in fig. 4, and optionally, each transistor is a P-type transistor in the pixel circuit shown in fig. 4. Referring to fig. 4 and 5, the operation of the pixel circuit includes an initialization phase t0, a data writing phase t1, and a light emitting phase t2.

In the initialization stage T0, the first Scan signal Scan1 is at a low level, the first initialization transistor T1 is turned on, and the first initialization voltage Vref1 is transmitted to the gate of the driving transistor DT. Therefore, at the completion of the initialization phase, the potential of the gate of the driving transistor DT and the first intermediate node N1 of the first initialization transistor T1 are both equal to the first initialization voltage Vref1.

In the data writing stage T1, the second Scan signal Scan2 is at a low level, the data writing transistor T2 and the compensation transistor T3 are turned on, the data voltage Vdata is written to the gate of the driving transistor DT through the data writing transistor T2, the driving transistor DT and the compensation transistor T3 until the gate voltage of the driving transistor DT is equal to vdata+vth (where Vth represents the threshold voltage of the driving transistor DT), and the driving transistor DT is turned off, so that writing of the data voltage Vdata to the gate of the driving transistor DT and compensation of the threshold voltage of the driving transistor DT are realized. When the data writing period T1 is completed, the voltage of the gate of the driving transistor DT and the voltage of the second intermediate node N2 of the compensating transistor T3 are both equal to vdata+vth.

In the light emitting stage T2, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at low level, the first light emitting control transistor T4 and the second light emitting control transistor T5 are turned on, and the driving transistor DT generates a driving current according to the self gate voltage and the first electrode voltage to drive the light emitting device D1 to emit light.

In this embodiment, the first leakage suppression module 140 includes a connection line 141 connecting at least one second intermediate node N2 and at least one first intermediate node N1, so that when the data writing phase t1 is completed, the potential of the first intermediate node N1 is equal to the potential of the second intermediate node N2, so that the potential of the first intermediate node N1 of the first initialization module 130 connected to the second intermediate node N2 is also equal to vdata+vth, so that the voltage difference between the intermediate node of the first initialization module 130 and the driving transistor DT is nearly 0, and the leakage of the first initialization module 130 is reduced, so that the gate potential of the driving transistor DT can be well maintained in the light emitting phase t 2.

Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, referring to fig. 6, on the basis of the pixel circuit shown in fig. 4, optionally, the first leakage suppression module 140 further includes a second capacitor C2, where one end of the second capacitor C2 is connected to a fixed voltage, and the other end is electrically connected to the connecting line 141.

The fixed voltage of the second capacitor C2 may be equal to the first power voltage input from the first power voltage input terminal VDD. The fixed voltage connected to one end of the second capacitor C2 may be equal to the first initialization voltage Vref1 or other fixed voltages, which is not limited herein, and fig. 6 illustrates that the second capacitor C2 is connected to the first power voltage input terminal VDD.

Specifically, because of the parasitic capacitance between the second intermediate node N2 of the compensation transistor T3 and the gate of the compensation transistor T3, the potential jump of the second Scan signal Scan2 connected to the gate of the compensation transistor T3 affects the potential of the second intermediate node N2 of the compensation transistor T3. The potential jump variable of the second intermediate node N2 of the compensation transistor T3 caused by the gate potential jump variable of the compensation transistor T3 can be expressed by the following formula:

wherein DeltaV _Scan2 Representing the voltage jump variable DeltaV of the second Scan signal Scan2 of the gate access of the compensation transistor T3 _N2 The voltage jump variable of the second Scan signal Scan2 representing the gate access of the compensation transistor T3 causes the voltage jump variable of the second intermediate node N2, C' represents the capacitance value of the parasitic capacitance between the second intermediate node N2 and the gate of the compensation transistor T3, C ₀ The capacitance value of the other capacitance (except the parasitic capacitance between the second intermediate node N2 and the gate of the compensation transistor T3) connected to the second intermediate node N2 is represented.

In this embodiment, the other capacitors connected to the second intermediate node N2 include a second capacitor C2, so that the jump variable of the second intermediate node N2 caused when the second Scan signal Scan2 jumps may be smaller, and the potential of the second intermediate node N2 may be kept relatively stable when the second Scan signal Scan2 jumps, and the potential of the first intermediate node N1 connected to the second intermediate node N2 through the second connection line 141 may also be kept relatively stable. For example, when the data writing phase is completed, the second Scan signal Scan2 jumps from low potential to high potential, and the second leakage suppression module is provided with the second capacitor C2, so that the potential of the second intermediate node N2 is not greatly affected by the jump of the second Scan signal Scan2, so that the potential of the second intermediate node N2 is still close to vdata+vth, the potential of the first intermediate node N1 connected to the second intermediate node N2 through the connection line 141 is still close to vdata+vth, and further, after the data writing phase is completed, the voltage difference between the second intermediate node N2 of the compensation transistor T3 and the gate of the driving transistor DT is smaller, and the voltage difference between the first intermediate node N1 of the first initialization transistor T1 and the gate of the driving transistor DT is also smaller, so that the gate potential of the compensation transistor T3 and the first initialization transistor T1 can be well maintained in the light-emitting phase after the data writing phase, and further, the screen flicker phenomenon can be improved.

Moreover, by setting that the second leakage suppression module includes the second capacitor C2, one end of the second capacitor C2 is connected to the fixed voltage, and the other end is electrically connected to the connecting line 141 (that is, the other end is connected to the first intermediate node N1 and the second intermediate node N2), the total capacitance connected to the first intermediate node N1 of the first initialization module 130 is increased, so that the leakage speed of the first sub-transistor T01 between the first intermediate node N1 and the first end of the first initialization module 130 (the first end of the first initialization module 130 is connected to the first initialization voltage Vref 1) is slowed down, and the voltage stabilizing effect on the first intermediate node N1 is played. And the total capacitance connected to the second intermediate node N2 of the compensation module 150 is increased, so that the leakage speed between the second intermediate node N2 and the first end of the compensation module 150 (the first end of the compensation module 150 is electrically connected to the second electrode of the driving transistor DT) is reduced, and the voltage stabilizing effect on the second intermediate node N2 is achieved.

Fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 7, optionally, the pixel circuit further includes a second leakage suppression module 180, where the second leakage suppression module 180 includes a third capacitor C3, a first end of the third capacitor C3 is connected to a fixed voltage, and a second end of the third capacitor C3 is electrically connected to at least one second intermediate node N2.

The fixed voltage of the third capacitor C3 may be equal to the first power voltage input from the first power voltage input terminal VDD. The fixed voltage connected to one end of the third capacitor C3 may be equal to the first initialization voltage Vref1 or other fixed voltages, which is not limited herein, and fig. 7 illustrates that the third capacitor C3 is connected to the first power voltage input terminal VDD.

Specifically, by setting that the pixel circuit includes the second leakage suppression module 180, the first end of the third capacitor C3 included in the second leakage suppression module 180 is connected to a fixed voltage, and the voltage value of the fixed voltage is maintained unchanged, that is, the potential of the first end of the third capacitor C3 is always stable, the second end of the third capacitor C3 is electrically connected with at least one second intermediate node N2 in the compensation module 150, so that the total capacitance connected with the second intermediate node N2 is increased, the data writing stage is completed, and when the second Scan signal Scan2 jumps, the potential jump variable of the second intermediate node N2 can be smaller. Moreover, since the gate of the driving transistor DT is connected to the storage module 120, the storage module 120 includes a storage capacitor, so that the total capacitance connected to the gate of the driving transistor DT is larger, and thus the data writing stage is completed, when the second Scan signal Scan2 jumps, the potential jump variable of the gate of the driving transistor DT may be smaller, and further, when the data writing stage is completed, the voltage difference between the second intermediate node N2 of the compensation module 150 and the gate of the driving transistor DT may be smaller, and further, the leakage of the compensation module 150 may be smaller, and the gate potential of the driving transistor DT may be better maintained in the light emitting stage.

Specifically, the voltage difference between the second intermediate node N2 of the compensation module 150 and the gate of the driving transistor DT may be smaller, so that the leakage current of the second sub-transistor T02 between the second intermediate node N2 of the compensation module 150 and the gate of the driving transistor DT may be smaller. In other alternative embodiments of the present invention, in the compensation module 150, the channel width-to-length ratio of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the second pole of the driving transistor DT is smaller than the channel width-to-length ratio of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the gate of the driving transistor DT, so that the leakage of the second sub-transistor T02 between the second intermediate node N2 and the second pole of the driving transistor DT in the compensation module 150 can be smaller, further reducing the leakage of the compensation module 150, further ensuring that the gate potential of the driving transistor DT in the light-emitting stage can be well maintained, and further improving the screen flicker phenomenon.

Optionally, the channel width of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the second pole of the driving transistor DT is less than or equal to 1.8 micrometers, and the channel length of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the second pole of the driving transistor DT is greater than or equal to 4 micrometers, so that in the compensation module 150, the channel width-to-length ratio of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the second pole of the driving transistor DT may be smaller.

Fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 8, optionally, the pixel circuit further includes a second leakage suppression module 180, where the second leakage suppression module 180 includes a fourth capacitor C4 and a first control transistor T6;

the gate of the first control transistor T6 is connected to the second Scan signal Scan2, the first pole of the first control transistor T6 is connected to the first fixed voltage V1, the second pole of the first control transistor T6 is electrically connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is electrically connected to the at least one second intermediate node N2.

In this embodiment, the first control transistor T6 of the second leakage suppression module 180 has the same channel type as the compensation transistor T3. The driving timing shown in fig. 5 is also used to drive the pixel circuit shown in fig. 8, and optionally, each transistor in the pixel circuit shown in fig. 8 is a P-type transistor, and referring to fig. 8 and 5, the operation process of the pixel circuit includes an initialization phase t0, a data writing phase t1 and a light emitting phase t2.

In the initialization stage T0, the first Scan signal Scan1 is at a low level, the first initialization transistor T1 is turned on, and the first initialization voltage Vref1 is transmitted to the gate of the driving transistor DT. Therefore, at the completion of the initialization phase T0, the potential of the gate of the driving transistor DT and the first intermediate node N1 of the first initialization transistor T1 are both equal to the first initialization voltage Vref1.

In the data writing stage T1, the second Scan signal Scan2 is at a low level, the data writing transistor T2 and the compensation transistor T3 are turned on, the data voltage Vdata is written to the gate of the driving transistor DT through the data writing transistor T2, the driving transistor DT and the compensation transistor T3 until the gate voltage of the driving transistor DT is equal to vdata+vth (where Vth represents the threshold voltage of the driving transistor DT), and the driving transistor DT is turned off, so that writing of the data voltage Vdata to the gate of the driving transistor DT and compensation of the threshold voltage of the driving transistor DT are realized. When the data writing period T1 is completed, the voltage of the gate of the driving transistor DT and the voltage of the second intermediate node N2 of the compensating transistor T3 are both equal to vdata+vth. In the data writing stage T1, the first control transistor T6 is turned on in response to the low-level second Scan signal Scan2, so that the first end of the fourth capacitor C4 is the first fixed voltage V1.

When the data writing phase ends T1, the second Scan signal Scan2 jumps from low level to high level, the first control transistor T6 is turned off, and the first end of the fourth capacitor C4 is kept at the first fixed voltage V1 because the first end of the fourth capacitor C4 has no signal input. Because of the fourth capacitor C4, the potential jump of the second Scan signal Scan2 does not greatly affect the potential of the second intermediate node N2 between two adjacent second sub-transistors T02 of the compensation transistor T3, so that the potential difference between the gate of the second intermediate node N2 and the gate of the driving transistor DT is not too large, and further, the leakage of the compensation module 150 can be ensured to be smaller, so that the gate potential of the driving transistor DT can be well maintained.

In the light emitting stage T2, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at low level, the first light emitting control transistor T4 and the second light emitting control transistor T5 are turned on, and the driving transistor DT generates a driving current according to the self gate voltage and the first electrode voltage to drive the light emitting device D1 to emit light. Since the potential change of the second intermediate node N2 connected to the second leakage suppression module 180 in the compensation transistor T3 may be smaller at the end of the data writing period T1, the difference between the second intermediate node N2 connected to the second leakage suppression module 180 and the gate potential of the driving transistor DT in the compensation transistor T3 in the light emitting period is smaller, so that the leakage of the compensation transistor T3 in the light emitting period is still smaller, thereby ensuring that the gate potential of the driving transistor DT in the light emitting period can be well maintained, the driving current generated by the driving transistor DT in the light emitting period T2 is relatively stable, and the light emitting brightness of the light emitting device D1 is ensured to be stable, thereby improving the flicker phenomenon of the display panel including the pixel circuit of the embodiment.

Alternatively, the first light emission control signal EM1 and the second light emission control signal EM2 are the same. The first light emission control signal EM1 and the second light emission control signal EM2 are the same, and for the same pixel circuit, the control end of the first light emission control module 160 and the control end of the second light emission control module 170 may be connected to the same light emission control signal line in the display panel, so that the number of wires in the display panel is smaller, and the difficulty of wire arrangement is reduced.

In the pixel circuit shown in fig. 8, by setting the second leakage suppression module 180 to include the first control transistor T6 and the fourth capacitor C4, the potential of the second intermediate node N2 of the compensation transistor T3 connected to the second leakage suppression module 180 is less affected by the transition of the second Scan signal Scan2, so that the leakage of the second sub-transistor T02 in the compensation transistor T3 between the second intermediate node N2 and the gate of the driving transistor DT is less, and the gate potential of the driving transistor DT can be well maintained.

In other alternative embodiments of the present invention, the leakage of the second sub-transistor T02 between the second intermediate node N2 of the compensation transistor T3 connected to the second leakage suppression module 180 and the second pole of the driving transistor DT can also be reduced by providing different configurations of the second leakage suppression module 180. In the prior art, at low gray scale, the display effect of the display panel is not ideal due in part to the leakage of the second sub-transistor T02 between the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT, and in order to reduce the leakage of the second sub-transistor T02 between the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT, the embodiment of the present invention provides the pixel circuit structure shown in fig. 9.

Fig. 9 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, referring to fig. 9, optionally, the second leakage suppression module 180 further includes a second control transistor T7, a gate of the second control transistor T7 is connected to the first light emitting control signal EM1 or the second light emitting control signal EM2, a first pole of the second control transistor T7 is connected to the second fixed voltage V2, and a second pole of the second control transistor T7 is electrically connected to a first end of the fourth capacitor C4; the second fixed voltage V2 is smaller than the first fixed voltage V1.

The channel type of the second control transistor T7 is the same as the channel types of the first light emitting control transistor T4 and the second light emitting control transistor T5, and optionally, in this embodiment, the first control transistor T6, the first light emitting control transistor T4, and the second light emitting control transistor T5 are P-type transistors.

Specifically, the second leakage suppression module 180 further controls whether the first end of the fourth capacitor C4 is connected to the second fixed voltage V2 according to the first light emitting control signal EM1 or the second light emitting control signal EM 2. Within one frame, the effective potential signal of the first light emission control signal EM1 and the effective potential signal of the second light emission control signal EM2 are both subsequent to the effective potential signal of the second Scan signal Scan 2. In the pixel circuit of the present embodiment, in the data writing stage, the first control transistor T6 is turned on according to the effective potential signal of the second Scan signal Scan2, the potential of the first end of the fourth capacitor C4 is equal to the first fixed voltage V1, and in the light emitting stage, the second control transistor T7 is turned on according to the effective potential of the first light emitting control signal EM1 or the second light emitting control signal EM2, and the potential of the first end of the fourth capacitor C4 is equal to the second fixed voltage V2.

In the array substrate prepared by the low-temperature polysilicon process, each transistor in the pixel circuit is usually a P-type transistor, and in this embodiment, each transistor in the pixel circuit may be a P-type transistor. At low gray scale, after writing the data voltage Vdata into the gate of the driving transistor DT in the pixel circuit, the voltages of the gate and the second pole of the driving transistor DT and the voltage of the second intermediate node N2 of the compensation transistor T3 are usually positive values, for example, 2V to 3V. In the light emitting stage, the first light emitting control transistor T4 and the second light emitting control transistor T5 are turned on, and the driving transistor DT is turned on, and the voltage of the second pole of the driving transistor DT is generally negative, for example, -1V, while the voltage of the second intermediate node N2 of the compensating transistor T3 is still positive (2V to 3V), such that the difference between the voltage of the second intermediate node N2 of the compensating transistor T3 and the voltage of the second pole of the driving transistor DT is larger in the light emitting stage. The second leakage suppression module 180 further includes a second control transistor T7, where the gate of the second control transistor T7 is connected to the first light emission control signal EM1 or the second light emission control signal EM2, the first electrode of the second control transistor T7 is connected to the second fixed voltage V2, and the second electrode of the second control transistor T7 is electrically connected to the first end of the fourth capacitor C4, so that in the light emitting stage, the first end of the fourth capacitor C4 is connected to the second fixed voltage V2, and since the second fixed voltage V2 is smaller than the first fixed voltage V1, the voltage at the first end of the fourth capacitor C4 is reduced (the first fixed voltage V1 is reduced to the second fixed voltage V2), and due to the coupling effect of the fourth capacitor C4, the voltage of the second intermediate node N2 of the compensation transistor T3 connected to the fourth capacitor C4 is also reduced, so that in turn, the voltage difference between the second intermediate node N2 of the compensation transistor T3 connected to the fourth capacitor C4 and the second intermediate node N2 of the compensation transistor DT is reduced, and the voltage difference between the second intermediate node N2 of the compensation transistor T3 and the second intermediate node of the compensation transistor DT is further reduced, and the voltage of the fourth capacitor C4 is further reduced, and the voltage difference between the second intermediate node and the second transistor DT is further reduced, and the voltage of the compensation transistor DT is further reduced, and the voltage difference between the voltage transistor is further reduced.

In the light emitting stage, the second electrode potential of the driving transistor DT is the sum of the voltage input from the second power voltage input terminal VSS and the voltage across the light emitting device D1. At the end of the light emitting period, the first light emitting control signal EM1 and the second light emitting control signal EM2 are changed from the active potential signal to the inactive potential signal, the first light emitting control module 160 and the second light emitting control module 170 are turned off, the driving transistor DT is still turned on, the first pole voltage of the driving transistor DT is the first power voltage input by the first power voltage input terminal VDD, and the first power voltage is higher than the sum of the second power voltage input by the second power voltage input terminal VSS and the voltage across the light emitting device D1, so that the voltage of the second pole of the driving transistor DT is pulled up. And because there is parasitic capacitance between the gate of the second control transistor T7 and the second pole of the second control transistor T7, the second pole potential of the second control transistor T7 is coupled to rise at the end of the light emitting phase, and the potential of the second intermediate node N2 of the compensation transistor T3 is coupled to rise due to the coupling action of the fourth capacitance C4, that is, the potential of the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT rise simultaneously, so that the potential difference between the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT is still smaller, and the leakage of the sub-transistor between the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT is smaller.

Optionally, the capacitance value of the fourth capacitor C4 is smaller than the capacitance value of the storage capacitor included in the storage module 120.

Specifically, since there is a parasitic capacitance between the gate of the compensation transistor T3 and the second pole of the compensation transistor T3 (the second pole of the compensation transistor T3 is electrically connected to the gate of the driving transistor DT as the second end of the compensation module 150), there is also a parasitic capacitance between the second intermediate node N2 of the compensation transistor T3 and the gate of the compensation transistor T3, so that when the second Scan signal Scan2 jumps from the active potential signal to the inactive potential signal at the end of the data writing phase, both the potential of the second intermediate node N2 of the compensation transistor T3 and the potential of the second pole of the compensation transistor T3 will change due to the jump of the second Scan signal Scan2, and accordingly, the gate potential of the driving transistor DT will also change due to the jump of the second Scan signal Scan 2. The compensation transistor T3 is a P-type transistor, the effective potential signal of the second Scan signal Scan2 is a low potential signal, and the ineffective potential signal is a high potential signal, so that when the data writing phase is ended, the second Scan signal Scan2 jumps from the low potential signal to the high potential signal, and accordingly, the gate potential of the driving transistor DT and the potential of the second intermediate node N2 of the compensation transistor T3 will rise accordingly, and since the capacitance value of the fourth capacitor C4 is smaller than the capacitance value of the storage capacitor Cst, the potential rise of the gate of the driving transistor DT is smaller than the potential rise of the second intermediate node N2. By setting the second leakage suppression module 180 to include the second control transistor T7, the voltage at one end connected to the fourth capacitor C4 and the second control transistor T7 is reduced relative to the voltage at one end connected to the second control transistor T7 during the data writing phase, so that the potential of the second intermediate node N2 of the compensation transistor T3 connected to the fourth capacitor C4 is reduced by coupling, and thus the potential difference between the second intermediate node N2 of the compensation transistor T3 and the gate of the driving transistor DT during the light emitting phase is also reduced, and further the leakage of the sub-transistor between the second intermediate node N2 of the compensation transistor T3 and the gate of the driving transistor DT connected to the second leakage suppression module 180 is further reduced, that is, the leakage of the compensation transistor T3 is further reduced, thereby further ensuring the stability of the gate potential of the driving transistor DT during the light emitting phase and further improving the flicker phenomenon of the display panel.

Fig. 10 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 10, optionally, the first light emitting control module 160 and the second light emitting control module 170 are configured to be turned on in a plurality of included light emitting sub-phases of the light emitting phase, and the driving transistor DT is configured to drive the light emitting module to emit light in the light emitting sub-phases;

the pixel circuit further includes a second initialization module 200 and a third initialization module 190, the control terminal of the second initialization module 200 and the control terminal of the third initialization module 190 are connected to the reset control signal EMR, the second initialization module 200 is used for writing the second initialization voltage Vref2 to the first pole of the driving transistor DT in a plurality of reset sub-phases included in the light emitting phase, and the third initialization module 190 is used for writing the third initialization voltage Vref3 to the second pole of the driving transistor DT and the first pole of the light emitting device D1 in the reset sub-phases, wherein each reset phase corresponds to one light emitting sub-phase, and the reset sub-phase precedes the corresponding light emitting sub-phase.

Optionally, the second initialization module 200 includes a second initialization transistor T8, and the third initialization module 190 includes a third initialization transistor T9. Optionally, the second initialization voltage Vref2 is equal to the first initialization voltage Vref1 or the first power voltage input by the first power voltage input terminal VDD. Optionally, the third initialization voltage Vref3 is equal to the first initialization voltage Vref1.

Optionally, the first end of the third initialization module 190 is connected to the third initialization voltage Vref3, and the second end of the third initialization module 190 is electrically connected to the first pole of the light emitting device D1 or the second end of the third initialization module 190 is electrically connected to the second pole of the driving transistor DT (fig. 10 schematically illustrates a case where the second end of the third initialization module 190 is electrically connected to the first pole of the light emitting device D1); wherein the reset control signal EMR overlaps with the active level of the second light emission control signal EM2, and the active levels of the first light emission control signal EM1 and the second light emission control signal EM2 overlap, the active level of the reset control signal EMR being before the active level of the first light emission control signal EM 1.

Fig. 11 is a driving timing diagram of another pixel circuit according to an embodiment of the invention, where the driving timing diagram can be used to drive the pixel circuit shown in fig. 10, and each transistor in the pixel circuit shown in fig. 10 can be a P-type transistor. Referring to fig. 10 and 11, the operation of the pixel circuit includes an initialization phase t01, a data writing phase t11, and a light emitting phase t21, wherein the light emitting phase t21 includes a plurality of light emitting sub-phases t212 and a plurality of reset sub-phases t211.

In the initialization stage T01, the first Scan signal Scan1 is low, the first initialization transistor T1 is turned on, and the first initialization voltage Vref1 is transmitted to the gate of the driving transistor DT. Therefore, at the completion of the initialization phase T01, the potential of the gate of the driving transistor DT and the first intermediate node N1 of the first initialization transistor T1 are both equal to the first initialization voltage Vref1.

In the data writing stage T11, the second Scan signal Scan2 is at a low level, the data writing transistor T2 and the compensation transistor T3 are turned on, the data voltage Vdata is written to the gate of the driving transistor DT through the data writing transistor T2, the driving transistor DT and the compensation transistor T3 until the gate voltage of the driving transistor DT is equal to vdata+vth (where Vth represents the threshold voltage of the driving transistor DT), and the driving transistor DT is turned off, so that writing of the data voltage Vdata to the gate of the driving transistor DT and compensation of the threshold voltage of the driving transistor DT are realized. When the data writing period T11 is completed, the voltage of the gate of the driving transistor DT and the voltage of the second intermediate node N2 of the compensating transistor T3 are both equal to vdata+vth.

In the reset sub-stage T211 of the light emitting stage T21, the first light emitting control signal EM1 is at a high level, and the first light emitting control transistor T4 is turned off; the second emission control signal EM2 is low, and the second emission control transistor T5 is turned on. The reset control signal EMR is in a low level, the second initialization transistor T8 and the third initialization transistor T9 are both conducted, the second initialization voltage Vref2 is written into the first pole of the driving transistor DT through the second initialization transistor T8, the reset of the first pole of the driving transistor DT is realized, the third initialization voltage Vref3 is written into the first pole of the light emitting device D1 through the third initialization transistor T9, the first pole of the light emitting device D1 can be the anode of the light emitting device D1, and the reset of the anode of the light emitting device D1 is realized; and the third initialization voltage Vref3 is transmitted to the second pole of the driving transistor DT through the third initialization transistor T9 and the second light emission control transistor T5, thereby realizing the reset of the second pole of the driving transistor DT.

It should be noted that, when the second end of the third initialization module is electrically connected to the second pole of the driving transistor, in the reset sub-stage of the light emitting stage, the third initialization voltage is written into the second pole of the driving transistor through the third initialization transistor, so as to realize the reset of the second pole of the driving transistor; the third initialization voltage is transmitted to the first electrode of the light emitting device through the third initialization transistor and the second light emitting control transistor, wherein the first electrode of the light emitting device can be the anode of the light emitting device, and the reset of the anode of the light emitting device is realized;

in the light emitting sub-stage T212 of the light emitting stage T21, the first light emitting control signal EM1 and the second light emitting control signal EM2 are both low level, the first light emitting control transistor T4 and the second light emitting control transistor T5 are turned on, and the driving transistor DT drives the light emitting device D1 to emit light.

The pixel circuit of the present embodiment further includes a second initialization module 200 and a third initialization module 190, where the control end of the second initialization module 200 and the control end of the third initialization module 190 are connected to the reset control signal EMR, the second initialization module 200 is configured to write the second initialization voltage Vref2 to the first pole of the driving transistor DT in a plurality of reset sub-phases t211 included in the light-emitting phase t21, and the third initialization module 190 is configured to write the third initialization voltage Vref3 to the second pole of the driving transistor DT and the first pole of the light-emitting device D1 in the reset sub-phases t211, where each reset phase corresponds to one light-emitting sub-phase t212, and the reset sub-phases t211 precede the corresponding light-emitting sub-phase t212, so that the electric potential of the first pole of the driving transistor DT in the pixel circuit is equal after each reset sub-phase t211 for the display panel including the pixel circuit of the present embodiment. Because the light emitting sub-stage t212 is performed after the corresponding reset sub-stage t211, the potential of the first pole of the driving transistor DT is equal, the potential of the second pole of the driving transistor DT is equal, and the influence degree of the potential of the first pole and the potential of the second pole of the driving transistor DT on the driving current generated by the driving transistor DT is consistent, the light emitting intensity of the light emitting device D1 is more consistent, the light emitting brightness difference of the light emitting device D1 in different light emitting sub-stages t212 is reduced, the visual effect is improved, and the overall display effect is further improved. In addition, the potential of the first electrode of the light emitting device D1 in each pixel circuit is equal, so that the light emitting sub-stage t212 is the same in light emitting process of the light emitting device D1, and accordingly, the light emitting brightness of the light emitting device D1 is more consistent, the visual effect of human eyes is further improved, and the display effect is further improved. In the reset sub-stage before each light emitting sub-stage, the first pole of the light emitting device D1 is reset to the third initialization voltage, so that the problem that the first end potential of the light emitting sub-stage light emitting device gradually rises due to the rising of the second pole potential of the driving transistor DT after the first light emitting control module 160 and the second light emitting control module 170 of the plurality of light emitting sub-stages are turned off, and the light emitting device is more easily lightened and the dark state is difficult to turn off due to the rising of the second pole potential of the driving transistor DT can be avoided, and further, higher dark state data voltage is not required to be set in the driving chip, and the power consumption of the driving chip is saved.

In addition, the pixel circuit of the embodiment includes the first leakage suppression module 140 and the second leakage suppression module 180, so that the gate potential of the driving transistor can be well maintained in the light-emitting stage, and further, the driving currents generated by the driving transistor can be relatively consistent in each light-emitting sub-stage of the light-emitting stage, and the light-emitting brightness of the light-emitting device in each light-emitting sub-stage of the light-emitting stage is further ensured to be consistent, so that the display effect is improved.

The embodiment of the invention also provides a display panel which comprises the pixel circuit of any embodiment of the invention.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A pixel circuit, comprising: the device comprises a driving transistor, a data writing module, a storage module, a first initialization module and a first leakage suppression module;

the first initialization module is used for writing a first initialization voltage to the grid electrode of the driving transistor in an initialization stage; the first initialization module comprises at least two first sub-transistors connected in series, adjacent first sub-transistors are electrically connected through a first intermediate node between the two first sub-transistors, the first leakage suppression module is electrically connected with at least one first intermediate node, and the first leakage suppression module is used for positively and correlatively coupling the grid potential variation of the driving transistor to the first intermediate node connected with the first leakage suppression module;

the data writing module is used for writing the voltage of the data to the grid electrode of the driving transistor in the data writing stage; the storage module is used for storing the grid voltage of the driving transistor;

The control end of the data writing module is connected with a second scanning signal;

the pixel circuit further comprises a first light-emitting control module and a second light-emitting control module, wherein the first light-emitting control module is used for controlling the conduction state between a first power supply voltage input end and a first pole of the driving transistor according to a first light-emitting control signal accessed by a control end of the pixel circuit, the second light-emitting control module is used for controlling the conduction state between a second pole of the driving transistor and a first pole of a light-emitting device according to a second light-emitting control signal accessed by the control end of the pixel circuit, and the second pole of the light-emitting device is connected with the second power supply voltage input end;

the second leakage suppression module comprises a fourth capacitor and a first control transistor;

the grid electrode of the first control transistor is connected with the second scanning signal, the first electrode of the first control transistor is connected with a first fixed voltage, the second electrode of the first control transistor is electrically connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is electrically connected with at least one second intermediate node;

the second leakage suppression module further comprises a second control transistor, wherein the grid electrode of the second control transistor is connected with the first light-emitting control signal or the second light-emitting control signal, the first electrode of the second control transistor is connected with a second fixed voltage, and the second electrode of the second control transistor is electrically connected with the first end of the fourth capacitor; wherein the second fixed voltage is less than the first fixed voltage.

2. The pixel circuit of claim 1, wherein the first leakage suppression module comprises a first capacitor having a first plate electrically connected to the gate of the drive transistor and a second plate electrically connected to at least one of the first intermediate nodes.

3. The pixel circuit of claim 1, wherein in the first initialization module, a channel width to length ratio of the first sub-transistor between the first intermediate node to which the first leakage suppression module is connected and a first end of the first initialization module is smaller than a channel width to length ratio of the first sub-transistor between the first intermediate node to which the first leakage suppression module is connected and a second end of the first initialization module; the first end of the first initialization module is connected to the first initialization voltage, and the second end of the first initialization module is connected to the grid electrode of the driving transistor.

4. A pixel circuit according to claim 3, wherein the channel width of the first sub-transistor between the first intermediate node to which the first leakage rejection module is connected and the first end of the first initialization module is less than or equal to 1.8 microns and the channel length is greater than or equal to 4 microns.

5. The pixel circuit of claim 1, wherein the compensation module is configured to write information including a threshold voltage of the drive transistor to a gate of the drive transistor during a data write phase.

6. The pixel circuit of claim 5, wherein a control terminal of the first initialization module is coupled to a first scan signal, a first terminal of the first initialization module is coupled to a first initialization voltage, and a second terminal of the first initialization module is electrically connected to a gate of the driving transistor.

7. The pixel circuit of claim 6, wherein a first terminal of the data writing module is connected to a data voltage, and a second terminal of the data writing module is electrically connected to a first pole of the driving transistor; the control end of the compensation module is connected to the second scanning signal, the first end of the compensation module is electrically connected with the second pole of the driving transistor, and the second end of the compensation module is electrically connected with the grid electrode of the driving transistor.

8. The pixel circuit of claim 1, wherein the first leakage rejection module comprises a connection line connecting at least one of the second intermediate nodes and at least one of the first intermediate nodes.

9. The pixel circuit according to claim 8, wherein the first leakage suppression module further comprises a second capacitor, one end of the second capacitor is connected to a fixed voltage, and the other end of the second capacitor is electrically connected to the connection line.

10. The pixel circuit of claim 1, further comprising a second leakage suppression module comprising a third capacitor, a first end of the third capacitor being tied to a fixed voltage, a second end of the third capacitor being electrically connected to at least one of the second intermediate nodes.

11. The pixel circuit of claim 10, wherein in the compensation module, a channel width to length ratio of the second sub-transistor between the second intermediate node to which the second leakage suppression module is connected and a second pole of the drive transistor is smaller than a channel width to length ratio of the second sub-transistor between the second intermediate node to which the second leakage suppression module is connected and a gate of the drive transistor.

12. The pixel circuit of claim 11, wherein a channel width of the second sub-transistor between the second intermediate node to which the second leakage suppression module is connected and a second pole of the drive transistor is less than or equal to 1.8 microns, and a channel length of the second sub-transistor between the second intermediate node to which the second leakage suppression module is connected and the second pole of the drive transistor is greater than or equal to 4 microns.

13. The pixel circuit according to claim 1, wherein,

the capacitance value of the fourth capacitor is smaller than that of the storage capacitor included in the storage module.

14. The pixel circuit according to claim 1, wherein the first light emission control module and the second light emission control module are configured to be turned on in a plurality of included light emission sub-phases of a light emission phase, and the driving transistor is configured to drive the light emission module to emit light in the light emission sub-phases;

the pixel circuit further comprises a second initialization module and a third initialization module, wherein a control end of the second initialization module and a control end of the third initialization module are connected with reset control signals, the second initialization module is used for writing second initialization voltages to a first pole of a driving transistor in a plurality of reset sub-phases included in a light-emitting phase, and the third initialization module is used for writing third initialization voltages to a second pole of the driving transistor and a first pole of a light-emitting device in the reset sub-phases, wherein each reset phase corresponds to one light-emitting sub-phase, and the reset sub-phases are before the corresponding light-emitting sub-phases.

15. The pixel circuit of claim 14, wherein a first terminal of the third initialization module is connected to the third initialization voltage, a second terminal of the third initialization module is electrically connected to a first pole of the light emitting device or a second terminal of the third initialization module is electrically connected to a second pole of the driving transistor; wherein the reset control signal overlaps with an active level of the second light emission control signal, the first light emission control signal overlaps with an active level of the second light emission control signal, and the active level of the reset control signal is before the active level of the first light emission control signal.

16. A display panel comprising the pixel circuit of any one of claims 1-15.