CN114003088B - Clock distribution network, chip and electronic equipment - Google Patents
Clock distribution network, chip and electronic equipment Download PDFInfo
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- CN114003088B CN114003088B CN202111329243.6A CN202111329243A CN114003088B CN 114003088 B CN114003088 B CN 114003088B CN 202111329243 A CN202111329243 A CN 202111329243A CN 114003088 B CN114003088 B CN 114003088B
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- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
Abstract
The application provides a clock distribution network, chip and electronic equipment includes: a clock transmission circuit provided between the clock generation circuit and the plurality of loads; wherein, clock transmission circuit includes: a plurality of buffer elements corresponding to the plurality of loads one to one, and a plurality of rectifier circuits corresponding to the plurality of loads one to one; the plurality of buffer elements are sequentially connected in series, and the output end of each buffer element is connected with the input end of the corresponding rectifying circuit; the output end of each rectification circuit is connected with the corresponding load; one end of each of the buffer elements is connected to one end of the first inductor, and the other end of the first inductor is connected to a bias voltage; the clock generating circuit is used for providing an initial clock signal, and the rectifying circuit outputs a control clock signal to a corresponding load based on the voltage output by the corresponding buffer element, so that the network can ensure that the load obtains the same clock signal while reducing power consumption.
Description
Technical Field
The present application relates to the field of electronic technologies, and in particular, to a clock distribution network, a chip, and an electronic device.
Background
Currently, in the field of electronic technology, clock signal synchronization design in circuit design is a very critical factor for the performance and reliability of a circuit, that is, it is generally required in circuit design to ensure that clock signals arrive at clock signal synchronization of each sequential device (e.g., register, flip-flop, latch, etc.) in the circuit.
In the related art, a clock distribution network may be used to adjust a clock signal to ensure that the clock signals received by each sequential device in the clock distribution network are synchronized. In general, the clock distribution network may adopt a cascade structure as shown in fig. 1, and in the clock distribution network of the cascade structure, the clock signals of the respective sequential devices connected to the ends of the nodes in the cascade structure are ensured to be synchronous by arranging the same number of buffer units and the same branch line length on each branch.
However, when the clock distribution network having the cascade structure is adopted, as the number of connected sequential devices increases, the number of buffer units for driving the clock signal in the circuit structure increases, and thus the power consumption of the clock distribution network is large.
Disclosure of Invention
The application provides a clock distribution network, a chip and an electronic device, which are used for solving the problem of larger power consumption of the clock distribution network in the related technology.
In a first aspect, the present application provides a clock distribution network, comprising: a clock transmission circuit provided between the clock generation circuit and the plurality of loads; wherein the clock transmission circuit includes: a plurality of buffer elements corresponding to the plurality of loads one to one, and a plurality of rectifier circuits corresponding to the plurality of loads one to one;
the plurality of buffer elements are sequentially connected in series, and the output end of each buffer element is connected with the input end of the rectifying circuit corresponding to the buffer element; the output end of each rectification circuit is connected with the corresponding load of the rectification circuit; wherein, one end of each of the plurality of buffer elements is connected to one end of the first inductor; the other end of the first inductor is connected to a bias voltage;
the clock generating circuit provides an initial clock signal to the clock transmission circuit, and the rectifying circuit outputs a control clock signal to a corresponding load based on the voltage output by the corresponding buffer element; the output voltages of the plurality of buffer elements are stabilized from an inconsistent state to a consistent state under the resonance effect of the first inductor based on an initial clock signal in a first clock cycle, wherein the first clock cycle comprises a time period between adjacent falling edges and rising edges in the initial clock signal;
the inversion voltages of the plurality of rectification circuits are the same, the inversion voltage is the output voltage of the buffer element in the consistent state at any moment, and the inversion voltage is larger than the minimum output voltage of the buffer element in the first clock cycle and smaller than the minimum output voltage of the buffer element in the inconsistent state.
In some embodiments, the cushioning element comprises: the first inverter and the second inverter are sequentially connected in series; and the grounding end of the second inverter is connected to one end of the first inductor.
In some examples, the second inverter includes: a first switching element and a second switching element; the output end of the first inverter is connected with the control end of the first switch and the control end of the second switch; one end of the first switch is connected with a power supply voltage; the other end of the first switching element is connected with one end of the second switching element and the input end of the rectifying circuit; the ground terminal of the second switch element is the ground terminal of the second inverter, and the ground terminal of the second switch element is connected to one end of the first inductor.
In some examples, the first inverter includes: the power connection end of the third switching element is connected with a power supply; a ground terminal of the fourth switching element is grounded; an output terminal of the clock generation circuit is connected to a control terminal of the third switching element and a control terminal of the fourth switching element; one end of the third switch is connected with one end of the fourth switch, the control end of the first switch and the control end of the second switch.
In some examples, a clock adjustment circuit is disposed between the clock generation circuit and the clock transmission circuit;
the input end of the clock adjusting circuit is connected with the clock generating circuit, the output end of the clock adjusting circuit is connected with the input end of the clock transmission circuit, and the clock adjusting circuit is used for adjusting the pulse width of an initial clock signal generated by the clock generating circuit, so that the time corresponding to the rising edge of the first clock cycle in the initial clock signal after adjustment is within the time period corresponding to the consistent state of the output voltage of each level of buffer element when the first inductor resonates.
In some examples, the rising edge of the first clock cycle corresponds to a time that is within an interval from a rising of the resonant signal waveform of the first inductor to a ground level of the clock distribution network to a first peak point of the resonant signal waveform; or the time corresponding to the rising edge of the first clock cycle is the time when the waveform of the resonance signal reaches the first peak point.
In some examples, the bias voltage has a value of 0.
In some examples, the plurality of buffer elements and the plurality of rectifying circuits are integrally disposed on a substrate, and the plurality of buffer elements are uniformly arranged on the substrate; the distance from the first inductor to the conducting path of the grounding end of the second inverter in each buffer element is equal.
In some examples, the first inductor is an integrated inductor or an external inductor.
In some examples, the rectifier circuit includes a third inverter, an input terminal of the third inverter is connected to the output terminal of the buffer element, and an output terminal of the third inverter is connected to a corresponding load of the rectifier circuit.
In some examples, the third inverter is a low threshold device.
In some examples, the clock generation circuit includes: an AND gate circuit, a feedback circuit; the output end of the AND gate circuit is connected with the input end of the feedback circuit, and the output end of the feedback circuit is connected to the first input end of the AND gate circuit; the feedback circuit is used for outputting a feedback signal with a phase opposite to that of the output signal of the AND gate circuit based on the output signal of the AND gate circuit; the second input end of the AND gate circuit is used for receiving an external control signal; the AND gate circuit outputs an initial clock signal based on the feedback signal and the external control signal.
In some examples, the clock adjustment circuit includes: a delay circuit and a NAND gate circuit; the output end of the delay circuit is connected with the first input end of the NAND gate circuit; the clock generation circuit provides initial clock signals to the delay circuit and the second input end of the NAND gate circuit respectively, and the NAND gate circuit adjusts the pulse width of the initial clock signal generated by the clock generation circuit based on the initial clock signal and the delay signal generated by the delay circuit, so that the time corresponding to the rising edge of the first clock cycle in the initial clock signal after adjustment is within the time period from the first rise of the resonance voltage at the output end of the buffer element to the ground level voltage of the clock distribution network when the resonance of the first inductor occurs and the first peak point of the resonance voltage.
In a second aspect, the present application provides a chip comprising a clock distribution network according to any one of the first aspect.
In a third aspect, the present application provides an electronic device comprising a clock distribution network as defined in any of the first aspects.
The application provides a clock distribution network comprising: a clock transmission circuit provided between the clock generation circuit and the plurality of loads; wherein, clock transmission circuit includes: a plurality of buffer elements corresponding to the plurality of loads one to one, and a plurality of rectifier circuits corresponding to the plurality of loads one to one; the plurality of buffer elements are sequentially connected in series, and the output end of each buffer element is connected with the input end of the corresponding rectifying circuit; the output end of each rectification circuit is connected with the corresponding load; the buffer elements are connected to one end of the first inductor, and the other end of the first inductor is connected to a bias voltage; the clock generating circuit is used for providing an initial clock signal, and the rectifying circuit outputs a control clock signal to a corresponding load based on the voltage output by the corresponding buffer element, so that the network can ensure that the load obtains the same clock signal while reducing power consumption. Compared with the clock distribution network structure in the related art in which each sequential device corresponds to a plurality of buffer units, each load only corresponds to one buffer unit and one rectifying circuit, and the power consumption of the rectifying circuit is low, the clock distribution network structure in the embodiment of the invention can effectively reduce the number of the buffer units, thereby reducing the power consumption required for driving the buffer units.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic structural diagram of a clock distribution network provided in the present application;
fig. 2A is a schematic structural diagram of a clock distribution network according to an embodiment of the present disclosure;
fig. 2B is a schematic structural diagram of another clock distribution network according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram illustrating a variation of a waveform of an operation of a buffer device according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of an equivalent resonant path of a clock transmission network according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of an equivalent resonant path of another clock transmission network according to an embodiment of the present disclosure;
FIG. 6 is a schematic waveform diagram of a resonant signal provided by an embodiment of the present application;
fig. 7 is a schematic structural diagram of another clock distribution network according to an embodiment of the present application;
fig. 8 is a schematic configuration diagram of a clock transmission network according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a clock generation circuit according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of a clock adjusting circuit according to an embodiment of the present disclosure.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
Currently, in circuit design, in order to ensure that each sequential device in a circuit can receive a clock signal of the same length, a clock tree type clock distribution network can be generally adopted.
Fig. 1 is a schematic structural diagram of a clock distribution network according to the present application. The clock distribution network shown in fig. 1 is a conventional cascade structure, in which 4 sequential devices are connected to the last node in the cascade structure, and the initial clock signal generated is received at the first root node in the cascade structure. In addition, the cascade structure further includes a plurality of buffer cells (indicated by triangular symbols in fig. 1), and the buffer cells may be inverters in actual circuit design. In the figure, for each sequential device, the received clock signal is obtained by sequentially driving the initial clock signal through the 3-stage buffer unit, and the lengths of signal paths of the receiving ends of each sequential device and the initial clock signal are the same, so that the sequential signals received by each sequential device are ensured to be the same through the cascade structure, and the sequential devices can work at the same working time.
However, in the clock distribution network with the cascade structure, each sequential device corresponds to multiple stages of buffer units, and as the number of sequential devices in the circuit increases, the number of buffer units required in the corresponding clock distribution network also increases, so that the power consumption of the clock distribution network increases.
The application provides a clock distribution network, a chip and an electronic device, which aim to solve the above technical problems in the prior art.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. These several specific embodiments may be combined with each other below, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 2A is a schematic structural diagram of a clock distribution network according to an embodiment of the present application. As shown in fig. 2A, the clock distribution network provided in the embodiment of the present application includes a clock transmission circuit disposed between a clock generation circuit and a plurality of loads; wherein, clock transmission circuit includes: the load control circuit includes a plurality of buffer elements corresponding to a plurality of loads one to one, and a plurality of rectifier circuits corresponding to a plurality of loads one to one.
The plurality of buffer elements are sequentially connected in series, and the output end of each buffer element is connected with the input end of the rectifying circuit corresponding to the buffer element; the output end of each rectification circuit is connected with the corresponding load of the rectification circuit; wherein, one end of the plurality of buffer elements is connected to one end of the first inductor; the other end of the first inductor is connected to a bias voltage.
The clock generating circuit provides an initial clock signal to the clock transmission circuit, and the rectifying circuit outputs a control clock signal to a corresponding load based on the voltage output by the corresponding buffer element; the output voltages of the plurality of buffer elements are stabilized from an inconsistent state to an consistent state under the resonance effect of the first inductor based on an initial clock signal in a first clock cycle, wherein the first clock cycle comprises a time period between adjacent falling edges and rising edges in the initial clock signal; the initial clock signal starts to keep a low level state from the time when the initial clock signal starts to fall, the initial clock signal does not change from a low level to a high level until a rising edge arrives, and the time period between the falling edge and the rising edge is the time period between the adjacent falling edge and the rising edge.
In the embodiment of the invention, the turnover voltages of the plurality of rectifying circuits are the same, the turnover voltages are output voltages of the buffer elements in a consistent state at any moment, and the turnover voltages are greater than the minimum output voltage of the buffer elements in a first clock cycle and less than the minimum output voltage of the buffer elements in an inconsistent state. When the output voltages of the buffer elements are in an inconsistent state, that is, the output voltage values of the buffer elements are different at the same time (or the difference between the output voltage values of two buffer elements in each buffer element exceeds a preset error range), and when the output voltages of the buffer elements are in a consistent state, that is, the output voltage values of the buffer elements are the same at the same time (or the difference between the output voltage values of any two buffer elements in each buffer element is within the preset error range); the preset error range is a preset range according to a specific application scene. When the voltage value of the signal output by the buffer element is greater than the turning voltage, the signal output by the buffer element can be rectified by the rectifying circuit to obtain a control clock signal, and the rectifying circuit sends the control clock signal to a load connected with the control clock signal.
Illustratively, as shown in fig. 2A, the clock distribution network includes four loads (load 1-load 4), and in order to ensure that the four loads can receive synchronous clock signals, the clock distribution network in the embodiment of the present application further includes a clock generation circuit and a clock transmission circuit. The clock generation circuit is configured to generate an initial clock signal, send the initial clock signal to a clock transmission circuit connected to the clock generation circuit, and send the processed clock signal to each load through processing of the clock transmission circuit, so that each load can receive a synchronous clock signal (that is, the control clock signal), that is, the control clock signal received by each load is obtained after the clock transmission circuit processes the initial clock signal generated by the clock generation circuit. Here, the load may be a sequential device or a circuit or a chip that needs to ensure synchronization of clock signals.
Specifically, in the clock transmission circuit, a plurality of buffer elements are included in series, and an output end of each buffer element is connected to a rectifying circuit corresponding to the buffer element, each rectifying circuit is also correspondingly connected to a load corresponding to the rectifying circuit, wherein a common load may be formed by a sequential device such as a flip-flop or a latch. The rectifying circuit can be used for amplifying and shaping the signal output by the buffer element.
When the clock distribution network actually works, the clock generation circuit may be configured to provide an initial clock signal to the clock transmission circuit, where the common initial clock signal is an on-chip clock signal with a duty ratio of 50%, or the initial clock signal may also adjust parameters (e.g., duty ratio, frequency, pulse width, etc.) of the initial clock signal according to a subsequent circuit.
After the clock transmission circuit receives the initial clock signal, when the initial clock signal is a low-level signal, at this time, the lower-end paths of the buffer elements in the clock transmission circuit are sequentially opened under the action of the low-level signal, and after all the buffer elements are opened, because all the buffer elements are connected with the first inductor, at this time, the first inductor, the parasitic resistance and the parasitic capacitance in the lower-end paths of the buffer elements and the load capacitance of the buffer elements form a resonance path, and then the first inductor charges the load connected with the buffer elements through the lower-end paths of the buffer elements. Then, after the initial clock signal is converted from a low level to a high level, the lower end path of each buffer element is closed, the upper end path is opened, and the load connected to each buffer element can be continuously charged by the bias voltage connected to the corresponding buffer element.
In some examples, each buffer element includes a first inverter and a second inverter, the first inverter and the second inverter are connected in series, a ground terminal of the second inverter is connected to one end of the first inductor, and another end of the first inductor is connected to the bias voltage. The power supply terminal (i.e. Vdd in the figure) of the second inverter is used for receiving an external power supply signal, as shown in fig. 2B, and fig. 2B is a schematic structural diagram of another clock distribution network provided in the embodiment of the present application. In one example, when the buffer element is designed, the first inverter in the buffer element is a small-sized device, for example, an inverter with a small input capacitance, and the second inverter in the buffer element may be a resonant inverter with a large driving capability, so that the input capacitance of the buffer element is ensured to be small and the waveform of the output buffer element can be inverted and shaped at the same time.
On the basis of the clock distribution network structure of fig. 2B, after the clock transmission circuit receives the initial clock signal of the clock generation circuit, the operation principle of the clock transmission circuit is specifically explained with reference to the waveform diagram shown in fig. 3. Fig. 3 is a schematic diagram illustrating a waveform change of an operation of a buffering element according to an embodiment of the present disclosure. In the figure, the square wave signal shown in curve 1 represents the initial clock signal generated by the clock generation circuit. The waveform signals shown in the curve 2 are respectively composed of four waveforms, and the four waveforms respectively represent the timing waveforms output by the buffer elements at each stage in the clock transmission network of the conventional serial structure, wherein compared with the clock transmission network in the embodiment shown in fig. 2B, the ground terminal of the second inverter in each buffer element in the conventional serial structure is directly grounded. The waveform signal shown in the curve 3 is divided into four waveforms, wherein the four waveforms respectively represent the waveforms of the signals output from the output terminals of each stage of the buffer elements (i.e., the buffer elements 1-4) in the clock transmission network in the embodiment shown in fig. 2B.
When the square wave signal in graph 1 is in the first clock cycle as shown in fig. 3, wherein the first clock cycle refers to the time period when the square wave signal is in the adjacent falling edge and rising edge. First, a waveform of a curve 2 corresponding to a clock transmission network having a conventional series structure will be described. When the initial clock signal in the curve 1 is converted from a high level to a low level (i.e. at a falling edge in the figure), in the buffer element 1 connected to the clock generation circuit, the lower end path of the second inverter is turned on (where the lower end path refers to a path between the output end of the second inverter, the ground end of the second inverter, and the ground), and at this time, the energy stored at the output end node of the buffer element 1 may be transferred to the ground connected to the ground end of the second inverter through the lower end of the second inverter, that is, the voltage of the output end node of the buffer element 1 starts to gradually decrease. Then, the lower end paths of the buffer elements 2, 3, and 4 connected in series to the buffer element 1 are sequentially turned on in the order of connection, and then the voltages at the output ends of the buffer elements 2 to 4 start to sequentially decrease. Thereafter, when the rising edge in the curve 1 arrives, the initial clock signal generated by the clock generation circuit is converted from low level to high level, and at this time, the upper end path is opened because the lower end path of the second inverter in the buffer element 1 connected to the clock generation circuit is closed (wherein, the upper end path refers to the path from the power supply signal input end of the second inverter (i.e., the Vdd end of fig. 2B) to the output end of the second inverter). After the upper end path of the second inverter in the buffer element 1 is opened, the energy of the power supply signal connected to the second inverter can be transferred to the output end of the second inverter through the upper end path of the second inverter, that is, the voltage value at the output end of the second inverter starts to gradually rise at this time. The lower end path of each second inverter in the buffer elements 2-4 sequentially connected with the buffer element 1 in series is closed, the upper end path is sequentially opened, and the voltage value of the output end node of each buffer element sequentially starts to rise. As can be seen from the variation diagram of each waveform in curve 2 in fig. 3, when curve 1 is at a rising edge, the voltage values at the output ends of the buffer elements sequentially rise along with time according to the connection sequence, and then are output to the loads corresponding to the buffer elements. Because the voltage values of the output ends of the buffer elements are different at the same moment, the loads cannot simultaneously acquire the target effective edge of the clock signal, and the loads cannot simultaneously work.
Next, a description will be given of a waveform change corresponding to the clock transmission network structure provided in the embodiment of the present application (here, curve 3 is taken as an example). When the initial clock signal in the curve 1 is converted from the high level to the low level (i.e. at the falling edge of the curve 1 in the figure), the buffer element is in a discharging stage, the discharging stage is mainly divided into two stages, and the first stage is a stage in which the lower end paths in the buffer elements at each stage are sequentially conducted. In the buffer element 1 connected to the clock generation circuit in the first stage, the lower end path of the second inverter is turned on (where the lower end path refers to a path between the output end of the second inverter, the ground end of the second inverter, the first inductor, and the bias voltage end connected to the first inductor), and at this time, the energy stored at the output end node of the buffer element 1 may be transferred to the first inductor through the lower end path of the second inverter, that is, the voltage at the output end node of the buffer element 1 starts to decrease gradually. After the lower end paths of the buffer elements 2, 3 and 4 connected in series with the buffer element 1 are sequentially turned on according to the connection sequence, the voltages at the output ends of the buffer elements 2-4 also start to sequentially decrease, that is, the voltages at the output ends of the buffer elements start to sequentially decrease in the first stage, and at the same time, the voltage values at the output ends of the buffer elements are different, that is, the first stage is an inconsistent state of the buffer elements. When the lower end paths of the buffer elements are sequentially opened, it can be considered that the output ends of the buffer elements charge the same inductance device together through the respective lower end paths, and at this time, the voltages at the output ends of the buffer elements are gradually stabilized from the inconsistent state to the consistent state (i.e., the second stage of the discharge process), that is, when the buffer elements are in the consistent state, the voltage values of the output ends of the buffer elements at the same time are the same.
With the increasing of the energy stored in the first inductor, the first inductor forms a resonant path with a parasitic resistance in a lower end path of each buffer element, a parasitic capacitance at each buffer element, and the like under the condition that the lower end path of each buffer element is opened. At this time, an equivalent circuit diagram of the resonance path is shown in fig. 4. Fig. 4 is a schematic diagram of an equivalent resonant path of a clock transmission network according to an embodiment of the present disclosure. The resistor R1 represents an equivalent resistance of the output terminal of the second inverter, the ground terminal of the second inverter, and a parasitic resistor in a conduction path between the ground terminal of the second inverter and the first inductor in the buffer device 1. The capacitor C1 represents an equivalent capacitance of a sum of an output terminal of the second inverter in the buffer device 1, a ground terminal of the second inverter, a parasitic capacitance in a conduction path between the ground terminal of the second inverter and the first inductor, and a load capacitance at an input terminal in the buffer device 2. The resistor R2 and the capacitor C2 are equivalent resistors and equivalent capacitors of the buffer element 2. The resistor R3 and the capacitor C3 are equivalent resistors and equivalent capacitors of the buffer element 3. The resistor R4 and the capacitor C4 are the equivalent resistor and the equivalent capacitor of the buffer element 4, and each of the equivalent resistors R1, R2, R3, and R4 is connected to the same inductor. Based on the schematic diagram of the equivalent resonant path shown in fig. 4, the equivalent resonant path can be further equivalent to the equivalent circuit shown in fig. 5. As shown in fig. 5, fig. 5 is a schematic diagram of an equivalent resonant path of another clock transmission network provided in the embodiment of the present application.
The resistor R = R1| | | R2| | | R3| | | R4, and the capacitor C = C1| | | C2| | C3| | C4, namely the resistor R is a resistance value obtained by connecting the resistor R1, the resistor R2, the resistor R3 and the resistor R4 in parallel; the capacitor C is a capacitance value obtained by connecting the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 in parallel.
Then, the resonant waveform u of the equivalent circuit out Can be expressed as follows:
wherein R is the equivalent resistance, L is the inductance of the first inductor, C is the equivalent capacitance, V dd The value of the voltage for powering the second inverter, t is the resonance time, us is the bias voltage of the first inductor connection, ω 0 Is the resonance angular frequency and ω is the oscillation angular frequency.
In some embodiments, the bias voltage may be 0 or any voltage. When the bias voltage is not equal to 0, the peak value of the oscillating voltage at the time of the resonance of the first inductor can be increased. When the first inductor oscillates, the generated energy may be sequentially connected to the ground terminal of the second inverter and the output terminal of the second inverter through wires and then may be output to the load corresponding to the second inverter to charge the load, that is, at this time, the voltage at the output terminal of the second inverter gradually rises, and at this time, the change curves of the voltages at the output terminals of the second inverter in each buffer element are in a consistent state. As can be seen from the schematic diagram of the variation of each waveform in curve 3 in fig. 3, when curve 1 is at the rising edge, and when the first inductor is in resonant charging, the values of the voltages at the output ends of the buffer elements are the same, so that each load can be ensured to obtain the target effective edge of the clock signal at the same time, and then each load can work at the same time. However, due to the presence of dissipative devices such as parasitic resistances in the resonant circuit, the resonance may cause the highest level of the load in the clock distribution network to rise below the level value required by the clock signal of the load to control it.
When the rising edge in the curve 1 arrives, at this time, the initial clock signal generated by the clock generation circuit is converted from low level to high level, and at this time, the upper end path is opened because the lower end path of the second inverter in the buffer element 1 connected to the clock generation circuit is closed (wherein, the upper end path refers to the path from the power supply signal input end of the second inverter to the output end of the second inverter). After the upper end path of the second inverter in the buffer element 1 is opened, the energy of the power supply signal connected to the second inverter may be transferred to the output end of the second inverter through the upper end path of the second inverter, and the output end of the second inverter continues to supply power to the load corresponding to the second inverter until the power supply reaches the system voltage, that is, the voltage value at the output end of the second inverter continues to gradually increase. The lower end path of each second inverter in the buffer elements 2-4 sequentially connected with the buffer element 1 is closed, the upper end path is sequentially opened, and the voltage value of the output end node of each buffer element continues to sequentially start to rise.
In addition, since the voltage value output by the second inverter needs to be sampled by the rectifying circuits before being input to the corresponding loads, in order to ensure that the loads can obtain the same target effective edge at the same time, it is necessary to ensure that the inversion voltages of the plurality of rectifying circuits are the same, where the inversion voltage has a value range that is an output voltage at any time when the voltages at the output ends of the buffer elements are in a consistent state, and is greater than the minimum output voltage of the buffer elements in the first clock cycle (e.g., point a in fig. 3) and smaller than the minimum output voltage of the buffer elements in an inconsistent state (e.g., point B in fig. 3). Specifically, if the sampling point of the inversion voltage of the rectifying circuit is located at the output end of the buffer element and the voltage is in a non-uniform state, at this time, the time when each waveform in curve 3 in fig. 3 reaches the inversion voltage will be different, and it cannot be ensured that the load connected to the rectifying circuit can receive a synchronous clock signal. Therefore, the value of the inversion voltage needs to be the output voltage at any time when the voltages at the output ends of the buffer elements are in a consistent state. However, in fig. 3, when the voltages at the output ends of the buffer elements are in the consistent state, the voltage value ranges (that is, the value ranges in the direction of the longitudinal axis when several waveforms overlap in the curve 3 in fig. 3) have a coincidence point with the voltage value ranges of several curves in the inconsistent state before the consistent state (that is, in the non-coincidence stage in which the values of several waveforms sequentially decrease at a non-coincidence stage before several waveforms overlap in fig. 3), so that the values of the flipped voltages still need to be smaller than the values at the point B in fig. 3, so as to ensure that the rectifying circuit is flipped at the same time. In addition, the value of the flip voltage needs to be larger than the minimum output voltage of the buffer element in a consistent state, so that the rectifier circuit can work normally.
In this embodiment, compared to the conventional cascade configuration distributed network provided in fig. 1 in which each sequential device corresponds to the same number of buffer elements, the clock distribution network structure in this embodiment can effectively reduce the number of buffer units, thereby reducing the power consumption required for driving the buffer elements and reducing the area occupied by the buffer units in the clock distribution network. In addition, the first inductor is arranged in the embodiment of the invention, when the lower end path of the second inverter in each stage of buffer element is conducted under the condition that the initial clock signal is in a low level state, the first inductor stores a part of energy, and the first inductor can also assist the load to be charged through the lower end path, namely before the load is charged through the upper end path, the load is already charged through the first inductor, so that the power consumption required by charging the load is effectively reduced, the subsequent upper end path of the second inverter only needs to bear a small part of charging task, and meanwhile, the time for supplying power through the external power supply signal is far shorter than the power supply time in the traditional series structure circuit.
In some embodiments, when the actual circuit is designed, the second inverter in the buffer element is formed by connecting the first switch element and the second switch element in series, and the ground terminal of the second switch element is connected to the first inductor; the output end of the first inverter is respectively connected with the control end of the first switching element and the control end of the second switching element; one end of the first switching element is connected with a supply voltage; the other end of the first switch element is connected with one end of the second switch element and the input end of the rectifying circuit respectively. On the basis of the above embodiment, the first inverter in the buffer element may further include a third switching element and a fourth switching element connected in series, where an electrical connection end of the third switching element is externally connected to a power supply; the grounding end of the fourth switching element is grounded; the output end of the clock generation circuit is respectively connected with the control end of the third switching element and the control end of the fourth switching element; one end of the third switching element is connected with one end of the fourth switching element, the control end of the first switching element and the control end of the second switching element respectively.
In some embodiments, since the rising edge arrival time of the input initial clock signal determines the turn-off time of the second switching element in the second inverter, the failure time of the resonant path, and the time for the first switching element to continue to be charged by the external power supply signal after being turned on, the rising edge time of the initial clock signal needs to be matched with the resonant frequency of the resonant waveform of the first inductive resonant signal. Specifically, as shown in fig. 6, fig. 6 is a schematic waveform diagram of a resonant signal provided in the embodiment of the present application. When the rising edge of the initial clock signal is not considered, the waveform of the resonance signal is always in a continuous oscillation phenomenon.
To further reduce the power consumption of the system, the resonance signal waveform in fig. 6 may be divided into 4 regions. The whole area of the waveform of the resonant signal is the area corresponding to the time when the black curve in fig. 6 starts to fall (i.e. the time when the lower end path of the first buffer element is opened and the voltage at the output end of the first buffer element starts to fall) until the subsequent buffer elements are opened, and the curves in fig. 6 coincide and oscillate until the oscillation is finished. The region 1 is an interval when the resonance signal waveform falls to a voltage lowest point, the region 2 is an interval from the resonance signal waveform falling to the voltage lowest point to a resonance signal waveform rising to a ground level (GND) of the clock distribution network, and the region 3 is an interval from the resonance signal waveform rising to the ground level of the clock distribution network to a first peak point of the resonance signal waveform. The remaining section is a section corresponding to the area 4. When the rising edge of the initial clock signal falls in the region 1, since the voltage at the output of the buffer element falls to a lower value and possibly also to the ground level of the clock distribution network under the effect of the first inductive resonance at this time, setting the rising edge of the initial clock signal in the interval 1 will not only not reduce the power consumption of the external supply signal, but will also consume more energy. When the rising edge of the initial clock signal falls in the region 2, although the first inductor starts to charge the load at this time, since the resonant path is turned off too early, at this time, a large amount of energy needs to be consumed for supplementary charging, and when the external power supply signal charges the loads corresponding to the buffer elements of each stage, the clock signals obtained by the loads are still delayed backwards in sequence according to the serial connection sequence in the conventional structure, so that the loads cannot obtain synchronous clock signals. When the rising edge of the initial clock signal falls in the area 4, because the voltage waveform of the output end of the buffer element can generate unpredictable fluctuation in an actual circuit, if the voltage value of a second peak point of the output waveform reaches the turnover voltage of the rectifier circuit, the rectifier circuit can generate mis-sampling at the moment, and the function of the system can not be estimated, wherein the second peak point is the next peak point of the resonant signal waveform after the first peak point. Therefore, it is necessary to set the rising edge time of the initial clock signal in the region 3, and power consumption can be effectively reduced at this time.
In some embodiments, in order to ensure that the time corresponding to the rising edge of the first clock cycle in the initial clock signal is within the period corresponding to the output voltage of each stage of the buffer elements being in the consistent state when the first inductor resonates, a clock adjusting circuit may be disposed between the clock generating circuit and the clock transmitting circuit. As shown in fig. 7, fig. 7 is a schematic structural diagram of another clock distribution network provided in this embodiment of the application, and based on the structure shown in fig. 2B, an input end of a clock adjusting circuit is connected to a clock generating circuit, and an output end of the clock adjusting circuit is connected to an input end of a clock transmitting circuit. The clock adjusting circuit can adjust the pulse width of the initial clock signal output by the clock generating circuit, so that the rising edge time of the adjusted clock signal can be located in a period corresponding to the state that the output voltages of the buffer elements at all levels are consistent when the first inductor resonates, that is, the clock adjusting circuit can generate a clock signal with the pulse width consistent with the resonant period at the edge corresponding to the initial clock signal under the condition that the frequency of the initial clock signal is not changed.
By adopting the technical scheme of the invention, the clock distribution network can work in a variable-frequency and variable-voltage working environment by arranging the clock adjusting circuit, and even if the rising edge moment of the initial clock signal generated by the clock generating circuit is not matched with the resonance period of the subsequent resonance passage, the initial clock signal can fall in the range corresponding to the consistent state of the output voltage of each level of buffer element through the adjustment of the clock adjusting circuit, so that the clock signals received by each level of load are ensured to be synchronous.
In some embodiments, the rising edge of the first clock cycle corresponds to a time in the interval between the rising of the resonant signal waveform of the first inductor to the ground level of the clock distribution network to the first peak point of the resonant signal waveform (i.e., in region 3), which also reduces the power consumption required to charge the load; or the time corresponding to the rising edge of the first clock cycle is the time when the waveform of the resonance signal reaches the first peak point, and at this time, the power consumption of the clock distribution network is the lowest, that is, the power consumption required by the load charging is the lowest.
In some embodiments, during the actual use of the clock distribution network, when the plurality of buffer elements and the plurality of rectifying circuits in the clock distribution network are integrally disposed on the substrate on which the clock distribution network is located (i.e., when the buffer elements and the rectifying circuits in the clock distribution network are disposed on the circuit board), it is necessary to ensure that the plurality of buffer elements are uniformly arranged on the substrate, and it is further necessary to ensure that the electrical distance from the first inductor to the ground terminal conductive path of each buffer element is the same. Furthermore, when the conducting paths are arranged, the sizes of the second switches in the second inverters can be ensured to be consistent, and the conducting wires connected to the inductors are conducting wires of the same specification (namely the thickness and the length of the conducting wires are the same).
When the buffer elements are uniformly arranged, when the number of the buffer elements is small, the buffer elements can be considered to be arranged in a line on the substrate, so that the convenience of wiring when the rectifier circuit and the load corresponding to the rectifier circuit are connected in the following process is facilitated. When the number of the buffer elements is large, it is considered that a plurality of buffer elements are arranged in an array manner, so that the size of the area occupied by the buffer elements matches the size of the substrate.
Specifically, in order to ensure that the distances of the conductive paths are equal, when the positions of the buffer elements are set, the buffer elements may be set in the form of an H-tree structure. As shown in fig. 8, fig. 8 is a schematic diagram of an arrangement structure of a clock transmission network according to an embodiment of the present application. The figure comprises 16 buffering elements, wherein each level of buffering elements are sequentially connected end to end, each level of buffering elements can be provided with a rectifying circuit, the rectifying circuit can be composed of a third phase inverter, the input end of the third phase inverter is connected with the output end of the buffering element, and the output end of the third phase inverter is connected with a load corresponding to the rectifying circuit.
As shown in fig. 8, the 16 buffer elements may be divided into 4 groups, the 4 buffer elements in each group of buffer elements are respectively located at four end points of the H-tree structure, and the buffer elements in each group are also connected together to form an H shape, and then the H-tree structure is connected to the first inductor. In fig. 8, the third inverter in each rectifying circuit may be connected to a load, and the connection relationship between the rectifying circuit corresponding to the first buffer element and the load in the figure may be referred to, and the connection between the rest of the loads and the rectifying circuits is not shown in the figure. Also, the position of the load in the drawings is merely for illustration and is not particularly limited.
In addition, a winding mode can be adopted to ensure that the distances of the conducting paths are equal.
In one example, the first inductor in the clock transmission network may be an integrated inductor or an external inductor. That is, the first inductor may be integrated on the substrate or may be disposed outside the substrate. For example, the first inductor may be a spiral line made of metal as shown in fig. 8, and may be connected to an off-chip inductor device by using a corresponding contact (e.g., bump ball, etc.).
In some embodiments, the third inverter in the rectifying circuit is a low-threshold device, that is, the inverter with the lower threshold voltage is selected as the third inverter, so as to ensure that the inverter has a lower time delay, thereby further ensuring that the time of the effective edge of the clock signal received by each load is the same.
In addition, in the actual circuit design, the number of the series connection of the buffer elements also needs to be considered. When the number of the buffer elements connected in series is large, the resonant frequency of the resonant path is expressed as:
wherein, ω is the resonance frequency, L, C are the inductance and capacitance of the resonance path at resonance, and R is the resistance of the resonance path. When the resistance R is small, the resonance period
As the number of the buffer elements connected in series increases, the load capacitance of each buffer element (i.e., the input capacitance of the first inverter in each buffer element) also increases after being connected in parallel, and when the clock period required by the load in the clock distribution network is not changed, the resonance period is also not changed, and at this time, as the capacitance increases, the inductance for resonance also decreases, and when the relationship among the inductance, the capacitance, and the resistance for resonance does not satisfy the following initial conditions for resonance:
at this time, the whole clock distribution network circuit cannot resonate, and the clock transmission circuit cannot play the roles of reducing power consumption and ensuring that the loads obtain the same clock signal. Therefore, in an actual circuit design, the first inverter in the buffer element can select the inverter with lower input capacitance, thereby increasing the number of the buffer elements which can be connected in series. Moreover, the number of the buffer elements is not large, so that the circuit cannot realize resonance.
In some examples, the clock generation circuit includes: and gate circuit and feedback circuit. The output end of the AND gate circuit is connected with the input end of the feedback circuit, and the output end of the feedback circuit is connected to the first input end of the AND gate circuit. In one example, the feedback circuit is composed of an odd number of inverters connected in series. The feedback circuit is used for outputting a feedback signal with a phase opposite to that of an output signal of the AND gate circuit based on the output signal of the AND gate circuit; the second input end of the AND gate circuit is used for receiving an external control signal; the AND gate circuit outputs an initial clock signal based on the feedback signal and an external control signal.
As shown in fig. 9, fig. 9 is a schematic structural diagram of a clock generation circuit according to an embodiment of the present disclosure. Wherein. The feedback circuit consists of three inverters. When the external control signal input to the second input terminal of the and circuit is at a low level, the voltage output from the output terminal of the and circuit is kept constant at a ground level. When the external control signal input to the second input terminal of the and circuit is at a high level, the and circuit generates an initial clock signal (usually a clock signal with a duty ratio of 50%) according to the feedback signal output by the feedback circuit and the input high-level signal. The period of the initial clock signal is related to the time of the delay of the inverters in the feedback circuit, namely the period of the initial clock signal is 2 times of the total time length of the delay time of each level of inverters in the feedback circuit.
In some examples, a clock adjustment circuit includes: a delay circuit and a NAND gate circuit; the output end of the delay circuit is connected with the first input end of the NAND gate circuit; the clock generating circuit provides initial clock signals to the delay circuit and the second input end of the NAND gate circuit respectively, the NAND gate circuit adjusts the pulse width of the initial clock signals generated by the clock generating circuit based on the initial clock signals and the delay signals generated by the delay circuit, so that the time corresponding to the rising edge of the first clock cycle in the adjusted initial clock signals is positioned in the time period when the resonant voltage at the output end of the buffer element rises to the ground level voltage of the clock distribution network and the resonant voltage reach the first peak point when the resonant voltage of the first inductor resonates.
As shown in fig. 10, fig. 10 is a schematic structural diagram of a clock adjusting circuit according to an embodiment of the present disclosure. The delay circuit can be composed of three inverters, and a clock signal input to the clock adjusting circuit passes through the delay circuit composed of three-level inverters to generate a delay signal which is input to the first input end of the NAND gate circuit. And then, the NAND gate circuit obtains an adjusted clock signal based on the initial clock signal received by the first input end and the delay signal generated by the delay circuit, wherein the frequency of the adjusted clock signal is the same as that of the initial clock signal, and the duty ratio is different. The signal delay time length in the delay circuit can be determined by the number and the size of the inverters connected in series.
The application provides a chip comprising the clock distribution network provided by any one of the above embodiments.
The present application provides an electronic device comprising a clock distribution network as provided in any of the above embodiments.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (15)
1. A clock distribution network, comprising: a clock transmission circuit provided between the clock generation circuit and the plurality of loads; wherein the clock transmission circuit includes: a plurality of buffer elements corresponding to the plurality of loads one to one, and a plurality of rectifier circuits corresponding to the plurality of loads one to one;
the plurality of buffer elements are sequentially connected in series, and the output end of each buffer element is connected with the input end of the rectifying circuit corresponding to the buffer element; the output end of each rectification circuit is connected with the corresponding load of the rectification circuit; wherein, one end of each of the plurality of buffer elements is connected to one end of the first inductor; the other end of the first inductor is connected to a bias voltage;
the clock generation circuit provides an initial clock signal to the clock transmission circuit, and the rectifying circuit outputs a control clock signal to a corresponding load based on the output voltage of the buffer element corresponding to the rectifying circuit; the output voltages of the plurality of buffer elements are stabilized from an inconsistent state to a consistent state under the resonance action of the first inductor based on an initial clock signal in a first clock cycle; the first clock cycle comprises a period between adjacent falling and rising edges in the initial clock signal; the inversion voltages of the plurality of rectification circuits are the same, the inversion voltage is the output voltage of the buffer element in the consistent state at any moment, and the inversion voltage is larger than the minimum output voltage of the buffer element in the first clock cycle and smaller than the minimum output voltage of the buffer element in the inconsistent state.
2. The clock distribution network of claim 1, wherein the buffering element comprises: the first inverter and the second inverter are sequentially connected in series; and the grounding end of the second inverter is connected to one end of the first inductor.
3. The clock distribution network of claim 2, wherein the second inverter comprises: a first switching element and a second switching element; the output end of the first inverter is respectively connected with the control end of the first switching element and the control end of the second switching element; one end of the first switching element is connected with a power supply voltage; the other end of the first switching element is respectively connected with one end of the second switching element and the input end of the rectifying circuit; the ground terminal of the second switch element is the ground terminal of the second inverter, and the ground terminal of the second switch element is connected to one end of the first inductor.
4. The clock distribution network of claim 3, wherein the first inverter comprises: the power connection end of the third switching element is connected with an external power supply; a ground terminal of the fourth switching element is grounded; an output end of the clock generation circuit is connected with a control end of the third switching element and a control end of the fourth switching element respectively; one end of the third switch element is connected with one end of the fourth switch element, the control end of the first switch and the control end of the second switch respectively.
5. The clock distribution network of claim 1, wherein a clock adjustment circuit is disposed between the clock generation circuit and the clock transmission circuit;
the input end of the clock adjusting circuit is connected with the clock generating circuit, the output end of the clock adjusting circuit is connected with the input end of the clock transmission circuit, and the clock adjusting circuit is used for adjusting the pulse width of an initial clock signal generated by the clock generating circuit, so that the time corresponding to the rising edge of the first clock cycle in the initial clock signal after adjustment is within the time period corresponding to the consistent state of the output voltage of each level of buffer element when the first inductor resonates.
6. The clock distribution network of claim 5, wherein the rising edge of the first clock cycle corresponds to a time in an interval from the resonant signal waveform of the first inductor rising to a ground level of the clock distribution network to a first peak point of the resonant signal waveform; or the time corresponding to the rising edge of the first clock cycle is the time when the waveform of the resonance signal reaches the first peak point.
7. The clock distribution network of any of claims 1-6, wherein the bias voltage has a value of 0.
8. The clock distribution network of any one of claims 1-6, wherein the plurality of buffer elements and the plurality of rectifying circuits are integrally disposed on a substrate, and the plurality of buffer elements are uniformly arranged on the substrate; the distance from the first inductor to the conducting path of the grounding end of the second inverter in each buffer element is equal.
9. The clock distribution network of claim 8, wherein the first inductor is an integrated inductor or an external inductor.
10. The clock distribution network according to any of claims 1-6, wherein the rectifying circuit comprises a third inverter, an input of the third inverter is connected to an output of the buffering element, and an output of the third inverter is connected to a corresponding load of the rectifying circuit.
11. The clock distribution network of claim 10, wherein the third inverter is a low threshold device.
12. The clock distribution network of any of claims 1-6, wherein the clock generation circuit comprises: an AND gate circuit, a feedback circuit; the output end of the AND gate circuit is connected with the input end of the feedback circuit, and the output end of the feedback circuit is connected to the first input end of the AND gate circuit; the feedback circuit is used for outputting a feedback signal with a phase opposite to that of the output signal of the AND gate circuit based on the output signal of the AND gate circuit; the second input end of the AND gate circuit is used for receiving an external control signal; the AND gate circuit outputs an initial clock signal based on the feedback signal and the external control signal.
13. The clock distribution network of claim 5, wherein the clock adjustment circuit comprises: a delay circuit and a NAND gate circuit; the output end of the delay circuit is connected with the first input end of the NAND gate circuit; the clock generation circuit provides initial clock signals to the delay circuit and the second input end of the NAND gate circuit respectively, and the NAND gate circuit adjusts the pulse width of the initial clock signal generated by the clock generation circuit based on the initial clock signal and the delay signal generated by the delay circuit, so that the time corresponding to the rising edge of the first clock cycle in the initial clock signal after adjustment is within the time period from the first rise of the resonant voltage at the output end of the buffer element to the first rise of the ground level voltage of the clock distribution network and the first peak point of the resonant voltage when the first inductor resonates.
14. A chip comprising a clock distribution network according to any one of claims 1 to 13.
15. An electronic device comprising a clock distribution network according to any one of claims 1-13.
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| WO2013108350A1 (en) * | 2012-01-20 | 2013-07-25 | パナソニック株式会社 | Delay circuit |
| CN105763193A (en) * | 2016-02-14 | 2016-07-13 | 中国电子科技集团公司第二十四研究所 | Clock circuit used for high-speed high-precision SHA-less pipelined analog-to-digital converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2013108350A1 (en) * | 2012-01-20 | 2013-07-25 | パナソニック株式会社 | Delay circuit |
| CN105763193A (en) * | 2016-02-14 | 2016-07-13 | 中国电子科技集团公司第二十四研究所 | Clock circuit used for high-speed high-precision SHA-less pipelined analog-to-digital converter |
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