CN114003081A - Digital LDO circuit with low-voltage ripple output - Google Patents
Digital LDO circuit with low-voltage ripple output Download PDFInfo
- Publication number
- CN114003081A CN114003081A CN202111267589.8A CN202111267589A CN114003081A CN 114003081 A CN114003081 A CN 114003081A CN 202111267589 A CN202111267589 A CN 202111267589A CN 114003081 A CN114003081 A CN 114003081A
- Authority
- CN
- China
- Prior art keywords
- voltage
- circuit
- voltage ripple
- output
- ripple reduction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
Abstract
The invention belongs to the technical field of digital LDO (low dropout regulator) circuits, and particularly relates to a digital LDO circuit with low-voltage ripple output, which comprises: the circuit comprises a clock comparator, a bidirectional shift register, a switch array, a voltage ripple reduction circuit and a mode control circuit for controlling the switch of the voltage ripple reduction circuit; the parallel output end of the bidirectional shift register is connected with the input end of the voltage ripple reduction circuit; the output end of the voltage ripple reduction circuit is connected with the switch array; the mode control circuit is used for controlling the voltage ripple reduction circuit to be started when a signal that the resistance sent by the load is not changed is received; the turned-on voltage ripple reduction circuit is used for keeping the switching state of each switch in the switch array at the turning-on moment and latching the input voltage from each output end in the parallel output ends to the switch array. The invention uses the additional circuit to stop the change of the switch array in the digital LDO, so that the change is approximately a constant current source, and when the load is stable, the voltage ripple can be completely eliminated.
Description
Technical Field
The invention belongs to the technical field of digital LDO circuits, and particularly relates to a digital LDO circuit with low voltage ripple output.
Background
With the advent of digital LDO, its advantages have gradually attracted attention. The digital LDO has the advantages of good low-voltage working characteristics, high precision, stable output, process variability and the like, so that the digital LDO is widely applied to a high-efficiency power management system with low input voltage and high precision.
The traditional digital LDO consists of a comparator, a bidirectional shift register and a PMOS switch array. The clock comparator is used for comparing the output voltage VOUT with the reference voltage VREF, and providing a comparison result to the bidirectional shift register to control the shift direction of the register. The bidirectional shift register controls the conducting number of the PMOS switch array, and plays a role in adjusting output voltage. The switch array is composed of PMOS tubes with the same size, and the switched-on switch tubes work in a linear region under normal work to realize the low-voltage working characteristic of the digital LDO.
Traditional digital LDO can produce the sawtooth wave in the output signal under steady state, and the ripple can lead to the voltage unstability, influences the normal work of device. In order to solve the problem of voltage ripple, the ripple is generally reduced at the voltage output end by adding a capacitor on the basis of the conventional digital LDO structure. The scheme can reduce the amplitude of ripples and has simple structure. However, the disadvantages of this way of reducing voltage ripple are: first, implementing the capacitor on a chip requires a large area and introduces additional power consumption. Secondly, the traditional structure can only reduce the voltage ripple, and the effect is not obvious when the capacitor area is limited, and the voltage ripple can not be eliminated completely.
Disclosure of Invention
Aiming at the defects and the improvement requirements of the prior art, the invention provides a digital LDO circuit with low voltage ripple output, and aims to solve the technical problems that a larger on-chip area is needed and the effect is not obvious when the voltage ripple is reduced by adding a capacitor at a load end in the traditional digital LDO.
To achieve the above object, according to an aspect of the present invention, there is provided a digital LDO circuit having a low voltage ripple output, including: the circuit comprises a clock comparator, a bidirectional shift register, a switch array, a voltage ripple reduction circuit and a mode control circuit for controlling the switch of the voltage ripple reduction circuit;
the negative input end of the clock comparator is used for inputting reference voltage, the positive input end of the clock comparator is used for inputting output voltage of the LDO circuit, and the output end of the clock comparator is used for being connected with the input end of the bidirectional shift register; the parallel output end of the bidirectional shift register is connected with the input end of the voltage ripple reduction circuit; the output end of the voltage ripple reduction circuit is connected with the switch array;
the mode control circuit is used for controlling the voltage ripple reduction circuit to be started when a signal that the resistance sent by the load is not changed is received; the turned-on voltage ripple reduction circuit is used for keeping the switching state of each switch in the switch array at the turning-on moment and latching the input voltage from each output end in the parallel output ends to the switch array.
Further, the mode control circuit is further configured to control the voltage ripple reduction circuit to turn off when receiving a signal that resistance sent by the load changes, and the turned-off voltage ripple reduction circuit does not control the parallel output terminal to input a signal to the switch array.
Further, the voltage ripple reduction circuit includes latches of the same number as the output ports of the bidirectional shift register; the input ends of the latches are respectively connected with the parallel output ports of the bidirectional shift register in a one-to-one correspondence mode, the output ends of the latches are respectively connected with the switches in the switch array in a one-to-one correspondence mode, and the control ends of the latches are uniformly connected to the output end of the mode control circuit.
Further, the mode control circuit comprises two voltage comparators with different reference fixed voltages and an exclusive-or gate; the input voltage of one voltage comparator is the output voltage of the digital LDO circuit and the fixed voltage higher than the reference voltage of the digital LDO circuit respectively, and the input voltage of the other voltage comparator is the output voltage of the digital LDO circuit and the fixed voltage lower than the reference voltage of the digital LDO circuit respectively; and the exclusive-OR gate is used for receiving the output results of the two voltage comparators and outputting a switch control signal to the voltage ripple reduction circuit.
Further, the two voltage comparators perform comparison work when the resistance changes and does not change.
Further, the exclusive-or gate is further configured to receive a signal sent by a load, and input a start control signal to the voltage ripple reduction circuit when the signal sent by the load and sent by which the resistance does not change is received and the output result meets a preset voltage ripple size. The predetermined voltage ripple is a value within a ripple range after the ripple tends to be stable (i.e., the normal sawtooth ripple).
The invention also provides a voltage ripple reduction method of the digital LDO circuit, which comprises the following steps:
the adopted digital LDO circuit comprises: the clock comparator, the bidirectional shift register and the switch array; a voltage ripple reduction circuit and a mode control circuit for controlling the switch of the voltage ripple reduction circuit are configured; the parallel output end of the bidirectional shift register is connected with the input end of the voltage ripple reduction circuit; the output end of the voltage ripple reduction circuit is connected with the switch array; the mode control circuit controls the voltage ripple reduction circuit to be started when receiving a signal that the resistance sent by the load is not changed; the voltage ripple reduction circuit is started to keep the switch state of each switch in the switch array at the starting time, and the input voltage of each output end in the parallel output ends to the switch array is latched, so that the voltage ripple of the digital LDO circuit is reduced.
Further, the mode control circuit controls the voltage ripple reduction circuit to be turned off when receiving a signal that the resistance sent by the load changes, and the turned-off voltage ripple reduction circuit does not control the parallel output end to input a signal to the switch array.
Further, the mode control circuit comprises two voltage comparators with different reference fixed voltages and an exclusive-or gate; the input voltage of one voltage comparator is the output voltage of the digital LDO circuit and the fixed voltage higher than the reference voltage of the digital LDO circuit respectively, and the input voltage of the other voltage comparator is the output voltage of the digital LDO circuit and the fixed voltage lower than the reference voltage of the digital LDO circuit respectively; the exclusive-or gate is used for receiving output results of the two voltage comparators and outputting a switch control signal to the voltage ripple reduction circuit; the two voltage comparators carry out comparison work when the resistance is changed or not changed;
the mode control circuit controls the voltage ripple reduction circuit to be started, and specifically comprises: the exclusive-or gate is further used for receiving a signal sent by a load, and inputting a starting control signal to the voltage ripple reduction circuit when the signal sent by the load and the output result meet a preset voltage ripple size are received.
Generally, by the above technical solution conceived by the present invention, the following beneficial effects can be obtained:
(1) according to the invention, a voltage ripple reduction circuit and a mode control circuit are configured in a traditional digital LDO circuit, and the mode control circuit controls the voltage ripple reduction circuit to be started when receiving a signal that the resistance sent by a load is not changed; the started voltage ripple reduction circuit is used for keeping the switching state of each switch in the switch array at the starting moment (namely the voltage ripple reduction circuit can stop the switching change of the digital LDO switch array), and latches the input voltage of each output end in the parallel output end to the switch array, so that the voltage ripple can be thoroughly eliminated at the moment.
(2) The mode control circuit controls the voltage ripple reduction circuit to be switched off when receiving a signal that the resistance sent by the load changes, the switched-off voltage ripple reduction circuit does not interfere the parallel output end and the normal work of the switch array, the traditional LDO circuit works normally at the moment, and the circuit still produces large ripples when the load resistance changes so as to adapt to the change of the load resistance. Therefore, the circuit of the invention can lower the voltage ripple of the LDO circuit as a whole by looking at the load change and the change conditions.
(3) The circuit is simple in structure, does not need extra area on a chip, can obtain good capability of reducing voltage ripple, but has higher requirement on the load of the LDO.
Drawings
Fig. 1 is a schematic structural diagram of a digital LDO circuit for reducing voltage ripples according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an exemplary digital LDO circuit;
FIG. 3 is a schematic diagram of a shift register in a digital LDO circuit according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an operation of a shift register according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a clock comparator in a digital LDO circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a mode control circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a voltage ripple reduction circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example one
As shown in fig. 1, a digital LDO circuit for reducing voltage ripple includes: the digital LDO circuit L1 is connected with the voltage ripple reduction circuit L3; the mode control circuit is used for controlling the voltage ripple reduction circuit to be started when a signal that the resistance sent by the load is not changed is received; the turned-on voltage ripple reduction circuit is used for keeping the switching state of each switch in the switch array at the turning-on moment and latching the input voltage from each output end in the parallel output ends to the switch array.
The present embodiment uses additional circuitry to stop the change of the switch array in the digital LDO to make it approximate a constant current source. Thus, when the load is stable, the voltage ripple can be completely eliminated. This embodiment may be used to power a load that remains constant for a period of time, such as a circuit that goes into a sleep mode but is not powered down. In addition, the scheme of the embodiment can also reduce the power consumption of the digital LDO in operation and prolong the service time of the digital LDO circuit. The main principle is to reduce the switching times of the MOS tube array and the switching loss of the MOS tube, thereby reducing the power consumption and prolonging the service life.
(1) Principle for voltage ripple reduction
The reference voltage is an ideal output voltage of the digital LDO circuit, and the degree of deviation between the output voltage and the reference voltage determines what state the digital LDO circuit is in at the next time.
The mode control circuit L2 is substantially used to adjust the system operation mode according to the current output voltage (the operation mode includes the normal operation mode of the LDO or the operation mode in which the voltage ripple reduction circuit intervenes to reduce the ripple), when the output voltage has a large ripple (indicating that the resistance changes), the digital LDO circuit can enter the normal conventional adjustment state to adjust the output voltage to be near the reference value quickly; when the output voltage is stabilized near the reference value, the digital LDO circuit may enter a stable state, and at this time, the mode control circuit L2 and the voltage ripple reduction circuit L3 intervene to cancel the ripple of the output voltage.
(2) About digital LDO circuit body
The digital LDO circuit body comprises a clock comparator, a bidirectional shift register and a switch array which are connected in sequence; the negative input end of the clock comparator is used for inputting reference voltage, and the positive input end of the clock comparator is used for inputting output voltage; the switch array is connected with the voltage ripple reduction circuit. Preferably, the switch array is a PMOS transistor switch array. Preferably, the PMOS transistor switch array comprises a plurality of PMOS transistors connected in parallel.
Specifically, as shown in fig. 2, the digital LDO circuit body includes a clock comparator, a bidirectional shift register, and a switch array. The clock comparator is used for outputting the voltage VOUTAnd a reference voltage VREFComparing and providing the comparison result Compout to the bidirectional shift registerThe sel terminal of (1). The bidirectional shift register is composed of an alternative data selector and a D trigger to form a basic unit, an address input end sel of the data selector controls the shifting direction, and when sel is equal to 1, the shift register shifts to the right; when sel is 0, the shift register moves to left, the shift register can only control the on or off of one PMOS tube in one clock period, and the output Q [0: n ] of the shift register]The number of conducting tubes in the switch array is determined, and the function of regulating the output voltage is achieved. Switch array MP [0: n]Composed of PMOS tubes with same size, and the gates PG [0: n ] of the PMOS tubes in the switch array]And the output end Q [0: n ] of the bidirectional shift register]And connecting, wherein under normal work, the conducted switching tube works in a linear region, and the low-voltage working characteristic of the digital LDO is realized.
The working principle of the shift register is as follows: most of shift registers in the digital LDO circuit adopt an alternative data selector and a D edge trigger as basic units. The working principle of the D edge trigger is as follows: the output signal Q depends on the state of the rising edge coming time D; the specific operation principle of the data selector, which determines the shift condition of the register by selecting the high and low levels of the input signal of the port, can be described as follows in conjunction with fig. 3 and 4:
first, all the shift register outputs are set to 1, so that the register controlled transistors are turned off before the valid clock signal comes.
② the 1 end of the lowest bit and the 0 end of the highest bit are respectively Grounded (GND) and power supply (VDD), which is the basic connection condition of the shift register.
When the first valid clock signal Clk arrives, Q0 is 0, and the outputs Q1, Q2, Q3, Q4, Qn …, Qn 1 of the remaining shift registers; when the second valid clock signal Clk comes, Q0-Q1-0, and the outputs Q2-Q3-Q4-Qn … -Qn-1, … … of the remaining shift registers, and when the nth valid clock signal Clk comes, the outputs of the n-bit shift registers are all 0.
When the first valid clock signal reaches zero after all the transistors are turned on, i.e., when all the outputs of the shift register are 0, Qn is 1, Qn-1 is Qn-2 is … … is Q2 is Q1 is 0. When the second valid clock signal comes, Qn-1 is 1, and the outputs Qn-2, … …, Q2, Q1 are 0, … … of the rest of the shift registers, until when the nth valid clock signal comes, all the outputs of the shift registers are 1.
In summary, the following steps: macroscopically, the operating principle of the shift register is that when Compout is 1, every time an effective clock signal comes, in the clock period, the shift register moves one bit to the right, and a port with one bit output of 0 is added, so that the turned-on power tube in the one-bit power array can be added. When Compout is equal to 0, every time an active clock signal comes, the shift register is shifted to the left by one bit, so that the port of the shift register with 1 output is increased, and the conducting power tube in one power array can be turned off. For an n-bit shift register, when all output ends are 1, n effective clock signals are needed to set all output ends to be 0; similarly, on the premise that all the output terminals are 0, n clock signals are also needed to set all the output terminals of the shift register to 1. From the above analysis of the operating principle of the shift register and the operation of the 8-bit shift register described in fig. 4, it can be known that: within an effective clock range, the shift register either moves one bit to the right or one bit to the left, so that within one clock cycle, the shift register only controls the on or off of one power tube.
Referring to fig. 5, the working principle of the clock comparator is as follows: (1) vOUT>VREFWhen clk is 0, A, B point is charged, raising the voltage at A, B point. When CLK is 1, the discharge starts at A, B two points, but the discharge speed is different due to the difference between the gate voltages of the two MOS transistors, and the discharge speed at a point is higher than that at B point. After the voltage at point a is rapidly changed to a low voltage, Compout becomes 0 after passing through the latch. (2) VOUT<VREFWhen clk is 0, point A, B starts charging, and the voltage at these two points rises. When clk is 1, the discharge starts at point A, B, but at this time, the discharge rate at point B is greater than that at point a, and after passing through the latch, CompOUT is 1.
In summary, the control mechanism of the digital LDO circuit is: with reference to the schematic block diagram of fig. 2, when the output voltage vout > vref, the output signal Compout of the clocked comparator is equal to 0, and at this time, the shift register moves to the left by one bit, and the number of conductive transistors in the switch array controlled by the shift register is decreased by one, so that the output voltage vout becomes smaller; when the output voltage vout is smaller than vref, the output signal Compout of the clocked comparator is equal to 1, and at this time, the shift register moves one bit to the right, and the number of the turned-on transistors in the switch array is increased by one, so that the output voltage is increased, and the purpose of voltage stabilization is achieved.
(3) The mode control circuit comprises two voltage comparators with different reference voltages and an exclusive-OR gate. The input voltage of one of the voltage comparators is the output voltage of the digital LDO and a fixed voltage higher than the reference voltage of the digital LDO, and the input voltage of the other voltage comparator is the output voltage of the digital LDO and a fixed voltage lower than the reference voltage of the digital LDO. The input end of the exclusive-OR gate is the output result of the two voltage comparators and outputs a control signal.
Specifically, as shown in fig. 6, the mode control circuit comprises two voltage comparators for detecting the output voltage V of the digital LDO voltage in real timeOUTAnd generating a control signal according to the detection result through an exclusive-or gate, thereby controlling whether the voltage ripple reduction circuit operates. Let the input voltages of the two voltage comparators be Vref+And Vout，Vref-And VoutWhen V isref+>Vout>Vref-The input of the exclusive or gate is 0, 1. The output is 1 and the voltage ripple reduction circuit is started.
The voltage ripple reduction circuit includes the same number of latches as the output ports of the bidirectional shift register. The input end of each latch is respectively connected with the output end of the bidirectional shift register, the output end of each latch is connected with the switch array, and the control end of each latch is uniformly connected with the output end of the mode control circuit.
Specifically, as shown in fig. 7, the operating principle of the voltage ripple reduction circuit is as follows: when the mode control circuit outputs a low level signal, the latch transmits an output signal of the bidirectional shift register to the switch array, and the digital LDO works normally. When the mode control circuit outputs a high level signal, the latch stops transmitting the output signal of the bidirectional shift register to the switch array, and the switch array keeps the current state and becomes a constant current source. When the load is not changed, the voltage ripple can be completely eliminated.
Example two
The difference from the first embodiment is the condition that the voltage ripple reduction circuit is turned on.
The control signal finally output by the mode control circuit is jointly determined by the following parts: a load change signal provided by the load, a voltage ripple detection circuit (voltage comparator) consisting of the circuit shown in fig. 6, and an and gate. The input ends of the AND gates are respectively connected with a load change signal O1 provided by the load and an output signal O2 of the voltage ripple detection circuit, and the output ends of the AND gates are used as the integral output of the mode control circuit. If and only if both are 1, the mode control circuit outputs a high level and starts the ripple reduction circuit. The load change signal O1 provided by the load should be set to 0 when the load changes. The voltage ripple detection circuit is responsible for comparing the output voltage Vout of the LDO with two reference voltages Vref +, Vref-. The output signal O2 of the voltage ripple detection circuit will be set to 1 if and only if Vref + > Vout > Vref-. When the load changes, the load change signal O1 is set to 0, turning off the ripple reduction circuit. After a period of time, when the voltage ripple detection circuit detects that the output voltage will reach a relatively stable state again, the ripple reduction circuit is started again at this time to thoroughly eliminate the ripple.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A digital LDO circuit having a low voltage ripple output, comprising: the circuit comprises a clock comparator, a bidirectional shift register, a switch array, a voltage ripple reduction circuit and a mode control circuit for controlling the switch of the voltage ripple reduction circuit;
the negative input end of the clock comparator is used for inputting reference voltage, the positive input end of the clock comparator is used for inputting output voltage of the LDO circuit, and the output end of the clock comparator is used for being connected with the input end of the bidirectional shift register; the parallel output end of the bidirectional shift register is connected with the input end of the voltage ripple reduction circuit; the output end of the voltage ripple reduction circuit is connected with the switch array;
the mode control circuit is used for controlling the voltage ripple reduction circuit to be started when a signal that the resistance sent by the load is not changed is received; the turned-on voltage ripple reduction circuit is used for keeping the switching state of each switch in the switch array at the turning-on moment and latching the input voltage of each output end in the parallel output ends to the switch array.
2. The digital LDO circuit with low voltage ripple output of claim 1, wherein the mode control circuit is further configured to control the voltage ripple reduction circuit to turn off when receiving a signal sent by a load and having a changed resistance, and the voltage ripple reduction circuit that is turned off does not control the parallel output terminal to input a signal to the switch array.
3. The digital LDO circuit with low voltage ripple output of claim 1, wherein the voltage ripple reduction circuit comprises the same number of latches as the output port of the bidirectional shift register; the input ends of the latches are respectively connected with the parallel output ports of the bidirectional shift register in a one-to-one correspondence mode, the output ends of the latches are respectively connected with the switches in the switch array in a one-to-one correspondence mode, and the control ends of the latches are uniformly connected to the output end of the mode control circuit.
4. The digital LDO circuit with low voltage ripple output of claim 1, wherein the mode control circuit comprises two voltage comparators with different employed reference fixed voltages and an XOR gate; the input voltage of one voltage comparator is the output voltage of the digital LDO circuit and the fixed voltage higher than the reference voltage of the digital LDO circuit respectively, and the input voltage of the other voltage comparator is the output voltage of the digital LDO circuit and the fixed voltage lower than the reference voltage of the digital LDO circuit respectively; and the exclusive-OR gate is used for receiving the output results of the two voltage comparators and outputting a switch control signal to the voltage ripple reduction circuit.
5. The digital LDO circuit with low voltage ripple output of claim 4, wherein said two voltage comparators perform comparison operation when the resistance is changed and not changed.
6. The digital LDO circuit with low voltage ripple output of claim 5, wherein the XOR gate is further configured to receive a signal sent by a load, and input a turn-on control signal to the voltage ripple reduction circuit when the signal sent by the load with unchanged resistance is received and the output result satisfies a preset voltage ripple magnitude.
7. A method for reducing voltage ripple of a digital LDO circuit, comprising:
the adopted digital LDO circuit comprises: the clock comparator, the bidirectional shift register and the switch array; a voltage ripple reduction circuit and a mode control circuit for controlling the switch of the voltage ripple reduction circuit are configured; the parallel output end of the bidirectional shift register is connected with the input end of the voltage ripple reduction circuit; the output end of the voltage ripple reduction circuit is connected with the switch array; the mode control circuit controls the voltage ripple reduction circuit to be started when receiving a signal that the resistance sent by the load is not changed; the voltage ripple reduction circuit is started to keep the switching state of each switch in the switch array at the starting time, and latches the input voltage of each output end in the parallel output ends to the switch array, so that the voltage ripple of the digital LDO circuit is reduced.
8. The method of claim 7, wherein the mode control circuit controls the voltage ripple reduction circuit to turn off when receiving a signal sent by a load and having a changed resistance, and the voltage ripple reduction circuit that is turned off does not control the parallel output terminal to input a signal to the switch array.
9. The method of claim 7, wherein the mode control circuit comprises two voltage comparators with different reference fixed voltages and an exclusive-or gate; the input voltage of one voltage comparator is the output voltage of the digital LDO circuit and the fixed voltage higher than the reference voltage of the digital LDO circuit respectively, and the input voltage of the other voltage comparator is the output voltage of the digital LDO circuit and the fixed voltage lower than the reference voltage of the digital LDO circuit respectively; the exclusive-or gate is used for receiving output results of the two voltage comparators and outputting a switch control signal to the voltage ripple reduction circuit; the two voltage comparators carry out comparison work when the resistance is changed or not changed;
the mode control circuit controls the voltage ripple reduction circuit to be started, and specifically comprises: the exclusive-or gate is further used for receiving a signal sent by a load, and inputting a starting control signal to the voltage ripple reduction circuit when the signal sent by the load and the output result meet a preset voltage ripple size are received.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111267589.8A CN114003081B (en) | 2021-10-29 | 2021-10-29 | Digital LDO circuit with low-voltage ripple output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111267589.8A CN114003081B (en) | 2021-10-29 | 2021-10-29 | Digital LDO circuit with low-voltage ripple output |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114003081A true CN114003081A (en) | 2022-02-01 |
| CN114003081B CN114003081B (en) | 2022-07-05 |
Family
ID=79924845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111267589.8A Active CN114003081B (en) | 2021-10-29 | 2021-10-29 | Digital LDO circuit with low-voltage ripple output |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114003081B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115097889A (en) * | 2022-06-28 | 2022-09-23 | 清华大学 | Digital low dropout linear voltage stabilizing circuit and method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109597455A (en) * | 2018-11-22 | 2019-04-09 | 西安电子科技大学 | A kind of number low-dropout regulator |
| CN109871059A (en) * | 2019-02-25 | 2019-06-11 | 华中科技大学 | A kind of ultra low voltage LDO circuit |
| CN112034925A (en) * | 2020-09-29 | 2020-12-04 | 广东工业大学 | Digital LDO circuit for reducing limit loop oscillation |
| US20210232166A1 (en) * | 2018-09-04 | 2021-07-29 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Digital Voltage Regulator and Method of Regulating Voltage |
| CN113300599A (en) * | 2021-05-25 | 2021-08-24 | 杭州雄迈集成电路技术股份有限公司 | On-chip direct current voltage-stabilizing source circuit |
-
2021
- 2021-10-29 CN CN202111267589.8A patent/CN114003081B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210232166A1 (en) * | 2018-09-04 | 2021-07-29 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Digital Voltage Regulator and Method of Regulating Voltage |
| CN109597455A (en) * | 2018-11-22 | 2019-04-09 | 西安电子科技大学 | A kind of number low-dropout regulator |
| CN109871059A (en) * | 2019-02-25 | 2019-06-11 | 华中科技大学 | A kind of ultra low voltage LDO circuit |
| CN112034925A (en) * | 2020-09-29 | 2020-12-04 | 广东工业大学 | Digital LDO circuit for reducing limit loop oscillation |
| CN113300599A (en) * | 2021-05-25 | 2021-08-24 | 杭州雄迈集成电路技术股份有限公司 | On-chip direct current voltage-stabilizing source circuit |
Non-Patent Citations (2)
| Title |
|---|
| SAURABH CHAUBEY ET AL.: "Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators", 《2019 IEEE 62ND INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)》 * |
| 杨阳等: "一种低电压低静态电流LDO的电路设计", 《现代电子技术》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115097889A (en) * | 2022-06-28 | 2022-09-23 | 清华大学 | Digital low dropout linear voltage stabilizing circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114003081B (en) | 2022-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4972517A (en) | Driver circuit receiving input voltage and providing corresponding output voltage | |
| JP2017126339A (en) | Reference voltage circuit | |
| US20060255781A1 (en) | Constant voltage power supply | |
| CN114003081B (en) | Digital LDO circuit with low-voltage ripple output | |
| KR100334363B1 (en) | Power supply apparatus | |
| CN113568467A (en) | Parallel low dropout regulator | |
| CN109412408B (en) | Charge pump circuit and load driving method thereof | |
| CN113359921A (en) | Linear voltage regulator with fast transient response operation capability | |
| CN113285591B (en) | Circuit, chip and method for equalizing output current of two power supply chips | |
| CN112034925A (en) | Digital LDO circuit for reducing limit loop oscillation | |
| US20030098680A1 (en) | Power supply device and electric appliance employing the same | |
| CN109765959B (en) | Low dropout voltage stabilizing circuit based on time digital sampling | |
| WO2022134452A1 (en) | Voltage stabilization module and electronic apparatus | |
| CN214125566U (en) | LED dimming circuit, LED driving system and electronic equipment | |
| US6680685B2 (en) | Chopper analog-to-digital converter with power saving mode | |
| CN114094660A (en) | Linear charging system with high-voltage turn-off function | |
| US10437276B2 (en) | Heat dissipation circuit and regulator control circuit including the same | |
| CN113093851A (en) | Low dropout voltage regulator circuit based on fuzzy PI control and time-to-digital conversion | |
| Yuan et al. | A 225-mA binary searching digital LDO with transient enhancement | |
| CN114860017B (en) | LDO circuit, control method, chip and electronic equipment | |
| CN111786561A (en) | Synchronous rectification control circuit, control method and switching power supply | |
| CN116094313B (en) | Power supply device | |
| US11881863B2 (en) | Comparator circuit | |
| CN114928233A (en) | Drive circuit and drive method for switching element | |
| CN114253331B (en) | Transient enhanced digital LDO circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |