CN113994346A

CN113994346A - Scalable integrated circuit with synapse electronics and CMOS integrated memory resistors

Info

Publication number: CN113994346A
Application number: CN202080041609.7A
Authority: CN
Inventors: 乔斯·克鲁兹-阿尔布雷克特; 蒂莫西·德罗西耶; 纳拉扬·斯里尼瓦萨
Original assignee: HRL Laboratories LLC
Current assignee: HRL Laboratories LLC
Priority date: 2019-06-20
Filing date: 2020-06-16
Publication date: 2022-01-28
Also published as: EP3987452A1; EP3987452A4; WO2020257168A1

Abstract

The reconfigurable neural circuit includes an array of processing nodes. Each processing node includes: a single physical neuron circuit having only one input and output; a single physical synaptic circuit having a presynaptic input; and a single physical output coupled to an input of the neuron circuit; a weight memory to store N synaptic conductance values or have weights coupled to outputs of the single physical synaptic electrical circuit; a single physical Spike Timing Dependent Plasticity (STDP) circuit having an output coupled to the weight memory; a first input coupled to an output of the neuron circuit; and a second input coupled to the presynaptic input; and an interconnect circuit connected to the presynaptic input and to an output of the single physical neuron circuit. Both the synapse circuit and the STDP circuit are time division multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

Description

Scalable integrated circuit with synapse electronics and CMOS integrated memory resistors

Cross Reference to Related Applications

This application relates to and claims priority from U.S. patent application No. 16/447,210 filed on day 6/20 in 2019, which is a partial continuation of U.S. patent application No. 14/453,154 filed on day 6/8 in 2014, and to and claims priority from U.S. provisional application No. 61/890,166 filed on day 11/10 in 2013, and priority from U.S. provisional application No. 61/890,790 filed on day 14/10 in 2013, which are incorporated herein as if fully set forth. The present application also pertains to U.S. application No. 13/415,812 filed on 3/8/2012, U.S. application No. 13/535,114 filed on 6/27/2012, and U.S. patent application No. 13/679,727 filed on 11/16/2012, which are incorporated herein as if fully set forth.

Statement regarding federally funded

The invention was made under U.S. government contract HR 0011-09-C-0001. The U.S. government has certain rights in this invention.

Technical Field

The present disclosure relates to neural networks.

Background

An exemplary neural circuit is given in prior art reference [1] listed below. However, in reference [1], the neuron does not have spikes, nor does it have spike-time dependent plasticity (STDP). Furthermore, neurons can only communicate locally.

In prior art reference [2] listed below, spiking neurons and synapses with STDP are shown. However, these circuits are not connected to each other, and reference [2] does not have any interconnection structure. In the prior art reference [3] listed below, a memory resistor array integrated with CMOS is shown. However, no neural circuit, synapse, STDP, or interconnect structure is used in reference [3 ].

Neural circuits consisting of memory resistor based neurons and synapses are described in the prior art references [4] listed below. However, in this circuit, the connection is not programmable. Furthermore, in reference [4], the neurons are located only at the periphery of the synaptic array, so the number of neurons scales linearly with the horizontal or vertical dimension of the integrated circuit.

Reference to the literature

[1] Cruz et al, "16 x16 cellular neural network chip: first complete monolithic dynamic computer array with distributed memory and grayscale input and output, analog integrated circuit and signal processing, Vol.15, No. 3, p.227-

[2] j.m.cruz-Albrecht, m.yung and n.srinivasa, "energy-saving neuron, synapse and STDP integrated circuits", IEEE Trans biomedical circuitry, vol.6, phase 3, p.246-.

[3] Kuk-Hwan Kim, Siddharth Gaba, Dana Wheeler, Jose M.Cruz-Albrecht, Tahir Hussain, Narayan Srinivasa, and Wei Lu entitled "functional hybrid memory resistor crossbar array/CMOS System for data storage and neuromorphic applications", nanometer Kuk, Vol.12, No. 1, p.395, p.1, 11 p.2012.

[4] Jo S H, Chang T, Ebong I, Bhadviya B B, Mazumder P and Lu W "Nanomre resistor devices as synapses in neuromorphic systems"; nanometer Kuckman, 101297-.

[5] Minkovich et al, "time division multiplexing reconfigurable hardware programmed with scalable neuromorphic compiler", "IEEE neural network and learning systems affairs", Vol.23, No. 6, pp.889-.

What is needed is an improved neural network having neural circuits, synaptic circuits, and spike timing dependent plasticity circuits. Embodiments of the present disclosure answer these and other needs.

Disclosure of Invention

In a first embodiment disclosed herein, an array comprises a plurality of processing nodes, wherein each processing node comprises: a single physical neuron circuit having only one input and having an output; a single physical synapse circuit having a presynaptic input and having a single physical output coupled to only one input of the single physical neuron circuit; a weight memory to store N synaptic conductance values or weights, the weight memory having an output coupled to the single physical synaptic electrical circuit, wherein N is an integer greater than 1; a single physical Spike Timing Dependent Plasticity (STDP) circuit having an output coupled to an input of the weight memory; a first input coupled to an output of the single physical neuron circuit; and a second input coupled to the presynaptic input; and an interconnect circuit connected to the presynaptic input and to an output of the single physical neuron circuit, wherein only one input of the single physical neuron circuit is connected only to an output of the single physical synapse circuit, wherein the single physical synapse circuit is time division multiplexed to implement N virtual synapse circuits, and wherein the single physical STDP circuit is time division multiplexed to implement N virtual STDP circuits, and wherein the interconnect circuit in each respective processing node in the array is coupled to the interconnect circuit in each other processing node in the array.

In another embodiment disclosed herein, a method of providing an array includes a plurality of processing nodes, wherein each processing node includes: a single physical neuron circuit having only one input and having an output; a single physical synapse circuit having a presynaptic input and having a single physical output coupled to only one input of the single physical neuron circuit; a weight memory to store N synaptic conductance values or weights, the weight memory having an output coupled to the single physical synaptic electrical circuit, wherein N is an integer greater than 1; a single physical Spike Timing Dependent Plasticity (STDP) circuit having an output coupled to an input of the weight memory; a first input coupled to an output of the single physical neuron circuit; and a second input coupled to the presynaptic input; and an interconnect circuit connected to the presynaptic input and to an output of the single physical neuron circuit, wherein only one input of the single physical neuron circuit is connected only to an output of the single physical synapse circuit, wherein the single physical synapse circuit is time division multiplexed to implement N virtual synapse circuits, and wherein the single physical STDP circuit is time division multiplexed to implement N virtual STDP circuits, and wherein the interconnect circuit in each respective processing node in the array is coupled to the interconnect circuit in each other processing node in the array.

These and other features and advantages will become more apparent from the following detailed description and the accompanying drawings. In the drawings and the description, reference numerals indicate various features, and like numerals indicate like features throughout the drawings and the description.

Drawings

FIG. 1A shows a diagram of a reconfigurable neural network having an array of processing nodes, and FIG. 1B shows a diagram of processing nodes having a processing core, a memristor memory, and an interconnect fabric, according to the present disclosure;

FIG. 2A illustrates components of a processing core of a node according to the present disclosure, and illustrates interactions between neuron circuits, synapse circuits, Spike Timing Dependency Plasticity (STDP) circuits, and weight memories;

FIG. 2B illustrates an example array of processing nodes, and shows each processing node having a single physical neuron circuit, a single physical synapse circuit, a single physical STDP circuit, a weight memory, a connectivity memory, and interconnect circuits in accordance with the present disclosure;

FIG. 3 illustrates one embodiment of a neuron according to the present disclosure;

FIGS. 4A and 4B illustrate timing diagrams for time division multiplexing according to the present disclosure;

FIG. 5A shows a diagram of a memristor array within one processing node with row and column access circuitry, FIG. 5B shows circuitry connected to rows of the memristor array, FIG. 5C shows circuitry connected to columns of the memristor array, FIG. 5D shows an example of a typical I-V characteristic of the memristor, and FIG. 5E shows a typical value of the memristor current when the bias is at 0.4V, and corresponds to a synaptic weight code according to the present disclosure;

FIG. 6A shows an interconnect structure of one processing node, FIG. 6B shows a switch with on/off control, FIG. 6C shows a bidirectional switch with control, and FIG. 6D shows details of a memory for storing connectivity control according to the present disclosure;

FIG. 7A shows a simulated example of a neural network having outputs of a single time-shared synaptic circuit represented by synaptic outputs 1-16 connected to a neuron circuit, and FIG. 7B shows a memory having 16 rows corresponding to time slots disposed in an interconnect structure and 34 columns corresponding to switches, where black represents an OFF (OFF) state and white represents an ON (ON) state, according to the present disclosure;

FIG. 8A shows, at the top of FIG. 8A, time-shared synaptic spikes input to the neuron circuit, and neuron circuit outputs located at the bottom of FIG. 8A, and FIG. 8B shows example synaptic conductance values coupled to a single synapse circuit over time, in accordance with the present disclosure;

FIG. 9A shows voltage waveforms for a memory resistor read operation, and FIG. 9B shows current waveforms for a memory resistor read operation according to the present disclosure;

FIG. 10A shows voltage waveforms for a memristor write operation, and FIG. 10B shows current waveforms for a memristor write operation according to the present disclosure;

FIG. 11A shows a neural network with 10 neurons and 16 synapses, FIG. 11B shows a snapshot of switch states stored in memory for the network, where 16 rows correspond to time slots, 34 columns correspond to switches set in an interconnect structure for each neuron type, where black represents an OFF state, white represents an ON state, FIG. 11C shows a simulation of the output neuron C in FIG. 11A, and FIG. 11D shows synaptic conductance values for 16 synapses over time, and shows convergence to the correct state, in accordance with the present disclosure; and is

FIG. 12A illustrates a simulation of pre-synaptic inputs for the 16 synapses in FIG. 11A, FIG. 12B illustrates a post-synaptic spike produced by the output neuron C of FIG. 11A, and FIG. 12C illustrates weights for the 16 synapses in FIG. 11A during a 3-second test in accordance with the present disclosure.

Detailed Description

In the following description, numerous specific details are set forth to provide a thorough description of various specific embodiments disclosed herein. However, it will be understood by those skilled in the art that the present invention may be practiced without all of the specific details discussed below. In other instances, well-known features have not been described in order not to obscure the present invention.

In the present disclosure, scalable neuromorphic integrated circuits with spiking neurons, synapses and Spike Timing Dependent Plasticity (STDP) are described, where the connection between neurons and synapses is not fixed, but rather can be programmed. The synapses, the STDP circuit, and the interconnection paths between neurons and synapses are time division multiplexed. The integrated circuit includes a memory that stores synaptic weights and interconnect routing information. The circuit includes a CMOS circuit that implements a high density memory resistor memory and write and read memory resistors.

The structure of each node in the array is composed of a neuron circuit, a time division multiplexing synapse circuit, a time division multiplexing STDP circuit, a weight memory, a time division multiplexing programmable interconnect structure, and a connectivity memory for controlling the interconnect structure.

An object of the present disclosure is a reconfigurable integrated circuit with an array of nodes that can implement spiking neural circuits and dynamics of synapses with spiking timing dependent plasticity. An advantage of the integrated circuit of the present disclosure is the ability to scale to high densities, while having the flexibility to be able to implement different neural networks with different topologies.

Fig. 1A shows a top level diagram of a reconfigurable neural circuit 10 having an array 14 of processing nodes 12. The array 14 is a two-dimensional array and may be a square array. In FIG. 1A, an example array 14 of 10x10 processing nodes 12 is shown. Larger arrays can be built and integrated circuits with arrays of 24x24 nodes are realized using 90nm CMOS technology.

The processing nodes 12 are arranged in a two-dimensional array 14. This arrangement allows the number of nodes 12 to be proportional to the area of the integrated circuit. As the length of the horizontal or vertical edges of the integrated circuit increases, the number of nodes 12 increases by the square of the length.

In FIG. 1B, a diagram of a processing node 12 is shown. The processing node 12 has a processing core 20, the processing core 20 having a single physical neuron circuit 22 (which may be an integrated and firing neuron circuit), a single physical synapse circuit 24, a single physical STDP (spike-timing dependent plasticity) element 26, a memory 28 for storing synaptic weights, and a memory 30 for storing interconnect routing connectivity. The

memories

28 and 30 may be CMOS. The STDP element 26 is an adaptation element or circuit that adjusts the weight or gain of the synapse 24 in accordance with a biologically inspired Spike Timing Dependent Plasticity (STDP) learning rule.

Processing node 12 may include a memristor memory 32. As shown in fig. 2A and 2B, the memory resistor memory 32 has a memory resistor array 34 of memory resistors 35, a DAC/DeMUX (digital-to-analog converter/demultiplexer) circuit 33, and an ADC/MUX (analog-to-digital converter/multiplexer) circuit 36. The memristor memory 32 may be used to store synaptic weights. In one example embodiment, there may be 128 memristors per node. As shown in fig. 2A and 2B, the memory 28 in the processing core 20 may also store synaptic weights.

Processing nodes 12 also include interconnect circuitry or fabric 38, shown in fig. 1B and 6A, for enabling communication between processing nodes 12. The interconnect circuitry 38 in each processing node is coupled to a presynaptic input 40 in each other processing node 12 and to an output 42 of the single physical neuron circuit 22 in each other processing node 12. The interconnect structure 38 may also be used to provide connections between the neuron circuit 22, the synapse circuit 24 and the STDP circuit 26 in each processing node, as shown in fig. 6A.

Interconnect structure 38 is comprised of wire segment 83 and switches 84 and 85 shown in fig. 6A. As shown in fig. 6A, the switches 84 of the interconnect structure 38 may provide connections between the neuron circuit 22, the synapse circuit 24 and the STDP circuit 26 in the processing node.

The

switches

84 and 85 are controlled by connectivity settings stored in the memory 30 of the processing core 20.

The array of nodes 12 in the reconfigurable neural circuit 10 is modular and each node 12 may be directly adjacent to its neighboring node 12. All processing nodes 12 have the same processing core 20, the same memristor memory 32, and the same interconnect structure 38. However, the operation of each node 12 may be programmed independently. Each node 12 may be programmed to support communication between nodes 12 in the array of nodes 14 that are both close and far apart.

FIG. 2A shows a diagram illustrating the interaction between the neuron circuit 22 (which may be an integrated and firing neuron circuit), the synapse circuit 24, the STDP circuit 26 and the

memristor memory

32 or 28. Each node 12 has a neuron circuit 22, each node has a synapse circuit, each node has an STDP circuit, and a

memristor memory

32 or 28. Shown in fig. 3 is an integrating and firing type neuron circuit 22 that integrates input 25, shown in fig. 2A and 2B, in an internal pressure accumulator 48. When the integrated value reaches a threshold set by the value of addressing memory resistor 35, neuron 22 resets accumulator 48 back to zero and generates an output spike.

The processing core 20 of each node 12 has only a single physical neuron circuit 22, a single physical synapse circuit 24 and a single physical STDP circuit 26. The single physical synapse circuit 24 has a single physical output 25 connected to an input of the single physical neuron circuit 22. As shown in FIG. 2A, a single physical neuron circuit 22 in a node has only one physical input 25 connected to only a single physical synapse circuit 24 in the node.

A single physical synapse circuit 24 may be implemented in a variety of ways, and one way is that of reference [2] above]The synaptic electrical circuit shown in FIG. 3b, reference [2]]Incorporated herein by reference, and which shows synapses with presynaptic inputs and weights w. The boundaries of the single physical synapse circuit 24 are the same as the portion of the synapse within the circle of FIG. 3b, having the Vpre input and i_sOutput and w-weights, and the synaptic cores shown in fig. 5a and 5 b. The synapses of FIG. 3b are not time-shared. In the present disclosure, a single physical synapse circuit 24 is time-multiplexed to implement N virtual synapse circuits, which reduces the amount of circuitry required, which may be CMOS circuitry. Having a single physical synapse circuit 24 in a node 12 also reduces the number of required interconnections in the node 12. The single physical STDP circuit 26 in the node 12 may be implemented in a variety of ways, and one way is that of reference [2]]The STDP circuit shown in figure 5 b. The boundaries of the single physical synapse circuit 24 are the same as the portions of fig. 5a and 5b showing the STDP circuit with Vpre and Vpost inputs and w outputs to the synapse core. When the weights are read from the memristor memory 32 or memory 28, the synapses 24 are time-multiplexed to implement N virtual synapses. Thus, the output 42 of the neuron 22 changes at each time interval, and hence the input to the STDP circuit also changes at each time interval, so that one physical STDP circuit is time-multiplexed to implement N virtual STDPs, which reduces the number of circuits required and also reduces the required interconnections in the node 12The number of the cells. The memory for storing synaptic weights stores N synaptic weights, the number of which is the same as the number N of virtual synaptic circuits and virtual STDP circuits. Synaptic weights that implement the N virtual synaptic circuits may be stored in either the memristor memory 32 or the memory 28. In one example embodiment, N may be 128.

With continued reference to fig. 2A, the single physical STDP circuit 26 has two inputs, one input being a presynaptic input 40, and a second input being fed back from a post-synaptic output 42 of the single physical neuron circuit 22. The output 44 of the STDP circuit 26 is used to access synaptic weights 46 from either the memristor memory 32 or from the memory 28. The synaptic weights 46 are connected to the single physical synaptic electrical circuit 24, as shown in FIG. 2A.

Fig. 2B shows an example array of processing nodes 12 having a two-dimensional array of 9 processing nodes 12 arranged in a 3x3 array. The size of the array and the number of processing nodes in the array may be any size and number. FIG. 2B shows that each processing node 12 has a single physical neuron circuit 22, a single physical synapse circuit 24, a single physical STDP circuit 26, a weight memory 37, a connectivity memory 30, and interconnect circuitry 38. The weight memory 37 may be the memory resistor memory 32 or the memory 28. Interconnect circuitry 38 in node 12 is connected to interconnect circuitry in all other nodes 12 as shown in fig. 2B.

Fig. 3 illustrates an embodiment of the neuron circuit 22 in the processing core 20. In this embodiment, the neuron circuit 22 is a digital circuit. The inputs 52 shown in FIGS. 2A and 2B illustrate multiple virtual synaptic inputs to a neuron from a single physical synaptic electrical circuit 24. Each virtual synapse input is digital and the output of accumulator 48 is a count. When the accumulator 48 count reaches a threshold, the comparator 50 outputs a spike on line 51 and resets the accumulator 48. In one embodiment, the spike may be a 1-bit digital signal. The accumulator 48 integrates an input 52, which input 52 may be the output of one or more virtual synapse circuits 24, which virtual synapse circuits 24 may be implemented by a single physical synapse circuit 24 time multiplexed, a single physical output 25 of which single physical synapse circuit 24 is connected to a single physical neuron circuit 22, as shown in fig. 2A and 2B. The comparator 50 compares the state of the accumulator 48 with a threshold voltage Vth 54, which may be digital. If the state of the accumulator 48 is greater than Vth 54, the comparator 50 generates an output spike and resets the state of the accumulator 48. For example, the state of accumulator 48 may be reset to a count corresponding to 0 volts. The accumulator 48 may be a 9-position accumulator.

Other neuron circuits may also be used in the processing core. Another neuron implementation that may be used is shown in fig. 6A in U.S. patent application 13/679,727, filed on 11, 16, 2012, which is incorporated herein as if fully set forth.

Fig. 4A and 4B show timing diagrams of synaptic time division multiplexing. This time division multiplexing of Synapses (STM) may be performed by dividing the time consumed in a given STM cycle 56 (which is the time required to cycle through the N virtual synapse circuits and the N virtual STDP circuits) into slots 58, which in one example, slots 58 may be 100 μ s in duration, each slot for a total cycle time of up to N x 100 μ s in duration.

In one embodiment, during each 100 μ s time slot 58, synapse circuitry 24 is assigned to perform the functions of a given virtual synapse and a virtual STDP. In one example, N may be 128, so during a 12.8ms cycle corresponding to 128 slots 58, the synapse 24 may implement 128 different virtual synapses and STDP. Time-division multiplexing requires that each virtual synapse store one synaptic conductance. For example, the storage may be provided by a memory resistor array 34 of 12 memory resistors 35 of 8. In each time slot, one memristor 35 is read to access the synaptic synapse conductance. Further, in each time slot 58, the synaptic weight value stored in each memristor 35 in the memristor array 34 may be updated according to the update value provided by the STDP circuit 26. The updated value is used to increase or decrease the synaptic conductance value of the virtual synapse currently stored in the memristor 35. The memristors 35 may be accessed in a fixed order. During a time slot 58 of an STM cycle 56, the corresponding memristor 35 corresponding to the virtual synapse may be accessed once for reading and, if necessary, once for writing to increment or decrement the currently stored synaptic conductance value by an updated value.

Synaptic weights or conductance values may be stored in memory 28 or memristor memory 32 with 3-bit precision. In one embodiment, the memory 28 may be made of CMOS flip-flops, SRAM (static random access memory), or any other type of digital memory.

The array of memory resistors 34 of each node 12 is connected to circuitry, which may be CMOS, to select the memory resistor 35 for a read or write operation. A symbolic diagram of the memristor array 34 is shown in fig. 5A, and 128 memristors 35 are shown, with

nanowires

60 and 61 arranged in 16 rows and 8 columns, respectively. In this embodiment, there are 16 row vias 62 and 8 column vias 63 to connect the

nanowires

60 and 61 to row circuitry 64 and column circuitry 66, respectively. The row circuit 64 and the column circuit 66 are used to select one of the memristors 35 of the memristor array 34 to perform a read operation or a write operation at any one of the time slots 58.

Fig. 5B shows a diagram of row circuit 64, with row circuit 64 having buffer amplifiers 70, analog-to-digital converters (ADCs) 72, and demultiplexers (DeMUX) 74. The row address is input to the DeMUX 74 to connect the output Vsel _ row 71 of the buffer amplifier 70 to one of the row vias 62 connected to the memory resistor nanowire 60. The other 15 unselected nanowires 60 may be connected to a bias voltage 76.

To read the memristor value from the memristor 35, a buffer amplifier 70 is used to set the read voltage on Vsel _ row 71. The amplifier 70 has an additional terminal 73 which provides a current equal to the current flowing to the memory resistor. This current, proportional to the value stored in the memristor, is digitized by an analog-to-digital converter 72 to produce the synaptic weight or synaptic conductance value 46, which may be a 3-bit (8-level) code. Synaptic weights or synaptic conductance values 46 are applied to the synapses 24, as shown in FIGS. 2A and 2B.

FIG. 5C shows a diagram of a column circuit 66, the column circuit 66 having a demultiplexer (DeMUX)78, the demultiplexer 78 connecting Vsel _ col 79 to one of the column vias 63 connected to the memory resistor nanowires 61 according to a column address 80, as shown in FIG. 5A. The other unselected nanowires are connected to other bias voltages, such as bias voltage 81. These bias voltages are used to minimize leakage paths. Typical I-V characteristics of the memristor 35 are shown in FIG. 5D, and typical current levels during a 0.4V memristor read operation are shown in FIG. 5E.

The output spike signals generated by the neuron circuits 22 in the processing nodes 12 may be routed through the interconnect structure 38 to the synapse circuits 24 of the different nodes 12, which are shown in detail in fig. 6A, 6B and 6C.

Fig. 6A shows details of the interconnect structure or interconnect circuitry 38 associated with one node 12. Interconnect structure 38 is comprised of conductors or wires 83, unidirectional buffer based switch 84, bidirectional buffer based switch 85, and memory 30. The memory 30 stores connectivity data used by the interconnect fabric. In one embodiment, the memory is implemented using CMOS technology. The on or off state of each of the

switches

84 and 85 is stored in the memory 30. All nodes 12 have the same hardware, but the switch states can be programmed independently in each node 12 for each slot 58 of an STM cycle 56. The one-way switch 84 may be implemented by a buffer 84 as shown in fig. 6B. The buffer 84 may be turned on or off according to a control line 86. Details of the bi-directional switch 85 are shown in fig. 6C. The switch consists of two buffers, but only one of the two buffers is set to conduct at a given time, and the state of the bidirectional switch 85 is controlled by two control lines 87. The memory 30 within the node 12 contains information about the control (on or off) of all the

switches

84, 85. For all slots 58 in an STM cycle 56, all switch states of a node 12 may be the same for each STM cycle 56. Thus, the memory 30 need only store the switch states of all slots of one STM cycle, which is the time required to cycle through the N virtual synapses.

The memory 30 stores the interconnect or routing configuration for all slots of an STM cycle as shown in figure 6D. In one embodiment, memory 30 has 34 columns and N rows per node. The data in one column of the memory 30 is used to generate the control signals for the particular switch for all N time slots. The memory 30 is initialized with a user-defined network topology. A neuromorphic compiler may be used to initialize the memory. An example of a compiler is described in the above reference [5], which is incorporated herein by reference.

The reconfigurable neural circuit 10 may be programmed to implement different neural networks. Two simulations are described below. In each case of simulation, the integrated circuit implements a particular neural network topology.

The neural network in the first simulation shown in fig. 7A is composed of

neurons

22 and 16 synapses 24. The weight of each synapse is controlled internally by the STDP circuit 26. The network of fig. 7A can distinguish whether its several inputs are related to each other.

The simulation to implement the network of fig. 7A begins by setting the switch states in the nodes to initialize the memory 30 to route spikes between neurons, as shown in fig. 7B. The graph in fig. 7B shows the contents of the memory 30 using the same format as shown in fig. 6D. FIG. 7B shows the memory as an array of bits. The column is associated with a particular switch of the node. A row is associated with a time slot. In the graph of fig. 7B, the size of the memory 30 is 34 rows, each row having 16 bits. In this example, bits having a value of "0" are shown in black, and bits having a value of "1" are shown in white.

The top curve in FIG. 8A shows the input provided to synapse 24 in the form of a spike string. A set of eight different input spike trains that are not correlated with each other are applied to the synapses 9 to 16. An additional spike, e.g. In FIG. 8A_1-8Shown as serving as a common input to synapses 1 to 8. In this simulation, synapses 1-8 receive identical inputs, fully correlated with each other. As described above, the network may be used to determine which inputs are or are not related to each other. The circuit of the present invention can implement different neural networks (having different topologies) that can be used for different applications. To illustrate and simulate the operation of a circuit, as a first example, we have implemented a neural network that can be used to distinguish between applications where correlated inputs are to uncorrelated inputs. The circuit of the present invention may also implement other neural networks for other applications.

The bottom graph in fig. 8A shows the output produced by the neuron 22 shown in fig. 7A during the simulation. The STDP circuit 24 uses the presynaptic input 40 and the neuron output 42 to generate updates to the synaptic conductance values. In this simulation, there are 16 synaptic conductance weights stored in 16 memristors. The time evolution of the 16 synaptic conductance weights, denoted as w, is shown in FIG. 8B_1,1To w_1,16. Memory resistors M stored in a node_1,1To M _1,1635, respectively. During the cycle 56, the node's memory resistor is accessed cyclically for each time slot 58. Each access operation includes a memristor read, a weight increment or decrement calculated by the STDP circuitry, and a memristor write to update the synaptic conductance weight in the memristor. Writing is performed only when there is a change other than a zero increment or decrement.

One memory resistor 35 of node 12 is accessed once during the 100 mus time slot 58. During the 1.6ms STM cycle 56, all 16 memristors 35 of node 12 are accessed once. The graph in fig. 8B shows a simulation of the weights for 0.3 second operation. In this simulation, 187 access operations were performed on average on each of the 16 memory resistors.

The vertical axis of the graph in FIG. 8B represents the code of the synaptic conductance value 46. This code is generated by the ADC 72 shown in fig. 5B, ranging from 0 to 7, with a step size of 1. It can be observed from the simulation that after 0.3 seconds, the synaptic conductance value w associated with the synapse 24 receiving the relevant input_1,1To w_1,8Tend to be high. Weights w associated with synapses 24 receiving unrelated inputs_1,9To w_1,16Tend to be low, which is the desired behavior.

Details of a single memristor 35 read operation during this simulation are shown in fig. 9A and 9B. The waveform in fig. 9A is labeled P100 and represents the voltage applied to the positive terminal of the memory resistor 35 and is 0.4V in this simulation, however, this voltage could also be programmed to a different value. The line labeled N102 represents the voltage applied to the negative terminal of the memristor 35. During a read operation, it is zero. The control signals, as shown in FIG. 9A, enable the operation of the ADC circuitry 72 to digitize the current of the memristor into one of eight possible synaptic conductance codes 46. In a typical embodiment, the read operation lasts 4 μ s. The current through the memory resistor 35 during a read operation is shown in FIG. 9B. In typical embodiments, the current ranges from 2 μ A to 16 μ A during a read operation.

Details of a typical write operation during simulation are shown in fig. 10A and 10B. The write operation is used to increment or decrement the value of the memristor 35 by an update value. STDP 26 calculates the required increase or decrease in synaptic weight. It then applies a pulse or a set of pulses to one of the two terminals of the memristor in proportion to the magnitude of the change in synaptic conductance.

For incremental changes in synaptic conductance, a pulse is applied to the positive terminal of the memristor 35. The critical voltages for a write operation are shown in FIG. 10A. The waveform labeled P104 represents the voltage applied to the positive terminal of the memristor 35. In this simulation, the write voltage used was 1.4 volts, however, the voltage could also be programmed to different values. The line labeled N106 represents the voltage applied to the negative terminal of the memristor 35. During a read operation, it is approximately zero. The dashed line 108 represents a control signal for setting the duration of the write pulse. To write an increment to a synaptic weight, from 1 to 4 write pulses are applied.

The number of pulses is determined by on-chip control circuitry that reads the memory resistor current just after each write pulse. When the target increment value is reached, the set of pulses is stopped. In the example of fig. 10A, the target increment is achieved after two write pulses. The current through the memory resistor 35 during the write sequence is shown in FIG. 10B. During each write pulse, a current of about 100 μ s may flow through the memory resistor 35. The read current measured in the 4 mus interval after each write pulse is in the desired range of 2 muA to 16 muA. For the decrement operation, a similar process occurs when a pulse is applied to the negative terminal of the memory resistor 35.

A simulation of a reconfigurable neural circuit 10 implementing a more complex network with 10 neurons 22 is shown in fig. 11A. The simulation has an additional layer of 9 neurons 22 located between the input 90 and the output neuron 92, the output neuron 92 having an output 93. The functional behavior of the network is similar to the simulation described above in that the network can distinguish between relevant inputs and irrelevant inputs.

The memory 30 is initialized as shown in fig. 11B. The switch state in each node 12 is set as shown in FIG. 11B and is used to route spikes between individual neurons in the network during each STM cycle 56. After each STM cycle is completed, the process repeats from the beginning. The output 93 of neuron 92 is shown in FIG. 11C. The time evolution of the 16 synaptic weights, denoted as w, is shown in FIG. 11D_1,1To w_1,16. Memory resistor M with weight stored in node 12_1,1To M _1,1635, respectively. In one embodiment of the invention, these memristors are part of an 8 × 16 memristor array shown in FIG. 5A. It can be observed that the weight w associated with the synapse receiving the relevant input is about 0.8 seconds later_1,1To w_1,8Tend to be high. Weights w associated with synapses receiving unrelated inputs_1,9To w_1,16Tend to be low, which is the desired behavior.

An integrated circuit implementing the reconfigurable neural circuit 10 is fabricated and tested. The reconfigurable neural circuit 10 is configured to implement the same network as shown in fig. 11A, which can distinguish whether several input signals are related to each other as described.

The synaptic weights are stored in memory 28. In the network, there are 16 synapses 24 between input neurons 22 and output neurons 92. The graph of FIG. 12A shows the presynaptic input for these 16 synapses. The eight inputs to the synapse are identical and therefore related to each other. The other 8 inputs to other synapses are uncorrelated with each other. The graph of fig. 12B shows a post-synaptic spike produced by output neuron 92. FIG. 12C is a graph showing the weights of 16 synapses during a 3 second test. At the end of the test, the weights are spread to a high or low value. Weights that reach high values correspond to synapses receiving the relevant inputs as needed. Weights that reach low values correspond to synapses receiving unrelated inputs, as desired.

Having described the invention as required by the patent statutes, those skilled in the art will understand how to make changes and modifications to the invention to meet the specific requirements or conditions thereof. Such changes and modifications can be made without departing from the scope and spirit of the present invention as disclosed herein.

The foregoing detailed description of exemplary and preferred embodiments has been presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive or to limit the invention to the precise form described, but rather to enable one skilled in the art to understand how the invention may be adapted for particular uses or implementations. Modifications and variations will be apparent to those skilled in the art. Descriptions of exemplary embodiments that may have tolerances, feature sizes, specific operating conditions, engineering specifications, etc., are not intended to be limiting and may vary from implementation to implementation or from modification to the prior art and no limitation should be implied therefrom. The applicant has carried out the present disclosure with respect to the prior art, but also considers improvements and modifications in the future may take these improvements into account, i.e. in accordance with the prior art of the prior art. The scope of the invention is defined by the claims, which are written and applicable equivalents. Reference to claim elements in the singular does not mean "one and only one" unless explicitly so stated. Furthermore, no element, component, or method or process step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the claims. No claim element herein should be construed as being as specified in 35u.s.c. section 112, paragraph six, unless the element is explicitly recited using the phrase "means.." and no method or process step in this document should be construed as being dependent on such specification unless the step or steps explicitly recite "including step … below.

Broadly, the present application discloses at least the following: the reconfigurable neural circuit includes an array of processing nodes. Each processing node includes: a single physical neuron circuit having only one input and output; a single physical synaptic circuit having a presynaptic input; a single physical output coupled to an input of the neuron circuit; a weight memory to store N synaptic conductance values or have weights coupled to outputs of the single physical synaptic electrical circuit; a single physical Spike Timing Dependent Plasticity (STDP) circuit having an output coupled to the weight memory; a first input coupled to an output of the neuron circuit; and a second input coupled to the presynaptic input; and an interconnect circuit connected to the presynaptic input and to an output of the single physical neuron circuit. Both the synapse circuit and the STDP circuit are time division multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

Concept

At least the following concepts have been disclosed.

Concept 1. a reconfigurable neural circuit, comprising: an array comprising a plurality of processing nodes; wherein each processing node comprises:

a single physical neuron circuit having only one input and having an output;

a single physical synapse circuit having a presynaptic input and a single physical output coupled to only one input of the single physical neuron circuit;

a weight memory to store N synaptic conductance values or weights, the weight memory having an output coupled to the single physical synaptic electrical circuit, wherein N is an integer greater than 1;

a single physical Spike Timing Dependent Plasticity (STDP) circuit having an output coupled to the input of the weight memory, a first input coupled to the output of the single physical neuron circuit, and a second input coupled to the presynaptic input; and

an interconnect circuit connected to the presynaptic input and to an output of the single physical neuron circuit;

wherein only one input of the single physical neuron circuit is connected to only an output of the single physical synapse circuit;

wherein the single physical synapse circuit is time-multiplexed to implement N virtual synapse circuits; and is

Wherein the single physical STDP circuit is time division multiplexed to implement N virtual STDP circuits; and is

Wherein the interconnect circuitry in each respective processing node in the array is coupled to the interconnect circuitry in each other processing node in the array.

Concept 2. the reconfigurable neural circuit according to concept 1:

wherein each processing node is adapted to read a respective one of N synaptic conductance values or weights from the weight memory for each respective one of N time periods, and wherein each respective synaptic conductance value or weight of the N synaptic conductance values or weights coupled to the single physical synaptic electrical circuit during a respective time period of the N time periods causes the single physical synaptic electrical circuit to operate as a respective virtual synapse in accordance with the conductance value or weight coupled during the respective time period; and is

Wherein each processing node is adapted to update the respective synaptic conductance value or weight read from the weight memory by writing to the weight memory in the respective time period in accordance with an output of the single physical spike timing-dependent plasticity circuit during the respective time period.

Concept 3 the reconfigurable neural circuit of

concept

1 or 2, wherein:

the neuron circuit includes an integrating and firing circuit.

Concept 4. the reconfigurable neural circuit of concept 1, wherein:

the weight memory includes a memristor memory, a flip-flop, a static random access memory, or a digital memory.

Concept 5. the reconfigurable neural circuit according to

concept

1, 2, 3, or 4:

wherein the interconnect circuitry in each processing node is coupled to the presynaptic input in each other processing node and to the output of the single physical neuron circuit in each other processing node.

Concept 6 the reconfigurable neural circuit of

concept

1, 2, 3, 4, or 5, wherein:

the interconnect circuitry includes a plurality of switches for changing the interconnections to and from the respective processing nodes and other processing nodes in the array.

Concept 7 the reconfigurable neural circuit of concept 6, wherein:

the plurality of switches includes a plurality of unidirectional and bidirectional switches.

Concept 8 the reconfigurable neural circuit of

concept

1, 2, 3, 4, 5, 6, or 7, wherein:

the single physical STDP circuit includes a biologically inspired Spike Timing Dependent Plasticity (STDP) learning rule.

Concept 9 the reconfigurable neural circuit of

concept

1, 2, 3, 4, 5, 6, 7, or 8, wherein:

the array comprises a two-dimensional array of processing nodes.

Concept 10 the reconfigurable neural circuit of

concept

1, 2, 3, 4, 5, 6, 7, 8, or 9, wherein each processing node further comprises:

a connectivity memory;

wherein the interconnect circuitry in each processing node comprises a plurality of switches;

wherein the connectivity memory stores a plurality of interconnect circuit routing controls for each respective switch of the plurality of switches; and is

Wherein the plurality of interconnect circuit routing controls for a respective switch of the plurality of switches is configured to control the respective switch for each respective time period of the N time periods.

Concept 11. the reconfigurable neural circuit according to concept 10:

wherein an interconnect circuit routing control stored in the connectivity memory in each processing node determines whether an output of a single physical neuron circuit in the respective processing node is connected to a respective presynaptic input in another processing node.

Concept 12. the reconfigurable neural circuit according to concept 10 or 11:

wherein the interconnect circuitry in the respective processing node provides a connection between the single physical neuron circuit, the single physical synapse circuit and the single physical STDP circuit in the respective processing node.

Concept 13 the reconfigurable neural circuit of concepts 10, 11 or 12:

wherein a plurality of interconnect circuit routing controls stored in the connectivity memory in a respective processing node are programmed independently for each respective processing node in the array.

Concept 14 the reconfigurable neural circuit of

concepts

10, 11, 12 or 13:

wherein the connectivity memory has a column corresponding to each respective switch in a processing node;

wherein each column has N rows corresponding to the N time periods; and is

Wherein the interconnect circuitry routing controls in the column for the respective switch comprise N controls for the respective switch, wherein each of the N controls is ON or OFF.

Concept 15 the reconfigurable neural circuit of

concept

1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, or 14:

wherein, during operation, time is divided into synaptic time division multiplexing cycles;

wherein each cycle comprises N time slots; and is

Wherein, during each of the N time slots, the weight memory outputs a respective one of the N synaptic conductance values or weights, the single physical synapse circuit implements a respective one of N virtual synapse circuits and outputs an output of the respective one of the N virtual synapse circuits to the single physical neuron circuit, and the single physical STDP circuit implements a respective one of the N virtual STDP circuits based on the output of the single physical neuron circuit during the time slot and the presynaptic input during the time slot, and updates the respective one of the N synaptic conductance values or weights during the time slot.

Concept 16 the reconfigurable neural circuit of concept 15:

wherein each processing node has a connectivity memory for controlling interconnect circuitry in the processing node; and is

Wherein during each time slot, interconnect circuitry in the respective processing node is configured in accordance with control read from the connectivity memory in the respective processing node.

Concept 17 a method for providing a reconfigurable neural circuit, comprising:

providing an array comprising a plurality of processing nodes;

wherein each processing node comprises:

a single physical neuron circuit having only one input and having an output;

Wherein the single physical STDP circuit is time division multiplexed to implement N virtual STDP circuits; and wherein the interconnect circuitry in each respective processing node in the array is coupled to the interconnect circuitry in each other processing node in the array.

Concept 18. the method of concept 17, further comprising:

reading, from the weight memory, a respective one of N synaptic conductance values or weights for each respective one of N time periods, and wherein each respective one of the N synaptic conductance values or weights coupled to the single physical synapse circuit during a respective one of the N time periods causes the single physical synapse circuit to operate as a respective virtual synapse in accordance with the conductance values or weights coupled during the respective time period; and

updating the respective synaptic conductance values or weights read from the weight memory by writing to the weight memory in respective time periods according to outputs of the single physical spike timing-dependent plasticity circuit during the respective time periods.

Concept 19 the method of concept 17 or 18, wherein:

the neuron circuit includes an integrating and firing circuit.

Concept 20 the method of concept 17, 18 or 19, wherein: the weight memory includes a memristor memory, a flip-flop, a static random access memory, or a digital memory.

Concept 21. according to the method of concept 17, 18, 19 or 20,

Concept 22 the method of concept 17, 18, 19, 20, or 21, wherein:

Concept 23. the method of concept 22, wherein:

Concept 24 the method of

concept

17, 18, 19, 20, 21, 22, or 23, wherein:

the STDP circuit includes a biologically inspired Spike Timing Dependent Plasticity (STDP) learning rule.

Concept 25 the method of

concept

17, 18, 19, 20, 21, 22, 23, or 24, wherein:

providing the array includes providing a two-dimensional array of processing nodes.

Concept 26 the method of

concept

17, 18, 19, 20, 21, 22, 23, 24, or 25, wherein:

wherein each processing node further comprises:

a connectivity memory;

wherein the interconnect circuitry in each processing node comprises a plurality of switches; and is

Storing, in a connectivity memory, a plurality of interconnect circuit routing controls for each respective switch of the plurality of switches; and is

Configuring the plurality of interconnect circuit routing controls for a respective switch of the plurality of switches to control the respective switch for each respective time period of the N time periods.

Concept 27. the method according to concept 26:

Concept 28. the method according to concept 26 or 27:

Concept 29 the method of

concept

26, 27 or 28, the method further comprising:

programming a plurality of interconnect circuit routing controls stored in the connectivity memory in each respective processing node;

wherein the programming is independent for each respective processing node in the array.

Concept 30. according to the method of

concepts

26, 27, 28 or 29,

wherein each column has N rows corresponding to the N time periods; and is

Concept 31 the method according to

concept

17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 or 30:

wherein each cycle comprises N time slots; and is

Concept 32. the method according to concept 31:

Claims

1. A reconfigurable neural circuit, comprising:

an array comprising a plurality of processing nodes;

wherein each processing node comprises:

a single physical neuron circuit having only one input and having an output;

2. The reconfigurable neural circuit of claim 1:

3. The reconfigurable neural circuit of claim 1, wherein: the neuron circuit includes an integrating and firing circuit.

4. The reconfigurable neural circuit of claim 1, wherein:

5. The reconfigurable neural circuit of claim 1:

6. The reconfigurable neural circuit of claim 1, wherein:

7. The reconfigurable neural circuit of claim 6, wherein:

8. The reconfigurable neural circuit of claim 1, wherein:

9. The reconfigurable neural circuit of claim 1, wherein:

the array comprises a two-dimensional array of processing nodes.

10. The reconfigurable neural circuit of claim 1, wherein each processing node further includes:

a connectivity memory;

11. The reconfigurable neural circuit of claim 10:

12. The reconfigurable neural circuit of claim 10:

13. The reconfigurable neural circuit of claim 10:

14. The reconfigurable neural circuit of claim 10:

wherein each column has N rows corresponding to the N time periods; and is

15. The reconfigurable neural circuit of claim 1:

wherein each cycle comprises N time slots; and is

16. The reconfigurable neural circuit of claim 15:

17. A method for providing a reconfigurable neural circuit, comprising:

providing an array comprising a plurality of processing nodes;

wherein each processing node comprises:

a single physical neuron circuit having only one input and having an output;

18. The method of claim 17:

19. The method of claim 17, wherein:

the neuron circuit includes an integrating and firing circuit.

20. The method of claim 17, wherein:

21. The method of claim 17:

22. The method of claim 17, wherein:

23. The method of claim 22, wherein:

24. The method of claim 17, wherein:

25. The method of claim 17, wherein:

26. The method of claim 17:

wherein each processing node further comprises:

a connectivity memory;

27. The method of claim 26:

28. The method of claim 26:

29. The method of claim 26, the method further comprising:

30. The method of claim 26:

wherein each column has N rows corresponding to the N time periods; and is

31. The method of claim 17:

wherein each cycle comprises N time slots; and is

32. The method of claim 31: