CN113992028A - Control method and control circuit of flyback power supply - Google Patents
Control method and control circuit of flyback power supply Download PDFInfo
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- CN113992028A CN113992028A CN202111313527.6A CN202111313527A CN113992028A CN 113992028 A CN113992028 A CN 113992028A CN 202111313527 A CN202111313527 A CN 202111313527A CN 113992028 A CN113992028 A CN 113992028A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention belongs to the technical field of switching power supplies, and particularly relates to a control method and a control circuit of a flyback power supply. The invention solves the problem of switching valley bottom of a flyback circuit based on a double-frequency clamping strategy, which mainly comprises the steps of carrying out zero-crossing detection on a ZCD signal of a flyback power supply according to period sampling to obtain a valley bottom signal, obtaining the valley bottom frequency of each period through counting the triggering frequency of the valley bottom signal, obtaining a valley bottom change signal according to the current valley bottom frequency and the last period valley bottom frequency, and finally generating a driving signal for controlling a switch according to the valley bottom signal, the valley bottom change signal and two groups of signals of a high-frequency clamping signal and a low-frequency clamping signal generated by a frequency control circuit. The invention limits the change of the valley bottom opening quantity through the double-frequency clamping, enlarges the transmission power range in the same valley bottom state, and avoids the repeated switching of the valley bottom due to the change of the system input condition when the valley bottom is close to the switching working point.
Description
Technical Field
The invention belongs to the technical field of switching power supplies, and particularly relates to a control method and a control circuit of a flyback power supply.
Background
Flyback converters are also known as single-ended Flyback or "Buck-Boost" converters. The power source is connected with the primary winding and the output end of the primary winding. The flyback converter has a simple circuit structure and low cost, and is widely applied to low-power supplies and various power adapters.
In the working state, the switching voltage of a switching device is lower than that in a continuous mode, which is beneficial to reducing the switching loss, and the peak current is smaller than that in an intermittent mode, which is beneficial to reducing the copper loss of a transformer, so that the efficiency can reach the best.
When the flyback converter works in light load, because the peak current is small, the frequency is very high under the quasi-resonance mode, and the switching loss is increased on the contrary, so that the conversion efficiency of the system is greatly reduced, and the flyback converter can be switched on when the flyback converter works in 2 nd, 3 rd or even more valley bottoms by frequency limitation in light load.
The converter falls to a plurality of valley bottoms and opens when light load, has effectively improved light load conversion efficiency, has nevertheless brought new problem:
problem 1: the problems of increased ripple, obvious audio noise, worse electromagnetic interference (EMI) and the like caused by frequent switching of the valley bottoms;
problem 2: for a flyback converter with a wide input range (90 Vrms-264 Vrms), when 90Vac low-voltage is input, rectified bus voltage generally has large fluctuation, particularly when the capacity of a high-voltage Bulk capacitor is small, the peak value of the bus voltage fluctuation can reach 50V or even higher, due to the fact that the introduction of a frequency reduction strategy is difficult, under the condition of the bus voltage fluctuation in such a large range, a multi-valley-bottom state can exist when the converter works in a full load mode, and therefore the primary current effective value is increased, and the working efficiency is reduced.
The current solution is to determine the valley bottom number of the main power switch when the main power switch is turned on through the feedback voltage VFB; a large hysteresis is made on the threshold of the feedback voltage VFB to prevent the valley bottom from switching frequently, as shown in fig. 1. The scheme is a better valley bottom switching solution, but the working frequency is completely determined by the inductance of the power level and the valley bottom period, the working frequency difference is large when the high-voltage full-load switch-type power supply works in the first valley bottom state under different bus voltages, and the working frequency is higher and the switching loss is larger if the high-voltage full-load switch-type power supply still works in the first valley bottom state. An additional maximum frequency limit strategy is also needed to solve this problem.
Disclosure of Invention
The invention provides a control method of a flyback power supply and a control circuit thereof aiming at the problems.
The technical scheme of the invention is as follows:
a control method of a flyback power supply comprises a primary winding unit, a secondary winding and an auxiliary winding unit, wherein the primary winding unit comprises a primary winding, a switching tube and a primary current detection resistor, one end of the primary winding is connected with a power supply voltage, the other end of the primary winding is connected with one end of the switching tube, and the other end of the switching tube is grounded after passing through the primary current detection resistor; the auxiliary winding unit comprises an auxiliary winding, a first resistor and a second resistor, one end of the auxiliary winding is grounded, the other end of the auxiliary winding is grounded after passing through a series structure of the first resistor and the second resistor, and a ZCD signal is arranged at the connecting point of the first resistor and the second resistor, and the control method is characterized in that:
sampling ZCD signals according to periods to perform zero-crossing detection to obtain valley bottom signals, and counting the number of valley bottoms in each period according to the triggering times of the valley bottom signals;
comparing the real-time valley bottom quantity of the current period with the valley bottom quantity of the previous period to obtain a valley bottom change signal, and defining that the corresponding valley bottom quantity is smaller than the valley bottom quantity of the previous period when the valley bottom change signal is high and corresponds to the next valley bottom signal of the current period, and the corresponding valley bottom quantity is larger than or equal to the valley bottom quantity of the previous period when the valley bottom change signal is low and corresponds to the next valley bottom signal of the current period;
produce two sets of signals of high frequency clamp signal and low frequency clamp signal through frequency control circuit to combine bottom of a valley change signal and bottom of a valley signal to produce the drive signal of switch tube jointly, specifically do: and performing phase-inversion on the low-frequency clamping signal and the valley bottom change signal to obtain a first control signal, performing phase-inversion on the high-frequency clamping signal and the valley bottom change signal to obtain a second control signal, performing phase-inversion on the first control signal and the second control signal to obtain a third control signal, and converting the third control signal into a driving signal under the enabling control of the valley bottom signal to drive the switching tube.
The flyback type power supply also comprises a control circuit of the flyback type power supply, wherein the flyback type power supply comprises a primary winding unit, a secondary winding and an auxiliary winding unit, the primary winding unit comprises a primary winding, a switching tube and a primary current detection resistor, one end of the primary winding is connected with a power supply voltage, the other end of the primary winding is connected with one end of the switching tube, and the other end of the switching tube is grounded after passing through the primary current detection resistor; the auxiliary winding unit comprises an auxiliary winding, a first resistor and a second resistor, one end of the auxiliary winding is grounded, the other end of the auxiliary winding is grounded after passing through a series structure of the first resistor and the second resistor, and a ZCD signal is arranged at the connecting point of the first resistor and the second resistor; the valley bottom working state change detection circuit is used for counting the valley bottom quantity of each period, comparing the real-time valley bottom quantity of the current period with the valley bottom quantity of the previous period and obtaining a valley bottom change signal; the dual-frequency clamping control circuit is used for generating a driving signal of the switching tube according to two groups of signals of a high-frequency clamping signal and a low-frequency clamping signal and combining a valley bottom change signal and a valley bottom signal; the valley bottom signal is obtained by carrying out zero-crossing detection on the ZCD signal; the frequency control circuit is used for generating;
the valley bottom working state change detection circuit comprises a rising edge counter, a latch, an adder and a digital comparator; a data input end of the rising edge counter inputs a valley bottom signal, and the rising edge counter is used for counting the valley bottom quantity in the current period when the valley bottom signal is triggered; the data input end of the latch is connected with the output end of the rising edge counter, the enabling end of the latch is connected with the switching tube driving signal and is used for latching the input data at the beginning of each period, namely when the switching tube driving signal is high; the constant 1 is input into one input end of the adder, the other input end of the adder is connected with the output end of the rising edge counter, the output end of the adder is connected with the first input end of the digital comparator, the second input end of the digital comparator is connected with the data output end of the latch, the output end of the digital comparator is at high level under the condition that the first input end is smaller than the second input end, and the output signal of the output end of the digital comparator is a valley bottom change signal;
the dual-frequency clamping control circuit comprises a first AND gate, a second AND gate, an OR gate, a phase inverter, a D trigger and a single-pulse trigger; one input end of the first AND gate inputs a valley bottom change signal, the other input end of the first AND gate inputs a low-frequency clamping signal, and the output end of the first AND gate is connected with one input end of the OR gate; one input end of the second AND gate inputs the high-frequency clamping signal, the other input end of the second AND gate is connected with the output end of the phase inverter, and the output end of the second AND gate is connected with the other input end of the OR gate; the input end of the phase inverter inputs valley bottom change signals; the D input end of the D trigger is connected with the output end of the OR gate, the edge trigger end of the D trigger is connected with the valley signal, the Q output end of the D trigger is connected with the input end of the single-pulse trigger, and the output end of the single-pulse trigger outputs a switching tube driving signal;
the frequency control circuit comprises a voltage-controlled current source, a capacitor, a first reference voltage source, a second reference voltage source, a first comparator, a second comparator and a switch tube; the output end of the voltage-controlled current source is connected with the positive plate of the capacitor, the negative plate of the capacitor is grounded, and the voltage-controlled current source is used for converting the feedback voltage into current to charge the capacitor; the positive input end of the first comparator is connected with the positive plate of the capacitor, the negative input end of the first comparator is connected with the positive electrode of the first reference voltage source, the output end of the first comparator outputs a high-frequency clamping signal, and when the capacitor voltage is higher than the voltage of the first reference voltage source, the high-frequency clamping signal output by the first comparator is high; the positive input end of the second comparator is connected with the positive plate of the capacitor, the negative input end of the second comparator is connected with the positive electrode of the second reference voltage source, the output end of the second comparator outputs a low-frequency clamping signal, and when the capacitor voltage is higher than the voltage of the second reference voltage source, the low-frequency clamping signal output by the second comparator is high; the switch tube is used to reset the voltage of the capacitor to 0 at the beginning of each cycle.
The frequency control circuit in the above scheme is an implementation method, and another implementation method is given below:
the frequency control circuit comprises a voltage-controlled current source, a capacitor, a reference voltage source, a comparator, a delay circuit and a switch tube; the output end of the voltage-controlled current source is connected with the positive plate of the capacitor, the negative plate of the capacitor is grounded, and the voltage-controlled current source is used for converting the feedback voltage into current to charge the capacitor; the positive input end of the comparator is connected with the positive plate of the capacitor, the negative input end of the comparator is connected with the positive electrode of the reference voltage source, the output end of the comparator outputs a high-frequency clamping signal, and the output end of the comparator outputs a low-frequency clamping signal after passing through the delay circuit; when the capacitor voltage is higher than the voltage of the reference voltage source, the high-frequency clamping signal output by the comparator is high, and conversely, the low-frequency clamping signal is high; the switch tube is used to reset the voltage of the capacitor to 0 at the beginning of each cycle.
The invention also provides a switching tube driving reset signal, wherein the switching tube driving reset signal is obtained by passing a current sampling signal and a feedback signal at the primary current detection resistor through a comparator and then passing a turn-off signal and a circuit protection signal through an OR gate; the switch tube drives a reset signal to be connected with a reset signal end of the D trigger and a reset signal end of the rising edge counter.
The beneficial effects of this technical scheme are: the invention combines the quasi-resonance flyback circuit topology, limits the change of the valley bottom opening quantity through the double-frequency clamping, increases the transmission power range under the same valley bottom state, and avoids the repeated switching of the valley bottom due to the change of the system input condition when the valley bottom is switched near the working point.
Drawings
Fig. 1 is a waveform diagram illustrating the conventional determination of the valley number of the main power switch when the main power switch is turned on by the feedback voltage VFB.
Fig. 2 is a schematic diagram of the operating frequency of the conventional frequency clamping method.
Fig. 3 is a schematic diagram of the operating frequency curve of the dual frequency clamping scheme proposed by the present invention.
Fig. 4 is a schematic circuit diagram of a flyback power supply.
Fig. 5 is a schematic diagram of a logic structure of a flyback power control circuit according to the present invention.
Fig. 6 is a schematic diagram of a dual frequency clamp control circuit according to the present invention.
Fig. 7 is a schematic diagram of a circuit structure for detecting valley bottom operation state change according to the present invention.
Fig. 8 is a schematic structural diagram of an implementation manner of the frequency control circuit according to the present invention.
Fig. 9 is a schematic structural diagram of another implementation manner of the frequency control circuit according to the present invention.
FIG. 10 is a timing diagram illustrating the critical waveforms and the valley count increasing control of the flyback power supply of the present invention.
FIG. 11 is a timing diagram illustrating the key waveforms and the valley count reduction control of the flyback power supply of the present invention.
FIG. 12 is a schematic diagram of a full-load full-QR operating state simulation waveform under 90Vac input condition according to the present invention.
FIG. 13 is a schematic diagram of a simulated waveform of a half-load full-valley bottom-3 operating state under a 90Vac input condition according to the present invention.
FIG. 14 is a schematic diagram of a simulated waveform of a 264Vac input condition according to the present invention in a fully loaded full valley 2 operating state.
Fig. 15 is a schematic diagram of a half-load full-valley bottom operating state simulation waveform under a 264Vac input condition.
In the simulation diagrams of fig. 12 to 15, the waveform names are, in order from top to bottom: ZCD _ CLK, FREQ _ Clamp _ Low, Valley _ Desrise, FREQ _ Clamp _ High, Valley _ Increase and DRV _ Set; iout, VDS, VFB, Vline, Vout.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
The working frequency of the conventional frequency clamping method is shown in fig. 2, and when the QR flyback converter works at a valley switching point, such as a-E point in the figure, frequent valley switching occurs; the reason is that: when the converter works near the point A, the converter is transited from the 2 nd valley bottom working state to the 1 st valley bottom working state along with the slow increase of the load, and when the converter works in the 1 st valley bottom working state on the right side of the point A, the transmission power of the converter is increased due to the improvement of the working frequency, the VFB voltage is regulated to be reduced through a negative feedback loop, and therefore the converter returns to the 2 nd valley bottom working state on the left side of the point A. This causes the transducer to repeatedly switch between the 1 st valley and the 2 nd valley operating states.
The operating frequency curve of the dual frequency clamping scheme proposed by the present invention is shown in fig. 3, and two frequency clamping curves are applied: when the load is reduced and the frequency needs to be reduced to increase the valley number, the valley number is clamped by a high-frequency curve; when the load is increased and the frequency needs to be increased to reduce the valley number, the low-frequency curve is used for clamping; therefore, the frequent switching of the number of the valley bottoms is avoided, the transmission power range of the working state of a single valley bottom is enlarged, and the improvement of the full load efficiency under 90Vac is facilitated.
The invention is an idea for solving the problem of valley bottom switching of a flyback circuit based on a dual-frequency clamping strategy, and the feedback mode of the flyback circuit can be a Secondary Side Regulator (SSR) mode or a Primary Side Regulator (PSR) mode; the operation mode of the flyback circuit may be a discontinuous mode (DCM), a quasi-resonant mode (QR), or a continuous mode (CCM).
The main mode of the dual-frequency clamping strategy is that zero-crossing detection is carried out on a ZCD signal of a flyback power supply according to period sampling to obtain a valley bottom signal, the valley bottom frequency of each period is obtained through counting the triggering frequency of the valley bottom signal, a valley bottom change signal is obtained according to the current valley bottom frequency and the valley bottom frequency of the last period, and then a driving signal for controlling a switch is finally generated according to the valley bottom signal and the valley bottom change signal and by combining two groups of signals of a high-frequency clamping signal and a low-frequency clamping signal generated by a frequency control circuit.
Fig. 4 is a schematic diagram of a typical flyback power supply, and on this basis, the logic structure of the control circuit proposed by the present invention is shown in fig. 5, which mainly includes: zero-crossing detection: sampling the ZCD signal to perform zero-crossing detection, and outputting a valley signal ZCD _ CLK; and (3) detecting the working state change of the valley bottom: according to the ZCD _ CLK signal of the current period and the Valley bottom working state of the previous period, Valley bottom working state change detection is carried out, a Valley bottom change signal Valley _ Release is output, and the Valley bottom change signal Valley _ Release is in a high level, which indicates that the corresponding Valley bottom quantity when the next ZCD _ CLK signal of the current period arrives is less than the Valley bottom quantity of the previous period; valley _ Release is low, which means that the number of corresponding valleys when the next ZCD _ CLK signal of the current period arrives is equal to or more than the number of valleys of the previous period; dual frequency clamp circuit: the frequency control circuit generates High and low two groups of frequency clamping signals FREQ _ Clamp _ low and FREQ _ Clamp _ High, and generates a driving opening signal DRV _ Set together with a Valley bottom working state change detection signal Valley _ Release and a Valley bottom signal ZCD _ CLK; the method can also comprise that a current sampling signal CS and a feedback signal FB pass through a comparator to obtain a turn-off signal, and the turn-off signal and signals sent by other protection functions (such as overvoltage protection, overcurrent protection, over-temperature protection and the like) generate a driving reset signal DRV _ Rst through an OR gate.
The main principle of the control of the invention is based on the following steps: locking the nth valley bottom working state by default; the condition that the number of the valley bottoms is increased to n + 1: the bottom period of the n valley is less than the high-frequency clamping period; the condition that the number of valleys decreases to n-1: (n-1) valley period > low frequency clamp period.
As shown in fig. 6, the logic circuit of the dual frequency clamping strategy is shown, wherein 100 is Valley _ Decrease signal, 100 obtains 106 signal Valley _ Decrease through inverter 105, and 100 and 106 are used as information for predicting the Decrease or increase (keep unchanged) of the Valley bottom operation state in real time; 103 is a low frequency clamp signal; 104 is a high frequency clamp signal, both of which are generated by a frequency control module; 100. 103, 104, 106, obtaining an input signal of 110(D flip-flop) through logic gates 101 (and gate), 107 (and gate), and 102 (or gate); 108 is the valley bottom detection signal ZCD _ CLK, 108 is connected to the edge trigger terminal of 110; 109 is a drive reset signal DRV _ Rst, the Rst reset terminal of 109 connection 110; an output end Q of the 110 is connected with an input end of the 111, the 111 is a single-pulse trigger, a high-level signal is converted into a narrow pulse, and a 112 driving setting signal DRV _ Set is obtained.
As shown in fig. 7, the circuit for detecting the change of the operating state of the valley bottom is shown, wherein 200 is a rising edge counter for counting the valley bottom information 201 of the current (nth) period in real time, i.e. Sn; at the beginning of each cycle (112 high), the valley number Sn is latched by the data latch 205 and compared to the valley state of the next (n +1) th cycle; the value 202 is constant 1, and is added to the value 201 through an adder 204 to obtain a value 203 (this is done to predict in advance to obtain real-time information of the valley bottom, for example, when the first valley bottom comes, the real-time valley bottom number is 0, but the first valley bottom will come certainly, the predicted valley bottom number should be 1, and so on); 203 and the output signal 206 of the latch 205 are compared to obtain a valley bottom working state change signal 100, if 203 is smaller than 206, 100 is high, and the valley bottom number of the current state is predicted to be smaller than the previous period; if 203 is greater than or equal to 206, 100 is low, and the valley number of the current state is predicted to be greater than or equal to the previous period.
As shown in fig. 8, which is a schematic diagram of a first frequency control circuit structure proposed by the present invention, wherein 301 is an internal power supply, 302 is a voltage-controlled current source, 303 is a feedback voltage signal, and the voltage-controlled current sources 302, 302 are connected to convert the voltage information of 303 into a current to charge a capacitor 305;
the positive terminal of the capacitor 305 is connected to the positive terminals of the comparators 306 and 309, the negative input terminal of the comparator 306 is connected to the positive terminal of the reference voltage source 307, the negative input terminal of the comparator 309 is connected to the positive terminal of the reference voltage source 308, when the voltage of the capacitor 305 is higher than the voltage VFCH of the 307, the 306 output signal FREQ _ Clamp _ High is High, and when the voltage of the capacitor 305 is higher than the voltage VFCL of the 308, the 309 output signal FREQ _ Clamp _ Low is High, thus generating the High and Low frequency clamping signals 103 and 104; 112 is the drive set signal, 112 is high at the beginning of each switching cycle, switch 304 is turned on, resetting the voltage of capacitor 305 to 0.
Fig. 9 is a schematic diagram of a second frequency control circuit structure proposed in the present invention, in which 310 is a delay circuit, and 103 is obtained by delaying the signal to 104; 310 may be either a fixed delay or may be designed as a variable delay time.
Fig. 10 and 11 are timing diagrams illustrating a key waveform and a control method thereof according to the present invention, wherein fig. 10 is a timing diagram illustrating an increase in the number of valleys, and fig. 11 is a timing diagram illustrating a decrease in the number of valleys.
12-15 are simulated waveforms in accordance with the present invention, wherein FIG. 12 is a 90Vac input, 12V/2.5A full load output; the fluctuation range of the rectified bus voltage is 75V-125V, and the peak value is 50V. And when the device is fully loaded, a full QR working state is realized. FIG. 13 shows the 90Vac input, 12V/1.25A half-load output; the voltage fluctuation range of the rectified bus is 73V-125V, and the peak value is 32V. And a full 3 rd valley bottom working state is realized during half load. FIG. 14 is the 264Vac input, 12V/2.5A full load output; the rectified bus voltage fluctuation range is 351V-372V, and the peak value is 21V. And when the machine is fully loaded, the 2 nd valley bottom working state is realized. FIG. 15 shows the 264Vac input, 12V/1.25A half-load output; the voltage fluctuation range of the rectified bus is 360V-372V, and the peak value is 12V. And a full 3 rd valley bottom working state is realized during half load. From the simulation examples described above, it can be seen that the approach of the present invention is practical and effective.
Claims (8)
1. A control method of a flyback power supply comprises a primary winding unit, a secondary winding and an auxiliary winding unit, wherein the primary winding unit comprises a primary winding, a switching tube and a primary current detection resistor, one end of the primary winding is connected with a power supply voltage, the other end of the primary winding is connected with one end of the switching tube, and the other end of the switching tube is grounded after passing through the primary current detection resistor; the auxiliary winding unit comprises an auxiliary winding, a first resistor and a second resistor, one end of the auxiliary winding is grounded, the other end of the auxiliary winding is grounded after passing through a series structure of the first resistor and the second resistor, and a ZCD signal is arranged at the connecting point of the first resistor and the second resistor, and the control method is characterized in that:
sampling ZCD signals according to periods to perform zero-crossing detection to obtain valley bottom signals, and counting the number of valley bottoms in each period according to the triggering times of the valley bottom signals;
comparing the real-time valley bottom quantity of the current period with the valley bottom quantity of the previous period to obtain a valley bottom change signal, and defining that the corresponding valley bottom quantity is smaller than the valley bottom quantity of the previous period when the valley bottom change signal is high and corresponds to the next valley bottom signal of the current period, and the corresponding valley bottom quantity is larger than or equal to the valley bottom quantity of the previous period when the valley bottom change signal is low and corresponds to the next valley bottom signal of the current period;
produce two sets of signals of high frequency clamp signal and low frequency clamp signal through frequency control circuit to combine bottom of a valley change signal and bottom of a valley signal to produce the drive signal of switch tube jointly, specifically do: and performing phase-inversion on the low-frequency clamping signal and the valley bottom change signal to obtain a first control signal, performing phase-inversion on the high-frequency clamping signal and the valley bottom change signal to obtain a second control signal, performing phase-inversion on the first control signal and the second control signal to obtain a third control signal, and converting the third control signal into a driving signal under the enabling control of the valley bottom signal to drive the switching tube.
2. The method for controlling a flyback power supply according to claim 1, wherein a circuit that generates two sets of signals, namely a high-frequency clamp signal and a low-frequency clamp signal by a frequency control circuit and generates a driving signal of a switching tube by combining a valley bottom change signal and a valley bottom signal is defined as a dual-frequency clamp control circuit, and the dual-frequency clamp control circuit comprises a first and gate, a second and gate, an or gate, an inverter, a D flip-flop and a single pulse flip-flop; one input end of the first AND gate inputs a valley bottom change signal, the other input end of the first AND gate inputs a low-frequency clamping signal, and the output end of the first AND gate is connected with one input end of the OR gate; one input end of the second AND gate inputs the high-frequency clamping signal, the other input end of the second AND gate is connected with the output end of the phase inverter, and the output end of the second AND gate is connected with the other input end of the OR gate; the input end of the phase inverter inputs valley bottom change signals; the D input end of the D trigger is connected with the output end of the OR gate, the edge trigger end of the D trigger is connected with the valley signal, the Q output end of the D trigger is connected with the input end of the single-pulse trigger, and the output end of the single-pulse trigger outputs a switching tube driving signal.
3. The control method of a flyback power supply as in claim 2, wherein a circuit for obtaining the valley bottom variation signal is defined as a valley bottom operation state variation detection circuit, the valley bottom operation state variation detection circuit comprising a rising edge counter, a latch, an adder and a digital comparator; a data input end of the rising edge counter inputs a valley bottom signal, and the rising edge counter is used for counting the valley bottom quantity in the current period when the valley bottom signal is triggered; the data input end of the latch is connected with the output end of the rising edge counter, the enabling end of the latch is connected with the switching tube driving signal and is used for latching the input data at the beginning of each period, namely when the switching tube driving signal is high; the constant 1 is input into one input end of the adder, the other input end of the adder is connected with the output end of the rising edge counter, the output end of the adder is connected with the first input end of the digital comparator, the second input end of the digital comparator is connected with the data output end of the latch, the output end of the digital comparator is at high level when the first input end is smaller than the second input end, and the output signal of the output end of the digital comparator is a valley bottom change signal.
4. The method according to claim 3, wherein the frequency control circuit comprises a voltage-controlled current source, a capacitor, a first reference voltage source, a second reference voltage source, a first comparator, a second comparator and a switch tube; the output end of the voltage-controlled current source is connected with the positive plate of the capacitor, the negative plate of the capacitor is grounded, and the voltage-controlled current source is used for converting the feedback voltage into current to charge the capacitor; the positive input end of the first comparator is connected with the positive plate of the capacitor, the negative input end of the first comparator is connected with the positive electrode of the first reference voltage source, the output end of the first comparator outputs a high-frequency clamping signal, and when the capacitor voltage is higher than the voltage of the first reference voltage source, the high-frequency clamping signal output by the first comparator is high; the positive input end of the second comparator is connected with the positive plate of the capacitor, the negative input end of the second comparator is connected with the positive electrode of the second reference voltage source, the output end of the second comparator outputs a low-frequency clamping signal, and when the capacitor voltage is higher than the voltage of the second reference voltage source, the low-frequency clamping signal output by the second comparator is high; the switch tube is used to reset the voltage of the capacitor to 0 at the beginning of each cycle.
5. The method according to claim 3, wherein the frequency control circuit comprises a voltage-controlled current source, a capacitor, a reference voltage source, a comparator, a delay circuit and a switch tube; the output end of the voltage-controlled current source is connected with the positive plate of the capacitor, the negative plate of the capacitor is grounded, and the voltage-controlled current source is used for converting the feedback voltage into current to charge the capacitor; the positive input end of the comparator is connected with the positive plate of the capacitor, the negative input end of the comparator is connected with the positive electrode of the reference voltage source, the output end of the comparator outputs a high-frequency clamping signal, and the output end of the comparator outputs a low-frequency clamping signal after passing through the delay circuit; when the capacitor voltage is higher than the voltage of the reference voltage source, the high-frequency clamping signal output by the comparator is high, and conversely, the low-frequency clamping signal is high; the switch tube is used to reset the voltage of the capacitor to 0 at the beginning of each cycle.
6. The control method of the flyback power supply according to claim 3, further comprising a switching tube driving reset signal, wherein the switching tube driving reset signal is obtained by passing a current sampling signal and a feedback signal at the primary side current detection resistor through a comparator and then passing a turn-off signal and a circuit protection signal through an or gate; the switch tube drives a reset signal to be connected with a reset signal end of the D trigger and a reset signal end of the rising edge counter.
7. A control circuit of a flyback power supply comprises a primary winding unit, a secondary winding and an auxiliary winding unit, wherein the primary winding unit comprises a primary winding, a switching tube and a primary current detection resistor, one end of the primary winding is connected with a power supply voltage, the other end of the primary winding is connected with one end of the switching tube, and the other end of the switching tube is grounded after passing through the primary current detection resistor; the auxiliary winding unit comprises an auxiliary winding, a first resistor and a second resistor, one end of the auxiliary winding is grounded, the other end of the auxiliary winding is grounded after passing through a series structure of the first resistor and the second resistor, and a ZCD signal is arranged at the connecting point of the first resistor and the second resistor; the valley bottom working state change detection circuit is used for counting the valley bottom quantity of each period, comparing the real-time valley bottom quantity of the current period with the valley bottom quantity of the previous period and obtaining a valley bottom change signal; the dual-frequency clamping control circuit is used for generating a driving signal of the switching tube according to two groups of signals of a high-frequency clamping signal and a low-frequency clamping signal and combining a valley bottom change signal and a valley bottom signal; the valley bottom signal is obtained by carrying out zero-crossing detection on the ZCD signal; the frequency control circuit is used for generating;
the valley bottom working state change detection circuit comprises a rising edge counter, a latch, an adder and a digital comparator; a data input end of the rising edge counter inputs a valley bottom signal, and the rising edge counter is used for counting the valley bottom quantity in the current period when the valley bottom signal is triggered; the data input end of the latch is connected with the output end of the rising edge counter, the enabling end of the latch is connected with the switching tube driving signal and is used for latching the input data at the beginning of each period, namely when the switching tube driving signal is high; the constant 1 is input into one input end of the adder, the other input end of the adder is connected with the output end of the rising edge counter, the output end of the adder is connected with the first input end of the digital comparator, the second input end of the digital comparator is connected with the data output end of the latch, the output end of the digital comparator is at high level under the condition that the first input end is smaller than the second input end, and the output signal of the output end of the digital comparator is a valley bottom change signal;
the dual-frequency clamping control circuit comprises a first AND gate, a second AND gate, an OR gate, a phase inverter, a D trigger and a single-pulse trigger; one input end of the first AND gate inputs a valley bottom change signal, the other input end of the first AND gate inputs a low-frequency clamping signal, and the output end of the first AND gate is connected with one input end of the OR gate; one input end of the second AND gate inputs the high-frequency clamping signal, the other input end of the second AND gate is connected with the output end of the phase inverter, and the output end of the second AND gate is connected with the other input end of the OR gate; the input end of the phase inverter inputs valley bottom change signals; the D input end of the D trigger is connected with the output end of the OR gate, the edge trigger end of the D trigger is connected with the valley signal, the Q output end of the D trigger is connected with the input end of the single-pulse trigger, and the output end of the single-pulse trigger outputs a switching tube driving signal;
the frequency control circuit comprises a voltage-controlled current source, a capacitor, a first reference voltage source, a second reference voltage source, a first comparator, a second comparator and a switch tube; the output end of the voltage-controlled current source is connected with the positive plate of the capacitor, the negative plate of the capacitor is grounded, and the voltage-controlled current source is used for converting the feedback voltage into current to charge the capacitor; the positive input end of the first comparator is connected with the positive plate of the capacitor, the negative input end of the first comparator is connected with the positive electrode of the first reference voltage source, the output end of the first comparator outputs a high-frequency clamping signal, and when the capacitor voltage is higher than the voltage of the first reference voltage source, the high-frequency clamping signal output by the first comparator is high; the positive input end of the second comparator is connected with the positive plate of the capacitor, the negative input end of the second comparator is connected with the positive electrode of the second reference voltage source, the output end of the second comparator outputs a low-frequency clamping signal, and when the capacitor voltage is higher than the voltage of the second reference voltage source, the low-frequency clamping signal output by the second comparator is high; the switch tube is used to reset the voltage of the capacitor to 0 at the beginning of each cycle.
8. A control circuit of a flyback power supply comprises a primary winding unit, a secondary winding and an auxiliary winding unit, wherein the primary winding unit comprises a primary winding, a switching tube and a primary current detection resistor, one end of the primary winding is connected with a power supply voltage, the other end of the primary winding is connected with one end of the switching tube, and the other end of the switching tube is grounded after passing through the primary current detection resistor; the auxiliary winding unit comprises an auxiliary winding, a first resistor and a second resistor, one end of the auxiliary winding is grounded, the other end of the auxiliary winding is grounded after passing through a series structure of the first resistor and the second resistor, and a ZCD signal is arranged at the connecting point of the first resistor and the second resistor; the valley bottom working state change detection circuit is used for counting the valley bottom quantity of each period, comparing the real-time valley bottom quantity of the current period with the valley bottom quantity of the previous period and obtaining a valley bottom change signal; the dual-frequency clamping control circuit is used for generating a driving signal of the switching tube according to two groups of signals of a high-frequency clamping signal and a low-frequency clamping signal and combining a valley bottom change signal and a valley bottom signal; the valley bottom signal is obtained by carrying out zero-crossing detection on the ZCD signal; the frequency control circuit is used for generating;
the valley bottom working state change detection circuit comprises a rising edge counter, a latch, an adder and a digital comparator; a data input end of the rising edge counter inputs a valley bottom signal, and the rising edge counter is used for counting the valley bottom quantity in the current period when the valley bottom signal is triggered; the data input end of the latch is connected with the output end of the rising edge counter, the enabling end of the latch is connected with the switching tube driving signal and is used for latching the input data at the beginning of each period, namely when the switching tube driving signal is high; the constant 1 is input into one input end of the adder, the other input end of the adder is connected with the output end of the rising edge counter, the output end of the adder is connected with the first input end of the digital comparator, the second input end of the digital comparator is connected with the data output end of the latch, the output end of the digital comparator is at high level under the condition that the first input end is smaller than the second input end, and the output signal of the output end of the digital comparator is a valley bottom change signal;
the dual-frequency clamping control circuit comprises a first AND gate, a second AND gate, an OR gate, a phase inverter, a D trigger and a single-pulse trigger; one input end of the first AND gate inputs a valley bottom change signal, the other input end of the first AND gate inputs a low-frequency clamping signal, and the output end of the first AND gate is connected with one input end of the OR gate; one input end of the second AND gate inputs the high-frequency clamping signal, the other input end of the second AND gate is connected with the output end of the phase inverter, and the output end of the second AND gate is connected with the other input end of the OR gate; the input end of the phase inverter inputs valley bottom change signals; the D input end of the D trigger is connected with the output end of the OR gate, the edge trigger end of the D trigger is connected with the valley signal, the Q output end of the D trigger is connected with the input end of the single-pulse trigger, and the output end of the single-pulse trigger outputs a switching tube driving signal;
the frequency control circuit comprises a voltage-controlled current source, a capacitor, a reference voltage source, a comparator, a delay circuit and a switch tube; the output end of the voltage-controlled current source is connected with the positive plate of the capacitor, the negative plate of the capacitor is grounded, and the voltage-controlled current source is used for converting the feedback voltage into current to charge the capacitor; the positive input end of the comparator is connected with the positive plate of the capacitor, the negative input end of the comparator is connected with the positive electrode of the reference voltage source, the output end of the comparator outputs a high-frequency clamping signal, and the output end of the comparator outputs a low-frequency clamping signal after passing through the delay circuit; when the capacitor voltage is higher than the voltage of the reference voltage source, the high-frequency clamping signal output by the comparator is high, and conversely, the low-frequency clamping signal is high; the switch tube is used to reset the voltage of the capacitor to 0 at the beginning of each cycle.
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