CN111293877A - Hybrid analog-to-digital converter circuit - Google Patents

Abstract

The invention discloses a hybrid analog-digital converter circuit capable of stabilizing voltage at two ends of a load and reducing output voltage ripple, which comprises a power supply, a digital converter, an analog converter and a load assembly, wherein the power supply is connected with the digital converter; the analog converter comprises a plurality of power supply capacitors which are arranged in parallel, the load components are communicated with the power supply capacitors in turn when working, and the power supply capacitors which are not connected with the load components are communicated with the digital converter in turn. The invention also discloses a mixed analog-digital converter circuit, which comprises a power supply, a digital converter, an analog converter and a load component; the digital converter comprises an element multiplexer connected with the input end and the output end of a power supply through wires, the element multiplexer comprises a plurality of power supply capacitors arranged in series, the analog converter comprises the element multiplexer, two ends of each power supply capacitor in the element multiplexer are respectively connected with the input end and the output end of the load assembly through discharge wires, and the load assembly is communicated with the power supply capacitors in turn when in work.

Description

Hybrid analog-to-digital converter circuit

technical field

The invention relates to a hybrid analog-digital converter circuit.

Background technique

A DC/DC converter is a voltage converter that effectively outputs a specified voltage after converting the input voltage. DC/DC converters are divided into three categories: step-up DC/DC converters, step-down DC/DC converters, and buck-boost DC/DC converters. DC/DC converters have both linear and switching modes. The traditional linear voltage has low efficiency, large heat generation and large volume. The mainstream of high-power conversion is switching power supply. Traditional switching power supplies are based on digital converters and use semiconductor devices as switches. The switching action will generate square voltage/current waveforms, and will suffer severe instantaneous power shocks during frequent switching. Therefore, a huge low-pass filter is required to filter ripples.

At present, there are three main methods to solve the problem of oversized low-pass filter:

One is to reduce the ripple from the power supply. Usually, a multi-level converter is used to reduce the ripple of the power supply. However, a multi-level converter requires a large number of semiconductors, and in order to maintain the power balance between the sub-modules, additional transmission is required. Inductive circuits and complex control methods.

The second is to increase the gain of the low-pass filter in the transmission process. By increasing the switching frequency, the filtering effect of a specific low-pass filter can be increased. But increasing the switching frequency increases power losses in the semiconductor and magnetic units. In addition, parasitic elements such as capacitors, resistors, and inductors reduce the filtering effect of the filter at high frequencies.

The third is to use advanced control methods, such as active capacitance method. The method can transfer the ripple power to the energy storage device, thereby reducing the magnitude of the ripple power delivered to the load. However, according to Shannon's sampling theorem, the control bandwidth in the existing DC/DC converter is limited by the switching frequency, but the frequency of the main component of the switching ripple is equal to or greater than the switching frequency. Therefore, existing active control methods cannot reduce switching harmonics.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a hybrid analog-to-digital converter circuit which can stabilize the voltage at both ends of the load, reduce the output voltage ripple and improve the power density of the transformer.

In order to solve the above-mentioned technical problems, the technical scheme adopted in the present invention is: a hybrid analog-to-digital converter circuit, comprising a power supply and a digital converter connected with the power supply, and an analog converter is connected between the input end and the output end of the digital converter The converter, the analog converter is connected with the load component;

The analog converter includes a number of power supply capacitors, and both ends of each power supply capacitor are respectively connected with the input end and the output end of the digital converter through a charging wire, and at least one charging wire is provided with a charging switch; both ends of each power supply capacitor are connected They are all connected to the input end and output end of the load component respectively through the discharge wire, and at least one discharge wire is provided with a discharge switch; when the load component is working, it is connected to each power supply capacitor in turn by closing the corresponding discharge switch, and is not connected to the load. The supply capacitors in the connected state of the components are in turn connected to the digital converter by closing the corresponding charging switches.

As a preferred solution, the load component is equivalent to a load capacitance _CL and a load resistance RL arranged in parallel and a load inductance _L connected in series with the two connected in parallel;

其中I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o是负载组件部分等效电阻R_L上的输出电压纹波；f_sw是电路开关频率；L为负载组件部分等效电感；When the partial equivalent capacitance _CL of the load component is given, the minimum capacitance value C ₁ , C ₂ , ... C _N of the power supply capacitor is equal to the DC bus capacitance value C _bus , which is calculated by the following formula:

where I _o is the output current on the equivalent resistance _RL of the load component part; V _o is the output voltage on the equivalent resistance _RL of the load component part; ΔV _o is the output voltage ripple on the equivalent resistance _RL of the load component part ; f _sw is the switching frequency of the circuit; L is the partial equivalent inductance of the load component;

令NC_bus＝C_L，得出所需最小C_L：

其中N为供电电容数量，I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o为负载组件部分等效电阻R_L上输出电压纹波；f_sw为电路开关频率；L 为负载组件部分等效电感。When the partial equivalent capacitance _CL of the load component is not limited, the minimum capacitance values C ₁ , C ₂ , . . . C _N of the power supply capacitors are equal to the DC bus capacitance value C _bus . Calculated by:

Let NC _bus = C _L , which gives the required minimum C _L :

where N is the number of power supply capacitors, I _o is the output current on the equivalent resistance _RL of the load component; V _o is the output voltage on the equivalent resistance _RL of the load component; ΔV _o is the equivalent resistance of the load component _RL upper output voltage ripple; f _sw is the switching frequency of the circuit; L is the partial equivalent inductance of the load component.

As a preferred solution, the digital converter is a DC/DC converter.

As a preferred solution, the digital converter is a step-down converter, a step-up transformer or a resonant converter.

As a preferred solution, the charging time and discharging time of each of the power supply capacitors are the circuit switching period T _sw / the number N of power supply capacitors.

Another technical problem to be solved by the present invention is to provide another hybrid analog-to-digital converter circuit that can stabilize the voltage at both ends of the load, reduce the output voltage ripple, and improve the power density of the transformer.

In order to solve the above-mentioned technical problems, the technical scheme adopted in the present invention is:

A hybrid analog-to-digital converter circuit comprises a power supply and a digital converter connected with the power supply, an analog converter is connected between an input end and an output end of the digital converter, and the analog converter is connected with a load component;

The digital converter includes an element multiplexer connected to the input end and the output end of the power supply through wires, the element multiplexer includes a plurality of power supply capacitors arranged in series, the analog converter includes the element multiplexer, and the element multiplexer is included. Both ends of each power supply capacitor in the component multiplexer are respectively connected with the input end and the output end of the load component through a discharge wire, and at least one discharge wire is provided with a discharge switch; when the load component is working, the corresponding discharge switch is closed by closing Turn on each power supply capacitor in turn.

As a preferred solution, the load component is equivalent to a load capacitance _CL and a load resistance RL arranged in parallel and a load inductance _L connected in series with the two connected in parallel;

其中N为供电电容数量，I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o是负载组件部分等效电阻R_L上输出电压纹波； f_sw是开关频率；L为负载组件部分等效电感；When the partial equivalent capacitance _CL of the load component is given, the minimum capacitance value C ₁ , C ₂ , ... C _N of the power supply capacitor is equal to the DC bus capacitance value C _bus , which is calculated by the following formula:

Among them, N is the number of power supply capacitors, I _o is the output current on the equivalent resistance _RL of the load component; V _o is the output voltage on the equivalent resistance _RL of the load component; ΔV _o is the equivalent resistance of the load component _RL. Upper output voltage ripple; f _sw is the switching frequency; L is the partial equivalent inductance of the load component;

令NC_bus＝C_L，得出：

其中N为供电电容数量，I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o负载组件部分等效电阻R_L上输出电压纹波；f_sw开关频率；L为负载组件部分等效电感；When the partial equivalent capacitance _CL of the load component is not limited, the minimum capacitance value C ₁ , C ₂ , . . . C _N of the power supply capacitor is equal to the DC bus capacitance value C _bus , which is calculated by the following formula:

Let NC _bus = C _L , we get:

where N is the number of power supply capacitors, I _o is the output current on the equivalent resistance _RL of the load component part; V _o is the output voltage on the equivalent resistance _RL of the load component part; ΔV _o is the equivalent resistance _RL of the load component part of the output voltage Output voltage ripple; f _sw switching frequency; L is the partial equivalent inductance of the load component;

As a preferred solution, the charging time and discharging time of each of the power supply capacitors are the circuit switching period T _sw / the number N of power supply capacitors.

The beneficial effects of the present invention are:

In the circuit disclosed in the present invention, the loads draw energy from the power supply capacitors one by one. Therefore, the voltage across the load is finally maintained between the voltages of the selected capacitors, which can be kept stable, and will not suddenly appear violent in traditional digital converters. The voltage fluctuation of (from 0 to E);

In addition, the charging circuit and the discharging circuit are independent circuits, so even without advanced control technology or high-bandwidth control, the ripple power will be forcibly transferred to the capacitor on the DC bus instead of directly supplying the load;

This circuit can obtain different types of hybrid analog-to-digital converter circuits by selecting a specific digital converter and the connection mode of the DC bus capacitor, and the most suitable solution can be selected for specific problems.

The hybrid analog-to-digital converter circuit can effectively reduce the ripple voltage on the load, and the larger the switching frequency, the more obvious this phenomenon is, thereby reducing the low-pass filter and improving the power density.

Since the power supply voltage, current and load voltage and current of the hybrid analog-to-digital converter circuit including the component multiplexer have no square waves, the ripple is very small, and only a small low-pass filter is required, which can effectively improve the power density, and, The power supply current is not a square wave or a square wave-like mode, the electromagnetic interference is small, and the required current maximum value will be reduced.

The circuit described in this patent discloses the minimum limit values of L, C _L , and C _bus to minimize the overall volume of the circuit. If the actual use value is greater than the minimum limit value, the output ripple will be smaller and the quality will be higher.

And when _CL is unknown, the goal is to minimize the total volume of the capacitor. The total volume of the total capacitance is determined by the total capacitance value (ie, NC _bus + C _L ), because for the product of two parameters (ie, NC _bus and _CL ) constant, then the sum of the parameters (ie, NC _bus + C _{L )} ) there is a minimum value obtained if and only if the two parameters are equal to each other. Because the total volume of the capacitor is proportional to the total capacitance value of the capacitor (ie, NC _bus + _CL ), the total volume is the smallest when NC _bus = _CL .

Description of drawings

1 is a circuit diagram of a hybrid analog-to-digital converter circuit for Embodiment 1 of the present invention;

2 is a circuit diagram of a step-down converter and a parallel DC capacitor for Embodiment 2 of the present invention;

3 is a waveform diagram of a step-down converter and a parallel DC capacitor for Embodiment 2 of the present invention;

4 is a graph obtained from a comparison simulation experiment of the output ripple size of the hybrid analog-to-digital converter converter and the discontinuous conduction step-down conversion circuit according to Embodiment 2 of the present invention;

5 is a circuit diagram of an N:1 voltage divider and a series capacitor for Embodiment 4 of the present invention;

6 is an equivalent circuit diagram of an N:1 voltage divider and a series capacitor for Embodiment 4 of the present invention;

FIG. 7 is a waveform diagram of an N:1 voltage divider and a series capacitor according to Embodiment 4 of the present invention.

Detailed ways

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Embodiment 1 As shown in FIG. 1, a hybrid analog-to-digital converter circuit includes a power supply and a digital converter connected to the power supply. An analog converter is connected between the input end and the output end of the digital converter, and the analog converter is connected to The load components are connected;

The analog converter includes a number of power supply capacitors, and both ends of each power supply capacitor are respectively connected with the input end and the output end of the digital converter through charging wires, wherein two charging wires are provided with charging switches; both ends of each power supply capacitor are connected. They are all connected to the input and output ends of the load components through discharge wires, and two discharge wires are provided with discharge switches; when the load components are working, they are connected to each power supply capacitor in turn by closing the corresponding discharge switches, and not connected to the load. The supply capacitors in the connected state of the components are in turn connected to the digital converter by closing the corresponding charging switches. The charging time and discharging time of each power supply capacitor are the circuit switching period T _sw / the number N of power supply capacitors.

Wherein, the load component is equivalent to a load capacitance _CL and a load resistance RL set in parallel and a load inductance _L connected in series with the two connected in parallel;

其中I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o是负载组件部分等效电阻R_L上的输出电压纹波给定的上限值；f_sw是电路开关频率；L为负载组件部分等效电感；When the partial equivalent capacitance _CL of the load component is given, the minimum capacitance value C ₁ , C ₂ , ... C _N of the power supply capacitor is equal to the DC bus capacitance value C _bus , which is calculated by the following formula:

where I _o is the output current on the equivalent resistance _RL of the load component part; V _o is the output voltage on the equivalent resistance _RL of the load component part; ΔV _o is the output voltage ripple on the equivalent resistance _RL of the load component part The given upper limit value; f _sw is the switching frequency of the circuit; L is the partial equivalent inductance of the load component;

令NC_bus＝C_L，得出所需最小C_L：

其中N为供电电容数量，I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o为负载组件部分等效电阻R_L上输出电压纹波给定的上限值；f_sw为电路开关频率；L为负载组件部分等效电感。When the partial equivalent capacitance _CL of the load component is not limited, the minimum capacitance values C ₁ , C ₂ , . . . C _N of the power supply capacitors are equal to the DC bus capacitance value C _bus . Calculated by:

Let NC _bus = C _L , which gives the required minimum C _L :

where N is the number of power supply capacitors, I _o is the output current on the equivalent resistance _RL of the load component; V _o is the output voltage on the equivalent resistance _RL of the load component; ΔV _o is the equivalent resistance of the load component _RL The upper limit value given by the upper output voltage ripple; f _sw is the switching frequency of the circuit; L is the partial equivalent inductance of the load component.

Embodiment 2. As shown in accompanying drawing 2: a kind of hybrid analog-to-digital converter circuit, including the power supply and the digital converter connected with the power supply, what the digital converter adopts is a step-down converter, the input end of the digital converter and An analog converter is connected between the output ends, and the analog converter is connected with the load component;

The analog converter includes a number of power supply capacitors arranged in parallel, and both ends of each power supply capacitor are respectively connected with the input end and the output end of the digital converter through a charging wire, one of which is provided with a charging switch; each power supply capacitor Both ends are respectively connected with the input and output ends of the load component through discharge wires, and a discharge switch is provided on one of the discharge wires; when the load component is working, it is connected to each power supply capacitor in turn by closing the corresponding discharge switch, and does not connect with the power supply capacitor. The power supply capacitor in the connected state of the load component is connected to the digital converter in turn by closing the corresponding charging switch. The charging time and discharging time of each power supply capacitor are the circuit switching period T _sw / the number N of power supply capacitors.

Wherein, the load component is equivalent to a load capacitance _CL and a load resistance RL set in parallel and a load inductance _L connected in series with the two connected in parallel;

其中I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o是负载组件部分等效电阻R_L上的输出电压纹波给定的上限值；f_sw是电路开关频率；L为负载组件部分等效电感；The equivalent capacitance _CL of the load component has been given, and the minimum capacitance values C ₁ , C ₂ , ... C _N of the power supply capacitors are equal to the DC bus capacitance value C _bus , which is calculated by the following formula:

where I _o is the output current on the equivalent resistance _RL of the load component part; V _o is the output voltage on the equivalent resistance _RL of the load component part; ΔV _o is the output voltage ripple on the equivalent resistance _RL of the load component part The given upper limit value; f _sw is the switching frequency of the circuit; L is the partial equivalent inductance of the load component;

When the layout of this circuit is determined, the specific working principle and the minimum capacitance required by the power supply capacitor are solved as follows:

(1) In the figure, S _uc1 and S _uc2 are charge switches, and S _ud1 and S _ud2 are discharge switches. When _C1 charges, _C2 discharges;

(2) S ₁ /S ₂ follows the working principle of a buck converter. When the buck converter operates in discontinuous current mode, the modulation ratio M is equal to:

Among them, V _bus is the voltage of the DC bus capacitor, D is the duty cycle, R _L is the equivalent resistance of the load component; E is the power supply voltage; f _sw is the switching frequency; L ₁ is the inductance of the buck converter;

According to the above formula (1), the duty ratio D is solved, and according to the circuit switching cycle, the conduction states of each switch as shown in Figure 3 are obtained, where t ₀ is the conduction of S ₁ in the first circuit switching cycle. Start time; t ₁ is the start time when S ₁ is turned off in the first circuit switching cycle; t ₂ is the start time when S ₁ is turned on in the second circuit switching cycle, which is the same as the t in the previous cycle. ₀ corresponds to; t ₃ is the start moment when S ₁ is turned off in the second circuit switching cycle, corresponding to t ₀ of the previous cycle;

(3) During the period of [t ₀ , t ₂ ], C ₁ is charged and C ₂ is discharged, and the equivalent circuit is shown in Figure 2b.

(4) During the period of [t ₂ , t ₄ ], C ₂ is charged and C ₁ is discharged, and the equivalent circuit is shown in Figure 2c.

Because the charge and discharge circuits are independent, the output voltage ripple depends on the discharge circuit. The discharge circuit has three energy storage devices (C _bus , L, C _L ). According to the space state method of network theory, three state equations (2)-(4) can be obtained to find general solutions. The three equations (5)-(7) are used to identify the initial state.

Among them, L ₂ is the partial equivalent inductance of the load component; _CL is the partial equivalent capacitance of the load component; C _bus is the equivalent capacitance on the DC bus; I _o is the output current on the equivalent resistance _RL of the load component part; V _o is the output voltage on the equivalent resistance _RL of the load component; ΔV _o is the output voltage ripple on the equivalent resistance _RL of the load component; f _sw is the switching frequency; L is the equivalent inductance of the load component;

Among them, I _o is the output current on the partial equivalent resistance _RL of the load component; V _o is the output voltage on the partial equivalent resistance _RL of the load component; T _sw is the circuit switching period; L is the partial equivalent inductance of the load component; Equations (2)-(7) are solved as follows:

According to the above formula, the waveforms of v _C1 and v _C1 as well as i _L and v _o in Fig. 3 can be obtained. As can be seen from the figure, v _Cbus (the value is equal to v _C1 and v _C2 ) is proportional to (-t), and i _L and v are proportional to (-t). (-t ² ) is proportional to v _o (value equal to v _CL (t)) and (-t ³ ), these conclusions are also verified by equations (8)-(10).

v_CL(t)的最大最小值分别记为V_{CL_max}和V_{CL_min}，其结果如公式(11)所示。In formula (10), let

The maximum and minimum values of v _CL (t) are denoted as V _{CL_max} and V _{CL_min} , respectively, and the results are shown in formula (11).

By formula (11), the ripple voltage of the load of this circuit will be obtained, denoted as ΔV _{o_MAD} , and the result is shown in formula (12), and the result can be verified by subsequent simulation analysis.

When the upper limit value ΔV _o of the ripple voltage of the load is given, the minimum capacitance value C ₁ , C ₂ , . . . C _N of the power supply capacitor can be calculated from the above formula (12), namely the DC bus capacitance value C _bus ,

The ripple voltage of the discontinuous conduction step-down converter circuit (DCM Buck circuit) is denoted as ΔV _{o_BUCK} , and the result is shown in equation (13).

成比例，而非连续导通降压式变换电路(DCM Buck电路)的波纹电压ΔV_{o_BUCK}与1/f_sw成比例。此外公式(12)的系数比公式(13) 的系数小。Comparing equations (12) and (13), it can be found that the ΔV _o of the hybrid analog-to-digital converter circuit described in this patent is lower because ΔV _{o_MAD} is different from the

The ripple voltage ΔV _{o_BUCK} of the discontinuous conduction buck converter circuit (DCM Buck circuit) is proportional to 1/f _sw . In addition, the coefficient of formula (12) is smaller than the coefficient of formula (13).

Figure 4 shows the comparison of the output ripple ΔV _o of the discontinuous conduction step-down converter circuit (DCM Buck circuit) and the hybrid analog-to-digital converter in this embodiment. Among them, the parameters used are as follows: P=1000W, E=400V, V _o =200V. In the hybrid analog-to-digital converter, L ₁ =L ₂ = 1μH, C ₁ =C ₂ =C _L =20μF; discontinuous conduction step-down type In the conversion circuit, L _total = 2μH, and C _total = 60μF.

令NC_bus＝C_L，此时电容总体积最小，得出所需最小 C_L：

其中N为供电电容数量，I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o为负载组件部分等效电阻R_L上输出电压纹波给定的上限值；f_sw为电路开关频率；L为负载组件部分等效电感。The third embodiment is basically the same as the second embodiment, except that the equivalent capacitance _CL of the load component is not limited, and the minimum capacitance values C ₁ , C ₂ , . . . C _N of the power supply capacitors are equal to the DC bus capacitance value C _bus . Calculated by:

Let NC _bus =C _L , at this time the total volume of the capacitor is the smallest, and the required minimum C _L is obtained:

where N is the number of power supply capacitors, I _o is the output current on the equivalent resistance _RL of the load component; V _o is the output voltage on the equivalent resistance _RL of the load component; ΔV _o is the equivalent resistance of the load component _RL The upper limit value given by the upper output voltage ripple; f _sw is the switching frequency of the circuit; L is the partial equivalent inductance of the load component.

Embodiment 4. A hybrid analog-to-digital converter circuit, comprising a power supply and a digital converter connected to the power supply, an analog converter is connected between the input end and the output end of the digital converter, and the analog converter is connected with a load component;

The digital converter includes an element multiplexer connected to the input end and the output end of the power supply through wires, the element multiplexer includes N power supply capacitors arranged in series, the analog converter includes the element multiplexer, and The two ends of each power supply capacitor in the component multiplexer are respectively connected with the input end and the output end of the load component through a discharge wire, and at least one discharge wire is provided with a discharge switch; when the load component is working, the corresponding discharge The switches are alternately connected to the respective supply capacitors. The charging time and discharging time of each power supply capacitor are the circuit switching period T _sw / the number N of power supply capacitors.

Wherein, the load component is equivalent to a load capacitance _CL and a load resistance RL set in parallel and a load inductance _L connected in series with the two connected in parallel;

其中I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o是负载组件部分等效电阻R_L上的输出电压纹波；f_sw是电路开关频率；L 为负载组件部分等效电感；The equivalent capacitance _CL of the load component has been given, and the minimum capacitance values C ₁ , C ₂ , ... C _N of the power supply capacitors are equal to the DC bus capacitance value C _bus , which is calculated by the following formula:

where I _o is the output current on the equivalent resistance _RL of the load component part; V _o is the output voltage on the equivalent resistance _RL of the load component part; ΔV _o is the output voltage ripple on the equivalent resistance _RL of the load component part ; f _sw is the switching frequency of the circuit; L is the partial equivalent inductance of the load component;

The circuit diagram of the hybrid analog-to-digital converter circuit is shown in FIG. 5 : the capacitors C ₁ -C _N are connected in series to form an N:1 voltage divider, which also serves as the capacitor of the DC bus. The equivalent circuits of different working stages are shown in Figure 6, and the waveforms are shown in Figure 7.

Similar to the hybrid analog-to-digital converter circuit based on the buck converter in the above-mentioned embodiment 2, the modulation index M and ΔV _o depend on the charging and discharging circuits, respectively. For a voltage divider, M=1/N; the main difference between Figure 3 and Figure 7 is that the ripple frequency in Figure 7 is Nf _sw and the discharge current of the DC bus capacitor Cbus is (I _o -I _S ). Therefore, ΔV _o in the circuit diagram of the hybrid analog-to-digital converter circuit of this embodiment can be derived from formula (14):

The accuracy of formula (14) can be verified by simulation analysis. Also, the voltage/current from the power supply and the voltage and current from the load (eg, E,is(t), _vL ( _t ), _iL (t)) do not have square waves, see Figure 7 for details. Therefore, the ripple power is very small, so only a small low-pass filter is required.

令NC_bus＝C_L，电容总体积最小，得出所需最小C_L：

其中N为供电电容数量，I_o是负载组件部分等效电阻R_L上的输出电流；V_o是负载组件部分等效电阻R_L上的输出电压；ΔV_o为负载组件部分等效电阻R_L上输出电压纹波；f_sw为电路开关频率。Embodiment 5 is basically the same as Embodiment 4, except that the equivalent capacitance _CL of the load component is not limited, and the minimum capacitance values C ₁ , C ₂ , . . . C _N of the power supply capacitors are equal to the DC bus capacitance value C _bus . Calculated by:

Let NC _bus = C _L , the total volume of the capacitor is the smallest, and the required minimum C _L is obtained:

Where N is the number of power supply capacitors, I _o is the output current on the equivalent resistance _RL of the load component; V _o is the output voltage on the equivalent resistance _RL of the load component; ΔV _o is the equivalent resistance of the load component _RL upper output voltage ripple; f _sw is the switching frequency of the circuit.

The above-mentioned embodiments are only illustrative of the principles and effects of the present invention, as well as some applied embodiments, but are not intended to limit the present invention; it should be pointed out that for those of ordinary skill in the art, without departing from the present invention Under the premise of creating ideas, several modifications and improvements can be made, which all belong to the protection scope of the present invention.

Claims (8)

1. a hybrid analog-digital converter circuit is characterized in that: comprise a power supply and a digital converter connected with the power supply, an analog converter is connected between the input end and the output end of the digital converter, and the analog converter is in phase with the load assembly. connect; The analog converter includes a number of power supply capacitors, and both ends of each power supply capacitor are respectively connected with the input end and the output end of the digital converter through a charging wire, and at least one charging wire is provided with a charging switch; both ends of each power supply capacitor are connected They are all connected to the input end and output end of the load component respectively through the discharge wire, and at least one discharge wire is provided with a discharge switch; when the load component is working, it is connected to each power supply capacitor in turn by closing the corresponding discharge switch, and is not connected to the load. The supply capacitors in the connected state of the components are in turn connected to the digital converter by closing the corresponding charging switches. 2. A hybrid analog-to-digital converter circuit as claimed in claim 1, wherein the load component is equivalent to a load capacitance _CL and a load resistance _RL set in parallel and a parallel connection with the two connected in series. load inductance L; When the partial equivalent capacitance _CL of the load component is given, the minimum capacitance value C ₁ , C ₂ , ... C _N of the power supply capacitor is equal to the DC bus capacitance value C _bus , which is calculated by the following formula:

where I _o is the output current on the equivalent resistance _RL of the load component part; V _o is the output voltage on the equivalent resistance _RL of the load component part; ΔV _o is the output voltage ripple on the equivalent resistance _RL of the load component part The given upper limit value; f _sw is the switching frequency of the circuit; L is the partial equivalent inductance of the load component; When the partial equivalent capacitance _CL of the load component is not limited, the minimum capacitance values C ₁ , C ₂ , . . . C _N of the power supply capacitors are equal to the DC bus capacitance value Cbus. Calculated by:

Let NC _bus = C _L , which gives the required minimum C _L :

where N is the number of power supply capacitors, I _o is the output current on the equivalent resistance _RL of the load component; V _o is the output voltage on the equivalent resistance _RL of the load component; ΔV _o is the equivalent resistance of the load component _RL The upper limit value given by the upper output voltage ripple; f _sw is the switching frequency of the circuit; L is the partial equivalent inductance of the load component. 3. A hybrid analog-to-digital converter circuit according to claim 1, wherein the digital converter is a DC/DC converter. 4 . The hybrid analog-to-digital converter circuit according to claim 3 , wherein the digital converter is a buck converter, a boost converter or a resonant converter. 5 . 5 . The hybrid analog-to-digital converter circuit according to claim 1 , wherein the charging time and discharging time of each power supply capacitor are the circuit switching period Tsw/the number N of power supply capacitors. 6 . 6. A hybrid analog-to-digital converter circuit is characterized in that: comprising a power supply and a digital converter connected with the power supply, an analog converter is connected between the input end and the output end of the digital converter, and the analog converter is in phase with the load component. connect; The digital converter includes an element multiplexer connected to the input end and the output end of the power supply through wires, the element multiplexer includes a plurality of power supply capacitors arranged in series, the analog converter includes the element multiplexer, and the element multiplexer is included. Both ends of each power supply capacitor in the component multiplexer are respectively connected with the input end and the output end of the load component through a discharge wire, and at least one discharge wire is provided with a discharge switch; when the load component is working, the corresponding discharge switch is closed by closing Turn on each power supply capacitor in turn. 7. A hybrid analog-to-digital converter circuit as claimed in claim 6, wherein the load component is equivalent to a load capacitance _CL and a load resistance _RL set in parallel and a parallel connection with the two connected in series. load inductance L; When the partial equivalent capacitance _CL of the load component is given, the minimum capacitance value C ₁ , C ₂ , ... C _N of the power supply capacitor is equal to the DC bus capacitance value C _bus , which is calculated by the following formula:

Among them, N is the number of power supply capacitors, I _o is the output current on the equivalent resistance _RL of the load component; V _o is the output voltage on the equivalent resistance _RL of the load component; ΔV _o is the equivalent resistance of the load component _RL. The upper limit value given by the upper output voltage ripple; f _sw is the switching frequency; L is the partial equivalent inductance of the load component; When the partial equivalent capacitance _CL of the load component is not limited, the minimum capacitance value C ₁ , C ₂ , . . . C _N of the power supply capacitor is equal to the DC bus capacitance value C _bus , which is calculated by the following formula:

Let NC _bus = C _L , we get:

where N is the number of power supply capacitors, I _o is the output current on the equivalent resistance _RL of the load component part; V _o is the output voltage on the equivalent resistance _RL of the load component part; ΔV _o is the equivalent resistance _RL of the load component part of the output voltage The upper limit value given by the output voltage ripple; f _sw switching frequency; L is the partial equivalent inductance of the load component; 8 . The hybrid analog-to-digital converter circuit according to claim 7 , wherein the charging time and discharging time of each power supply capacitor are the circuit switching period T _sw / the number N of power supply capacitors. 9 .

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