CN113992001A

CN113992001A - Configurable charge pump

Info

Publication number: CN113992001A
Application number: CN202111616180.2A
Authority: CN
Inventors: 吴劲; 胡建国; 段志奎; 王德明; 丁颜玉; 邓俊杰; 秦军瑞
Original assignee: Guangdong Yaoxin Technology Co ltd
Current assignee: Guangdong Yaoxin Technology Co ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2022-01-28
Anticipated expiration: 2041-12-28
Also published as: WO2023123829A1; CN113992001B

Abstract

The invention provides a configurable charge pump, which comprises a charge pump module, a clock level conversion module, a comparison module, a high-voltage configuration module and a clock control module, wherein the charge pump module is connected with the clock level conversion module; the clock level conversion module is used for converting the digital clock signal into a first level signal and then sending the first level signal to the clock control module; the first level signal is a clock signal required by the configurable charge pump; the high-voltage configuration module is used for configuring the target voltage of the input end of the comparison module; the comparison module is used for comparing the divided voltage of the output voltage of the charge pump module with a target voltage and sending a second level signal obtained by comparison to the clock control module; the clock control module is used for controlling whether two paths of reverse clock signals are provided for the charge pump module or not according to the first level signal and the second level signal. The configurable charge pump provided by the invention realizes the control of the output voltage of the charge pump module, and avoids the problem that the storage module cannot work normally due to the over-low output voltage of the charge pump module.

Description

Configurable charge pump

Technical Field

The invention relates to the technical field of circuits, in particular to a configurable charge pump.

Background

In the field of modern chip design, the power supply voltage of a chip is mostly concentrated within 10 volts (V), and along with the development trend of low power consumption of the chip, the power supply voltage of the chip is continuously reduced; however, for some special situations, a power supply signal higher than the power supply voltage is needed, for example, when many memory circuits (EEPROM and EFUSE) are designed, a high voltage pulse signal is needed to erase and write the memory circuits, and if a high voltage power supply is designed for the memory circuits alone, chip resources are wasted. The charge pump is a circuit capable of providing the high-voltage signal, and charges and discharges the capacitor repeatedly through two paths of clock signals with opposite phases, so that charges are accumulated on the capacitor continuously to achieve the purpose of boosting.

In the actual design process, the output voltage of the charge pump changes along with the change of the load, and if the power consumption of the load is too large, the output voltage of the charge pump is too low to meet the erasing and writing requirements of the storage circuit; on the contrary, if the load power consumption is too low, the output voltage of the charge pump can be boosted up uncontrollably until the switching tube is cut off due to the body effect, and then the boosting is stopped, so that the service life of the switching tube can be greatly reduced due to the overlarge grid voltage.

In the related art, a comparator circuit is usually added to the output terminal of the charge pump to form a negative feedback loop, so as to limit the rise of the output voltage of the charge pump.

However, in the related art, if the comparator circuit has a process corner, mismatch, or temperature deviation, the output voltage of the charge pump is clamped to a very low voltage, and the output voltage of the charge pump module is too low, which may cause the memory module to fail to operate normally.

Disclosure of Invention

To address the problems of the prior art, the present invention provides a configurable charge pump.

The invention provides a configurable charge pump, which comprises a charge pump module, a clock level conversion module, a comparison module, a high-voltage configuration module and a clock control module, wherein the charge pump module is connected with the clock level conversion module; the clock control module is respectively connected with the clock level conversion module, the comparison module and the charge pump module, and the comparison module is also connected with the charge pump module and the high-voltage configuration module;

the clock level conversion module is used for converting a digital clock signal into a first level signal and then sending the first level signal to the clock control module; the first level signal is a clock signal required by the configurable charge pump;

the high-voltage configuration module is used for configuring the target voltage of the input end of the comparison module;

the comparison module is used for comparing the divided voltage of the output voltage of the charge pump module with the target voltage and sending a second level signal obtained by comparison to the clock control module;

and the clock control module is used for controlling whether two paths of reverse clock signals are provided for the charge pump module or not according to the first level signal and the second level signal.

According to the configurable charge pump provided by the invention, a first input end of the high-voltage configuration module is connected with a reference voltage, a second input end of the high-voltage configuration module is connected with a first power voltage, a third input end of the high-voltage configuration module is connected with a processor, and an output end of the high-voltage configuration module is connected with a first input end of the comparison module; the reference voltage is a voltage signal output by the reference voltage circuit;

the processor is used for sending a first high-voltage configuration signal to the high-voltage configuration module when the output voltage of the charge pump module is determined to be greater than or equal to a preset voltage;

the high-voltage configuration module is specifically configured to determine the reference voltage as a target voltage of the first input terminal of the comparison module when the first high-voltage configuration signal is received.

According to the configurable charge pump provided by the invention, the processor is further configured to send a second high-voltage configuration signal to the high-voltage configuration module when it is determined that the output voltage of the charge pump module is less than the preset voltage;

the high-voltage configuration module is further specifically configured to determine the first power supply voltage as a target voltage of the first input terminal of the comparison module when the second high-voltage configuration signal is received.

According to the configurable charge pump provided by the invention, the clock control module comprises a first switch circuit and a reverse clock generation circuit;

a first input end of the first switch circuit is connected with an output end of the clock level conversion module, a second input end of the first switch circuit is connected with an output end of the comparison module, and an output end of the first switch circuit is connected with a first input end of the reverse clock generation circuit;

the second input end of the reverse clock generation circuit is connected with the processor, and the output end of the reverse clock generation circuit is connected with the charge pump module;

the first switch circuit is used for sending a control signal determined according to the first level signal and the second level signal to the reverse clock generation circuit;

and the reverse clock generation circuit is used for controlling two paths of reverse clock signals of the charge pump module based on the control signal and the enabling signal sent by the processor.

According to the configurable charge pump provided by the invention, the charge pump module comprises a charge pump circuit and a voltage division circuit, wherein the input end of the charge pump circuit is connected with the output end of the reverse clock generation circuit, the output end of the charge pump circuit is connected with the input end of the voltage division circuit, and the output end of the voltage division circuit is connected with the second input end of the comparison module;

and the voltage division circuit is used for dividing the output voltage of the charge pump circuit and then sending the divided voltage to the comparison module.

According to the configurable charge pump provided by the invention, the high-voltage configuration module comprises a transmission gate T1, a transmission gate T2 and a NOT gate F1;

the input terminal of the transmission gate T1 is connected with the reference voltage, the first control terminal of the transmission gate T1 is connected with the processor through the NOT gate F1, and the second control terminal of the transmission gate T1 is connected with the processor;

the input end of the transmission gate T2 is connected to a first power voltage, the first control end of the transmission gate T2 is connected to the processor, the second control end of the transmission gate T2 is connected to the processor through the not gate F1, and the output end of the transmission gate T2 and the output end of the transmission gate T1 are both connected to the first input end of the comparison module.

According to the configurable charge pump provided by the invention, the first switch circuit comprises an AND gate Y1;

a first input end of the and gate Y1 is connected to an output end of the clock level conversion module, a second input end of the and gate Y1 is connected to an output end of the comparison module, and an output end of the and gate Y1 is connected to a first input end of the inverted clock generation circuit.

According to the configurable charge pump provided by the invention, the reverse clock generation circuit comprises a second switch circuit, a first reverse clock generation circuit and a second reverse clock generation circuit;

a first input end of the second switch circuit is connected to an output end of the and gate Y1, a second input end of the second switch circuit is connected to the processor, an output end of the second switch circuit is connected to an input end of the first reverse clock generation circuit and an input end of the second reverse clock generation circuit, and an output end of the first reverse clock generation circuit and an output end of the second reverse clock generation circuit are both connected to an input end of the charge pump module.

According to the invention, a configurable charge pump is provided, the charge pump circuit comprising a plurality of unipolar circuits, each of the unipolar circuits comprising

A plurality of unipolar circuits, each unipolar circuit including an NMOS transistor N1, a PMOS transistor P1, a PMOS transistor P2, and a capacitor C1;

the source electrode of the NMOS transistor N1 is used as a first input end of the unipolar circuit, the grid electrode of the NMOS transistor N1 is connected with the grid electrode of the PMOS transistor P1, and the grid electrode of the NMOS transistor N1 is used as a second input end of the unipolar circuit;

the drain electrode of the NMOS transistor N1 is connected with the source electrode of the PMOS transistor P1, and the drain electrode of the PMOS transistor P1 is used as the output end of the unipolar circuit;

the gate of the PMOS transistor P2 is connected to the charge discharging module, the drain of the PMOS transistor P2 is connected to the first power voltage, the source of the PMOS transistor P2 is connected to the drain of the NMOS transistor N1, the drain of the NMOS transistor N1 is further connected to the first terminal of the capacitor C1, the first terminal of the capacitor C1 is used as the second clock signal terminal of the unipolar circuit, and the second terminal of the capacitor C1 is used as the first clock signal terminal of the unipolar circuit.

According to the configurable charge pump provided by the invention, the comparison module comprises a comparison circuit and a shaping circuit;

the first input end of the comparison circuit is connected with the reference voltage, the second input end of the comparison circuit is connected with the first power supply voltage, the output end of the comparison circuit is connected with the input end of the shaping circuit, and the output end of the shaping circuit is connected with the second input end of the first switch circuit.

According to the configurable charge pump provided by the invention, the target voltage at the input end of the comparison module is configured through the high-voltage configuration module, so that the comparison module outputs a second level signal based on the target voltage and the divided voltage of the output voltage of the charge pump module, a digital clock signal is converted into a first level signal required by the configurable charge pump through the clock level conversion module, and finally, the clock control module determines whether to provide two paths of reverse clock signals for the charge pump module or not based on the first level signal and the second level signal; that is, if it is determined that two reverse clock signals are provided for the charge pump module, the charge pump module starts to charge; if the two reverse clock signals are determined not to be provided for the charge pump module, the charge pump module stops charging, so that the output voltage of the charge pump module is controlled, and the phenomenon that the storage module cannot work normally due to too low output voltage of the charge pump module is avoided.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is one of the schematic block circuit diagrams of a configurable charge pump provided by the present invention;

FIG. 2 is a second schematic block diagram of the configurable charge pump of the present invention;

FIG. 3 is a third schematic block diagram of the configurable charge pump of the present invention;

FIG. 4 is a fourth schematic block diagram of the configurable charge pump of the present invention;

FIG. 5 is a circuit diagram of a high voltage configuration module provided by the present invention;

FIG. 6 is a circuit diagram of a clock control module provided by the present invention;

FIG. 7 is a circuit diagram of a unipolar circuit provided by the present invention;

fig. 8 is a circuit diagram of a charge discharging module provided by the present invention;

FIG. 9 is a circuit diagram of a charge pump module provided by the present invention;

fig. 10 is a circuit diagram of a voltage dividing circuit provided by the present invention;

FIG. 11 is a circuit diagram of a comparison module provided by the present invention;

FIG. 12 is a circuit diagram of a clock level translation module provided by the present invention;

fig. 13 is a circuit diagram of a configurable charge pump provided by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The configurable charge pump of the present invention is described below in conjunction with fig. 1-13.

Fig. 1 is a schematic circuit block diagram of a configurable charge pump according to the present invention, and as shown in fig. 1, the configurable charge pump is mainly applied to some applications requiring high voltage, such as the fields of Electrically Erasable Programmable Read Only Memory (EEPROM) or one-time Programmable memory (Efuse). The configurable charge pump comprises a charge pump module 101, a clock level conversion module 102, a comparison module 103, a high voltage configuration module 104 and a clock control module 105; the clock control module 105 is respectively connected to the clock level conversion module 102, the comparison module 103 and the charge pump module 101, and the comparison module 103 is further connected to the charge pump module 101 and the high voltage configuration module 104.

The clock level conversion module 102 is configured to convert a digital clock signal into a first level signal and send the first level signal to the clock control module 105; the first level signal is a clock signal required by the configurable charge pump.

The high-voltage configuration module 104 is configured to configure a target voltage at an input end of the comparison module 103;

the comparing module 103 is configured to compare the divided voltage of the output voltage of the charge pump module 101 with the target voltage, and send a second level signal obtained by the comparison to the clock control module 105.

The clock control module 105 is configured to control whether to provide two reverse clock signals for the charge pump module 101 according to the first level signal and the second level signal.

Illustratively, the digital clock signal is a signal generated by an external clock module, the voltage amplitude of the digital clock signal is 1.2 volts (V), and the clock level conversion module 102 is configured to convert the digital clock signal into a first level signal (1.5V) and send the first level signal to the clock control module 105; the high-voltage configuration module 104 is used for configuring a corresponding target voltage to the input end of the comparison module 103 based on a signal sent by the processor; and the comparing module 103 is configured to compare the divided voltage of the output voltage of the charge pump module 101 with a target voltage, and send a second level signal obtained by the comparison to the clock control module 105.

The clock control module 105 determines whether to start providing two reverse clock signals for the charge pump module 101 based on the received first level signal and the second level signal, and if it is determined that the configurable charge pump provides two reverse clock signals, the charge pump module 101 starts charging based on the two reverse clock signals; if it is determined that the configurable charge pump is not provided with two reverse clock signals, the charge pump module 101 stops charging, thereby implementing control of the output voltage of the charge pump module 101.

Optionally, fig. 2 is a second schematic circuit block diagram of the configurable charge pump provided in the present invention, as shown in fig. 2, a first input terminal of the high voltage configuration module 104 is connected to a reference voltage, a second input terminal of the high voltage configuration module 104 is connected to a first power voltage, a third input terminal of the high voltage configuration module 104 is connected to a processor, and an output terminal of the high voltage configuration module 104 is connected to a first input terminal of the comparison module 103; the reference voltage is a voltage signal output by the reference voltage circuit.

The processor is configured to send a first high-voltage configuration signal to the high-voltage configuration module 104 when it is determined that the output voltage of the charge pump module 101 is greater than or equal to a preset voltage.

The high voltage configuration module 104 is specifically configured to determine the reference voltage as a target voltage of the first input terminal of the comparison module 103 when the first high voltage configuration signal is received.

Further, the processor is further configured to send a second high-voltage configuration signal to the high-voltage configuration module 104 when it is determined that the output voltage of the charge pump module 101 is less than the preset voltage.

The high voltage configuration module 104 is further specifically configured to determine the first power voltage as a target voltage of the first input terminal of the comparison module 103 when the second high voltage configuration signal is received.

For example, the processor monitors the output voltage of the charge pump module 101 in real time, compares the output voltage of the charge pump module 101 with a preset voltage, and when it is determined that the output voltage of the charge pump module 101 is greater than or equal to the preset voltage, it indicates that the output voltage of the charge pump module 101 is too high, at this time, the processor sends a first high-voltage configuration signal (low-level signal) to the high-voltage configuration module 104, and when the high-voltage configuration module 104 receives the low-level signal, the processor outputs a reference voltage, that is, the reference voltage is used as a target voltage, so that the output voltage of the charge pump module 101 is pulled down by the clamp of the comparison module 103.

When the output voltage of the charge pump module 101 is determined to be less than the preset voltage, it is determined that the output voltage of the charge pump module 101 is lower, at this time, the processor sends a second high-voltage configuration signal (a high-level signal) to the high-voltage configuration module 104, and when the high-voltage configuration module 104 receives the high-level signal, the first power voltage is output, that is, the first power voltage is used as a target voltage, so that the output voltage of the charge pump module 101 is not clamped by the comparison module 103 and rises to a certain value (19V).

According to the configurable charge pump provided by the invention, in order to avoid deviation caused by a process corner and the like, the high-voltage configuration module is used for configuring the target voltage for the input end of the comparison module, so that the condition that the output voltage of the configurable charge pump is clamped too low by the comparison module to cause incapability of erasing and writing when the storage module is in erasing and writing operation is prevented.

Optionally, fig. 3 is a third schematic circuit block diagram of the configurable charge pump provided in the present invention, and as shown in fig. 3, the clock control module 105 includes a first switch circuit and a reverse clock generation circuit.

A first input end of the first switch circuit is connected to an output end of the clock level conversion module 102, a second input end of the first switch circuit is connected to an output end of the comparison module 103, and an output end of the first switch circuit is connected to a first input end of the backward clock generation circuit.

The second input end of the backward clock generation circuit is connected with the processor, and the output end of the backward clock generation circuit is connected with the charge pump module 101.

The first switch circuit is configured to send a control signal determined according to the first level signal and the second level signal to the inverted clock generation circuit.

The backward clock generation circuit is configured to control two backward clock signals of the charge pump module 101 based on the control signal and the enable signal sent by the processor.

For example, for a configurable charge pump, two inverted clock generation circuits are required to support dual voltage supply; the first switch circuit may be an and gate, and is configured to receive the first level signal and the second level signal, and output a corresponding control signal based on high and low levels of the first level signal and the second level signal, where the control signal is used to control whether the reverse clock generation circuit is allowed to generate two opposite clock signals; when the enable signal is a high level signal and the control signal is also a high level signal, two paths of reverse clock signals are allowed to be generated; when the control signal is a low level signal, the two opposite clock signals are turned off, so as to control whether the charge pump module 101 is charged.

The configurable charge pump provided by the invention controls whether the reverse clock generation circuit provides two reverse clock signals for the charge pump module or not through the first switch circuit, thereby realizing the control of the output voltage of the charge pump module.

Optionally, fig. 4 is a fourth schematic block diagram of the configurable charge pump provided in the present invention, as shown in fig. 4, the charge pump module 101 includes a charge pump circuit and a voltage divider circuit, an input end of the charge pump circuit is connected to an output end of the inverted clock generating circuit, an output end of the charge pump circuit is connected to an input end of the voltage divider circuit, and an output end of the voltage divider circuit is connected to a second input end of the comparison module 103.

The voltage dividing circuit is configured to divide the output voltage of the charge pump circuit and send the divided voltage to the comparison module 103.

Illustratively, in fig. 4, the first power voltage is 1.5V, the digital clock signal is an external clock signal and is 1.2V, the clock level conversion module 102 drives the 1.2V clock frequency to be 6.78MHz (megahertz), and when the high-voltage configuration signal is a high-level signal, the first power voltage is supplied to the first input terminal of the comparison module 103; when the high-voltage configuration signal is a low-level signal, the reference voltage is sent to a first input end of the comparison module 103; the output voltage of the charge pump circuit is divided by the voltage dividing circuit and then is sent to the second input end of the comparison module 103; the output of the comparison module 103 can control whether the converted first level signal is sent to two reverse clock generation circuits through a first switch circuit (and gate) to control the output voltage of the charge pump circuit; in addition, the enable signal of the reverse clock generation circuit also controls whether the two reverse clock generation signals provide two reverse clock signals for the charge pump circuit or not so as to achieve the purpose of controlling whether the charge pump circuit works or not.

Alternatively, fig. 5 is a circuit diagram of the high voltage configuration module provided in the present invention, and as shown in fig. 5, the high voltage configuration module 104 includes a transmission gate T1, a transmission gate T2, and a not gate F1.

The input terminal of the transmission gate T1 is connected to the reference voltage, the first control terminal of the transmission gate T1 is connected to the processor through the NOT gate F1, and the second control terminal of the transmission gate T1 is connected to the processor.

The input end of the transmission gate T2 is connected to a first power voltage, the first control end of the transmission gate T2 is connected to the processor, the second control end of the transmission gate T2 is connected to the processor through the not gate F1, and the output end of the transmission gate T2 and the output end of the transmission gate T1 are both connected to the first input end of the comparison module 103.

Illustratively, the high voltage configuration module 104 comprises an inverter (not gate F1) and two transmission gates (transmission gate T1 and transmission gate T2), wherein IN0 IN fig. 5 is connected to the reference voltage generated by the voltage reference circuit, IN1 is connected to the first power voltage, when HV _ setting is configured as the first high voltage configuration signal (low level signal), the reference voltage is connected to the comparison module 103 through the output terminal (OUT terminal), and the output voltage of the charge pump circuit is divided by the voltage dividing circuit and then applied to the comparison module 103, so as to clamp the output voltage of the charge pump circuit at about 15.5V; when HV _ setting is configured as the second high voltage configuration signal (high level signal), the first power voltage is terminated to the comparison module 103 through OUT, and at this time, the output voltage of the charge pump circuit is divided by the voltage dividing circuit and then applied to the comparison module 103, and since the first power voltage has 1.5V (the highest voltage of the output voltage of the charge pump circuit after being divided by the voltage dividing circuit does not exceed 1.5V), the output voltage of the charge pump circuit is pumped to the highest voltage (19V) without being controlled by the comparison module 103.

It should be noted that, HV _ setting, N _ HV _ setting, IN0, IN1, and Vref IN fig. 5 are all network labels, when HV _ setting is high, N _ HV _ setting is a low level signal for controlling the on/off of the transmission gate, Vref is the output voltage of the high voltage configuration module 104, and Vref may be the power supply voltage VDDA or the reference voltage Vref.

Alternatively, fig. 6 is a circuit diagram of the clock control module provided in the present invention, and as shown in fig. 6, the first switch circuit includes an and gate Y1.

A first input end of the and gate Y1 is connected to the output end of the clock level conversion module 102, a second input end of the and gate Y1 is connected to the output end of the comparison module 103, and an output end of the and gate Y1 is connected to the first input end of the inverted clock generation circuit.

The charge pump circuit provided by the invention takes the AND gate Y1 as a switch to control whether the reverse clock generating circuit provides two reverse clock signals for the charge pump circuit or not, namely whether the charge pump circuit is charged or not, thereby realizing the control of the output voltage of the charge pump circuit.

Optionally, as shown in fig. 6, the reverse clock generating circuit includes a second switching circuit, a first reverse clock generating circuit, and a second reverse clock generating circuit.

A first input end of the second switch circuit is connected to an output end of the and gate Y1, a second input end of the second switch circuit is connected to the processor, output ends of the second switch circuit are respectively connected to an input end of the first reverse clock generation circuit and an input end of the second reverse clock generation circuit, and output ends of the first reverse clock generation circuit and the second reverse clock generation circuit are both connected to an input end of the charge pump module 101.

The configurable charge pump provided by the invention generates two reverse clock signals through the first reverse clock generating circuit and the second reverse clock generating circuit so as to meet the charging requirement of the charge pump circuit.

Optionally, as shown in fig. 6, the second switch circuit includes a nand gate YF1, the first way of inverted clock generating circuit includes a transmission gate T3, a first nor gate HF1, and a first driving circuit, and the second way of inverted clock generating circuit includes a not gate F2, a nor gate HF2, and a second driving circuit.

An input terminal of the transmission gate T3 is connected to an output terminal of the nand gate YF1, a first control terminal of the transmission gate T3 is connected to a first power supply voltage, a second control terminal of the transmission gate T3 is grounded, an output terminal of the transmission gate T3 is connected to a first input terminal of the first nor gate HF1, a second input terminal of the first nor gate HF1 is connected to an output terminal of the nor gate HF2, and an output terminal of the first nor gate HF1 is connected to an input terminal of the first driving circuit.

An input end of the not gate F2 is connected with an output end of the nand gate YF1, an output end of the not gate F2 is connected with a first input end of the nor gate HF2, a second input end of the nor gate HF2 is connected with an output end of the first nor gate HF1, an output end of the nor gate HF2 is connected with an input end of the second driving circuit, and an output end of the second driving circuit and an output end of the first driving circuit are both connected with the charge pump circuit.

For example, in fig. 6, in order to avoid the propagation delay caused by the transmission gate T3 and the inverter (second nand gate) and to make an impression on the phase of the two inverted clocks, an SR flip-flop consisting of a first nor gate HF1 and a nor gate HF2 is designed to generate two inverted non-overlapping clock signals.

In addition, as shown in fig. 6, the first driving circuit includes a not gate F3, a not gate F4, and a not gate F5, wherein an input terminal of the not gate F3 is connected to an output terminal of the first nor gate HF1, an output terminal of the not gate F3 is connected to an input terminal of the nand gate F4, an output terminal of the not gate F4 is connected to an input terminal of the nand gate F5, and an output terminal of the not gate F5 is connected to the charge pump circuit as a reverse clock signal.

As shown in fig. 6, the second driving circuit includes a not gate F6, a not gate F7, and a not gate F8, wherein an input terminal of the not gate F6 is connected to an output terminal of the nor gate HF2, an output terminal of the not gate F6 is connected to an input terminal of the nand gate F7, an output terminal of the not gate F7 is connected to an input terminal of the nand gate F8, and an output terminal of the not gate F8 is connected to the charge pump circuit as another inverted clock signal.

It should be noted that the first driving circuit and the second driving circuit are both used for increasing the driving capability of the corresponding inverted clock signal.

It should be noted that DPXH, CLK _ EN, HV _ EN, CP _ CLK, and CP _ CLKN in fig. 6 are all network labels; the DPXH represents a first level signal output by the clock level conversion circuit, CLK _ EN represents a second level signal output by the comparison module 103, an enable signal sent by the HV _ EN processor, and CP _ CLK and CP _ CLKN represent two paths of inverted clock signals, which are both connected with the input end of the charge pump circuit.

Alternatively, fig. 7 is a circuit diagram of a unipolar circuit provided by the present invention, and as shown in fig. 7, the charge pump circuit includes a plurality of unipolar circuits, each of which includes an N-Metal-Oxide-Semiconductor (NMOS) transistor N1, a P-Metal-Oxide-Semiconductor (PMOS) transistor P1, a PMOS transistor P2, and a capacitor C1.

The source electrode of the NMOS transistor N1 is used as a first input end of the unipolar circuit, the grid electrode of the NMOS transistor N1 is connected with the grid electrode of the PMOS transistor P1, and the grid electrode of the NMOS transistor N1 is used as a second input end of the unipolar circuit; the drain electrode of the NMOS transistor N1 is connected with the source electrode of the PMOS transistor P1, and the drain electrode of the PMOS transistor P1 is used as the output end of the unipolar circuit; the gate of the PMOS transistor P2 is connected to the charge discharging module, the drain of the PMOS transistor P2 is connected to the first power voltage, the source of the PMOS transistor P2 is connected to the drain of the NMOS transistor N1, the drain of the NMOS transistor N1 is further connected to the first terminal of the capacitor C1, the first terminal of the capacitor C1 is used as the second clock signal terminal of the unipolar circuit, and the second terminal of the capacitor C1 is used as the first clock signal terminal of the unipolar circuit.

Illustratively, with a typical dickson charge pump structure, the charge pump circuit may be composed of 32 unipolar circuits, each unipolar circuit is shown in fig. 7, where CK is a first clock signal terminal connected to the output terminal of the inverted clock generating circuit, VCK is a second clock signal terminal, VOUT is an output terminal of the unipolar circuit, VIN _1 is a first input terminal of the unipolar circuit, VIN _2 is a second input terminal of the unipolar circuit, and discharge is a signal output by the charge discharging module, when discharge is a low-level signal, the configurable charge pump is forced not to additionally charge, and the charge on the configurable charge pump is discharged through the charge discharging module, so that the output voltage of the configurable charge pump is equal to the first power supply voltage VDDA.

In addition, the load capacity of the charge pump circuit is related to the first power supply voltage VDDA, the clock frequency and the size of the capacitor C1, in the design, the change range of the first power supply voltage VDDA is 1.35V-1.65V, the minimum clock frequency is 6.78MHz, and therefore, only the capacitance value of the capacitor C1 can be adjusted. In addition, when layout design is carried out, devices can be stacked under the capacitor C1, and three switching tubes (an NMOS tube N1, a PMOS tube P1 and a PMOS tube P2) in the unipolar circuit are placed under the capacitor C1, so that the layout area of the unipolar circuit is reduced, and the layout area of the charge pump circuit can be further greatly saved.

It should be noted that, when the configurable charge pump is not used, in order to quickly release the charge on the configurable charge pump, so that the output voltage VHH of the charge pump circuit is pulled to VDDA, the enable signal of the reverse clock generation circuit also controls the charge release module, fig. 8 is a circuit diagram of the charge release module provided by the present invention, as shown in fig. 8, when the enable signal HV _ EN is pulled to a low level, the reverse clock generation circuit of the configurable charge pump is turned off, the output voltage VHH of the charge pump circuit will not add any charge, and at this time, VHH will start to drop, but if there is no leakage path, VHH can only release the charge through the sub-threshold conductive path of the MOS transistor, VHH can drop to the 1.5V level of VDDA _1P2V after a long period of time, and in order to accelerate the process of VHH releasing the charge, the charge release module is designed here.

When HV _ EN is at low level, the discharge signal output by the charge release module is also at low level, then the PMOS tube connected with VDDA _1P2V is conducted to short circuit VHH and VDDA _1P2V, VHH will rapidly release charges through VDDA _1P2V, VHH can drop to 1.5V level of VDDA _1P2V in a short time; the resistor in fig. 8 functions as a current limiting protection.

When HV _ EN is at a high level, the discharge output by the charge discharging module rises with the rise of the output voltage of the charge pump circuit, so as to maintain the high voltage of VHH, and turn off the PMOS transistor connected to VDDA _1P2V (due to the characteristics of the PMOS transistor, when the PMOS transistor is turned off, the gate voltage must be greater than the source voltage of the PMOS transistor), at this time, the VHH signal is disconnected from VDDA _1P2V, the configurable charge pump starts to add charges, and VHH starts to rise.

It should be noted that fig. 9 is a circuit diagram of the charge pump module provided in the present invention, and the connection relationship between the plurality of unipolar circuits is as shown in fig. 9, for example, the number of unipolar circuits is 32, and the 32 unipolar circuits are divided into 16 stages, each stage includes two unipolar circuits, which are respectively a first unipolar circuit and a second unipolar circuit.

For a first group of unipolar circuits, a first clock signal end of each first unipolar circuit is connected with one path of reverse clock signals, a first input end of each first unipolar circuit is connected with a first power voltage, a second input end of each first unipolar circuit is connected with a second clock signal end of each second unipolar circuit, a second clock signal end of each first unipolar circuit is connected with a second input end of each second unipolar circuit, and an output end of each first unipolar circuit is connected with a first input end of a corresponding unipolar circuit in an adjacent second group of unipolar circuits; the first clock signal terminal of the second unipolar circuit is connected to the other inverted clock signal, the first input terminal of the second unipolar circuit is connected to the first power supply voltage, and the output terminal of the second unipolar circuit is connected to the first input terminal of the corresponding unipolar circuit of the adjacent second group of unipolar circuits. Referring to fig. 9, in fig. 9, CP _ CLK and CP _ CLKN are connected to an output terminal of the first driving circuit and an output terminal of the second driving circuit, respectively.

The configurable charge pump reduces the layout area of the charge pump circuit, reserves the area of a published graph for the high-voltage configuration module and the clock level conversion module, and does not change the layout area of the whole configurable charge pump as far as possible.

Optionally, fig. 10 is a circuit diagram of the voltage divider circuit provided by the present invention, and as shown in fig. 10, the voltage divider circuit includes a capacitor C2, a capacitor C3, a capacitor C4, and a capacitor C5, one end of the capacitor C2 is connected to an output end of the charge pump circuit, the other end of the capacitor C2 is connected to one end of the capacitor C5 sequentially through the capacitor C3 and the capacitor C4, the other end of the capacitor C5 is grounded, and the connection between the capacitor C4 and the capacitor C5 is used as an output end of the voltage divider circuit and connected to the second input end of the comparison module 103.

Illustratively, the voltage dividing circuit is composed of a capacitor C2, a capacitor C3, a capacitor C4 and a capacitor C5, the connection between the capacitor C4 and the capacitor C5 is used as an output end of the voltage dividing circuit, a sampling voltage of the output voltage of the charge pump circuit is divided, and the sampling voltage is input to the comparing module 103, so that the comparing module 103 determines whether to clamp the output voltage of the charge pump circuit based on the sampling voltage and a target voltage.

In fig. 10, VHH denotes an output voltage of the charge pump circuit, c0 denotes a divided voltage of the output voltage, and GDNA denotes ground.

Alternatively, fig. 11 is a circuit diagram of a comparing module provided by the present invention, and as shown in fig. 11, the comparing module 103 includes a comparing circuit and a shaping circuit.

Optionally, the comparison circuit includes an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, a PMOS transistor P3, a PMOS transistor P4, and a PMOS transistor P5.

The grid electrode of the NMOS transistor N2 is connected with the reference voltage, the source electrode of the NMOS transistor N2 is respectively connected with the source electrode of the NMOS transistor N3 and the drain electrode of the NMOS transistor N4, and the drain electrode of the NMOS transistor N2 is respectively connected with the source electrode of the PMOS transistor P3, the grid electrode of the PMOS transistor P3 and the grid electrode of the PMOS transistor P4; the grid electrode of the NMOS tube N3 is connected with the output end of the voltage division circuit, and the drain electrode of the NMOS tube N3 is respectively connected with the source electrode of the PMOS tube P4 and the grid electrode of the PMOS tube P5; the drain electrode of the PMOS tube P3, the drain electrode of the PMOS tube P4 and the drain electrode of the PMOS tube P5 are all connected with a first power supply voltage, the source electrode of the PMOS tube P5 is connected with the drain electrode of the NMOS tube N5, and the source electrode of the PMOS tube P5 is used as the output end of the comparison circuit; the grid electrode of the NMOS transistor N4 and the grid electrode of the NMOS transistor N5 are both connected with the output end of the reference voltage circuit, and the source electrode of the NMOS transistor N4 and the source electrode of the NMOS transistor N5 are both grounded.

Optionally, as shown in fig. 11, the shaping circuit includes a PMOS transistor P6 and an NMOS transistor N6.

The drain electrode of the PMOS tube P6 is connected with a first power supply voltage, and the gate electrode of the PMOS tube P6 is respectively connected with the source electrode of the PMOS tube P5 and the gate electrode of the NMOS tube N6; the source of the PMOS transistor P6 is connected to the drain of the NMOS transistor N6, the source of the PMOS transistor P6 is used as the output terminal of the comparison module 103, and the source of the NMOS transistor N6 is grounded.

For example, in order to stabilize the output voltage of the charge pump circuit, as shown in fig. 9, the comparison module 103 adopts a conventional two-stage open-loop comparator structure, the Bandgap _ out voltage is about 540 millivolts (mV), the Bandgap _ out voltage can be given by a reference voltage circuit of the analog portion, and the divided voltage obtained by dividing the output voltage (i.e., the high-voltage signal) generated by the charge pump circuit by a plurality of capacitors is c 0; when the processor sends a low-level high-voltage configuration signal to the high-voltage configuration module 104, c0 is compared with vref, and when c0 is greater than vref, the output clk _ en of the comparison module 103 is output at a low level and acts on the reverse clock generation circuit, at this time, the reverse clock generation circuit is turned off, so that the output voltage generated by the charge pump circuit is stabilized at 15.5V.

The vref value is controlled by the high voltage configuration module 104, and the HV _ Setting signal is configured to determine the magnitude of the vref value (when HV _ Setting is high, vref is the first power voltage, and when HV _ Setting is low, vref is the reference voltage), so as to avoid the situation that the output voltage of the charge pump circuit is clamped too low by the comparison module 103.

According to the configurable charge pump provided by the invention, the comparison module is additionally arranged at the output end of the charge pump circuit to form a negative feedback loop so as to limit the rise of the output voltage of the charge pump circuit; meanwhile, in order to avoid the situation that the output voltage is clamped to a very low voltage by the comparison module due to process angle, mismatch, temperature and other deviations, the target voltage at the input end of the comparison module is configured by the high-voltage configuration module.

Alternatively, fig. 12 is a circuit diagram of the clock level conversion module provided by the present invention, and as shown in fig. 12, the clock level conversion module 102 includes a PMOS transistor P7, a PMOS transistor P8, a PMOS transistor P9, an NMOS transistor N7, an NMOS transistor N8, and an NMOS transistor N9.

The grid electrode of the PMOS pipe P7 is connected with the digital clock signal, and the drain electrode of the PMOS pipe P7 is respectively connected with the source electrode of the NMOS pipe N7 and the grid electrode of the NMOS pipe N8; the drain of the NMOS transistor N7 and the drain of the NMOS transistor N8 are both connected to a first power voltage, the gate of the NMOS transistor N7 is connected to the source of the NMOS transistor N8, and the source of the NMOS transistor N8 is used as the output terminal of the clock level shifter module 102; the drain electrode of the PMOS tube P8 is connected with the source electrode of the NMOS tube N8, and the gate electrode of the PMOS tube P8 is respectively connected with the source electrode of the NMOS tube N9 and the drain electrode of the PMOS tube P9; the grid electrode of the NMOS transistor N9 and the grid electrode of the PMOS transistor P9 are both connected with the grid electrode of the PMOS transistor P7, and the drain electrode of the NMOS transistor N9 is connected with a second power supply voltage; the source electrode of the PMOS transistor P7, the source electrode of the PMOS transistor P8 and the source electrode of the PMOS transistor P9 are all grounded.

For example, as shown IN fig. 12, an input terminal IN of the clock level conversion module 102 receives an external 1.2V digital clock signal, and a 1.5V first level signal can be obtained after passing through the clock level conversion module 102, that is, an output terminal at OUT outputs 1.5V, so that switching of a clock voltage domain is realized, and the driving capability of the configurable charge pump is increased without changing the layout area of the configurable charge pump.

Alternatively, fig. 13 is a circuit diagram of a configurable charge pump provided in the present invention, and as shown in fig. 13, the operation principle of the configurable charge pump is as follows:

the clock level conversion module 102 may convert a 1.2V digital clock signal into a 1.5V clock signal required by the charge pump circuit, generate two reverse clock signals to the charge pump circuit after passing through two reverse clock generation circuits, start charging the charge pump circuit with the two reverse clock signals after the enable switch HV _ EN is turned on, divide the voltage when the output voltage of the charge pump circuit rises by a capacitor, compare the divided voltage c0 with a reference voltage or a first power voltage, and control the selection of the reference voltage and the first power voltage by the processor.

The processor monitors the output voltage of the charge pump circuit in real time, compares the output voltage of the charge pump circuit with a preset voltage, and when the output voltage of the charge pump circuit is determined to be greater than or equal to the preset voltage, the processor sends a first high-voltage configuration signal (low level signal) to the high-voltage configuration module 104, when the high-voltage configuration module 104 receives the low level signal, the reference voltage Vref is input to the reverse input end of the comparison module 103, the voltage division c0 of the output voltage of the charge pump circuit is connected with the non-inverting input end of the comparison module 103, and when c0 is greater than Vref, the comparison module 103 outputs a low level, the AND gate Y1 closes the reverse clock generation circuit, and does not provide two-way reverse clock signals for the charge pump circuit, so that the output voltage of the charge pump circuit is clamped by the comparison module 103 and is stabilized at 15.5V.

When the load of the configurable charge pump changes, if the output voltage of the charge pump circuit begins to drop, the processor sends a second high-voltage configuration signal (high-level signal) to the high-voltage configuration module 104 when determining that the output voltage of the charge pump circuit is less than the preset voltage, the high-voltage configuration module 104 inputs a first power supply voltage VDDA to the inverting input terminal of the comparison module 103 when receiving the high-level signal, the divided voltage c0 of the output voltage of the charge pump circuit is connected to the non-inverting input terminal of the comparison module 103, since VDDA is 1.5V, c0 is about 640mV, therefore VDDA is greater than c0, the comparison module 103 outputs high level, and the and gate Y1 turns on the backward clock generation circuit to provide two-way backward clock signals for the charge pump circuit, the output voltage of the charge pump circuit is not clamped by the comparison module 103 and rises to 19V, so that the output voltage of the charge pump circuit does not change along with the load.

In order to avoid the situation that the output voltage of the charge pump circuit is clamped at a voltage lower than 15.5V required by design due to process corners, mismatch and the like, a special configuration is performed on the comparison module 103, namely the high-voltage configuration module 104 is controlled by the HV _ Setting signal, and when the HV _ Setting is at a high level, the output voltage of the charge pump circuit does not rise to 19V under the clamping; when HV _ setting is low, the comparing module 103 is clamped by the reference voltage, so that the output voltage of the charge pump circuit is stabilized at 15.5V. Thus, by combining the clock level conversion module 102 and the high voltage configuration module 104, the digital clock voltage for the configurable charge pump to work can be increased from 1.2V to 1.5V, and the driving capability of the configurable charge pump is improved without changing the area of the configurable charge pump; meanwhile, the high-voltage configuration module 104 avoids the risk of the current slice failure caused by the output voltage of the charge pump circuit being clamped too low by the comparison module 103.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A configurable charge pump is characterized by comprising a charge pump module, a clock level conversion module, a comparison module, a high-voltage configuration module and a clock control module; the clock control module is respectively connected with the clock level conversion module, the comparison module and the charge pump module, and the comparison module is also connected with the charge pump module and the high-voltage configuration module;

2. The configurable charge pump of claim 1, wherein a first input of the high voltage configuration module is connected to a reference voltage, a second input of the high voltage configuration module is connected to a first supply voltage, a third input of the high voltage configuration module is connected to a processor, and an output of the high voltage configuration module is connected to a first input of the comparison module; the reference voltage is a voltage signal output by the reference voltage circuit;

3. The configurable charge pump of claim 2,

the processor is further configured to send a second high-voltage configuration signal to the high-voltage configuration module when it is determined that the output voltage of the charge pump module is less than the preset voltage;

4. The configurable charge pump of claim 2, wherein the clock control module comprises a first switching circuit and an inverted clock generation circuit;

5. The configurable charge pump of claim 4, wherein the charge pump module comprises a charge pump circuit and a voltage divider circuit, an input of the charge pump circuit is connected to an output of the inverted clock generation circuit, an output of the charge pump circuit is connected to an input of the voltage divider circuit, and an output of the voltage divider circuit is connected to the second input of the comparison module;

6. The configurable charge pump of claim 2, wherein said high voltage configuration module comprises transmission gate T1, transmission gate T2, and not gate F1;

7. The configurable charge pump of claim 4, wherein said first switching circuit comprises an AND gate Y1;

8. The configurable charge pump of claim 7, wherein the reverse clock generating circuit comprises a second switching circuit, a first reverse clock generating circuit and a second reverse clock generating circuit;

9. The configurable charge pump of claim 5, wherein said charge pump circuitry comprises a plurality of unipolar circuits, each said unipolar circuit comprising an NMOS transistor N1, a PMOS transistor P1, a PMOS transistor P2, and a capacitor C1;

10. The configurable charge pump of claim 5, wherein the comparison module comprises a comparison circuit and a shaping circuit;