CN113991285A - Packaged antenna, packaged chip and antenna-on-chip system - Google Patents
Packaged antenna, packaged chip and antenna-on-chip system Download PDFInfo
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- CN113991285A CN113991285A CN202111305384.4A CN202111305384A CN113991285A CN 113991285 A CN113991285 A CN 113991285A CN 202111305384 A CN202111305384 A CN 202111305384A CN 113991285 A CN113991285 A CN 113991285A
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- 229910000679 solder Inorganic materials 0.000 claims abstract description 56
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- 229910052751 metal Inorganic materials 0.000 claims description 51
- 230000008054 signal transmission Effects 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 38
- 238000012858 packaging process Methods 0.000 abstract description 6
- 238000009517 secondary packaging Methods 0.000 abstract description 3
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- 229910052737 gold Inorganic materials 0.000 description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Details Of Aerials (AREA)
Abstract
The invention discloses a packaged antenna, a packaged chip and an on-chip antenna system, wherein the packaged antenna comprises: the first dielectric substrate and the second dielectric substrate are oppositely arranged; the antenna units are arranged on the surface of the first dielectric substrate far away from the second dielectric substrate at intervals; the grounding plate is arranged between the first dielectric substrate and the second dielectric substrate; at least one feed through hole penetrates through the first dielectric substrate, the grounding plate and the second dielectric substrate; and the at least one first solder ball is arranged on the surface of the second dielectric substrate far away from the first dielectric substrate, wherein each antenna unit in the at least one antenna unit is electrically connected with one first solder ball through one feed through hole. The invention can independently package the antenna module and the chip module, so that the antenna module has the capability of secondary packaging, the packaging process is simplified, the packaging cost is reduced, the flexibility of the on-chip antenna application is enhanced, and different application scenes can be compatible.
Description
Technical Field
The invention relates to the technical field of antennas, in particular to a packaged antenna, a packaged chip and an on-chip antenna system.
Background
With the development of millimeter wave technology, millimeter wave antennas and radars are applied more and more. With the improvement of processing and preparation processes, the product has higher integration level and smaller volume. The on-chip antenna is designed on a wafer, an integrated circuit and a chip (such as a radio frequency chip), has the characteristics of high integration level, compact structure and fineness, and breaks through the mode of independently designing and re-integrating the traditional antenna, an active circuit and a component.
The existing integration and packaging methods for the chip and the antenna are mainly divided into on-chip integration and on-chip integration, that is, the antenna is integrated into the package of the chip or the antenna is integrated on the top of the package of the chip. For on-chip integration, the antenna is designed primarily on the redistribution layer (RDL) of the chip package structure, or inside the chip package mold; for on-chip integration, the antenna is designed primarily on the top layer of the chip package mold, with the chip feeding the antenna through the vias.
For the on-chip integration mode of designing the antenna on the RDL, if the chip has multiple transmitting ports and multiple receiving ports, the packaging volume of the final chip will increase greatly, and the chip packaging cost is high. And most of the on-chip antennas are independently completed by a packaging factory, the chip and the antenna belong to a customized structure, once the packaging is completed, the on-chip antenna system is shaped, and the requirements of different use scenes on the antenna are different, so that the on-chip antenna formed by adopting the scheme is difficult to be compatible with a plurality of application scenes, the application requirements of the plurality of scenes are met, and then a plurality of types of packaged antennas need to be developed, which can lead to the increase of hardware cost. For the on-chip integration form of designing the antenna on the top of the chip package mold, the feed line of the antenna needs to pass through the via hole, and the loss is high.
However, the on-chip antennas have low gains and can only be applied to short-distance scene detection requirements, and in order to meet the long-distance detection requirements, only the form of the antenna needs to be changed, and the structure of the chip does not need to be changed. And the fixed encapsulated antenna application layer client can not develop the hardware for the second time, which limits the development of the application layer client.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a packaged antenna, a packaged chip and an antenna-on-chip system, which can independently package an antenna module and a chip module, so that the antenna module has the capability of secondary packaging, the packaging process is simplified, the packaging cost is reduced, the flexibility of the antenna-on-chip application is enhanced, and different application scenes can be compatible.
According to a first aspect of the present disclosure, there is provided a packaged antenna comprising: the first dielectric substrate and the second dielectric substrate are oppositely arranged;
the antenna units are arranged on the surface of the first dielectric substrate far away from the second dielectric substrate at intervals;
the grounding plate is arranged between the first dielectric substrate and the second dielectric substrate;
at least one feed via passing through the first dielectric substrate, the ground plate and the second dielectric substrate;
at least one first solder ball arranged on the surface of the second dielectric substrate far away from the first dielectric substrate,
each antenna unit in the at least one antenna unit is electrically connected with one first solder ball through one feed through hole.
Optionally, the packaged antenna further includes:
and the rewiring layer comprises at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer, and is arranged between the first dielectric substrate and the grounding plate or between the grounding plate and the second dielectric substrate.
Optionally, a via hole connecting the metal wiring layer is formed in the rewiring layer.
According to a second aspect of the present disclosure, there is provided a packaged chip comprising: a package substrate;
a chip die disposed on the first surface of the package substrate;
a package mold encapsulating the chip die;
at least one metal via molded through the package and connected to leads of the chip die proximate an end of the package substrate;
a plurality of second solder balls disposed on a second surface of the package substrate opposite the first surface,
when the packaged chip is electrically connected to the packaged antenna, the at least one metal through hole of the packaged chip is electrically connected to the at least one first solder ball of the packaged antenna in a one-to-one correspondence manner.
Optionally, a diameter of an end of each of the at least one metal via, which is far away from the package substrate, is larger than a diameter of an end of the metal via, which is close to the package substrate.
According to a third aspect of the present disclosure, there is provided an on-chip antenna system comprising: a packaged antenna as described above; and
the chip is packaged as described above in a package,
the at least one metal through hole of the packaged chip is electrically connected with the at least one first solder ball of the packaged antenna so as to realize signal transmission between the packaged chip and the packaged antenna.
Optionally, a diameter of an end of each of the at least one metal via, which is far away from the package substrate, is smaller than a diameter of the corresponding electrically connected first solder ball, so that when the at least one metal via is electrically connected with the at least one first solder ball, each first solder ball is at least partially located outside the metal via.
Optionally, the packaged antenna further includes:
and the supporting unit is arranged on the surface of the second medium substrate far away from the first medium substrate, and the bottom end of the supporting unit is flush with the bottom end of the at least one first solder ball.
Optionally, the supporting unit is a plurality of bumps arranged at intervals.
Optionally, when the number of the first solder balls is two or more, at least one bump is disposed between every two adjacent first solder balls.
Optionally, the bump is a ball bump or a stud bump.
Optionally, a diameter of one end of each of the at least one metal through hole, which is far away from the package substrate, is larger than a diameter of the corresponding electrically connected first solder ball, so that when the at least one metal through hole is electrically connected with the at least one first solder ball, each first solder ball is located inside the metal through hole.
The beneficial effects of the invention at least comprise:
according to the packaged antenna disclosed by the invention, the first solder balls are added at the feed through holes corresponding to the antenna, and then the connection or separation with the chip can be easily realized based on the first solder balls, so that the packaged antenna can have the capability of secondary packaging, a client of an antenna application layer can be facilitated to carry out secondary development on hardware, the flexibility and compatibility of antenna application are enhanced, and the independent packaging of the antenna can be realized.
According to the packaging chip disclosed by the invention, the metal through holes corresponding to the first solder balls of the packaging antenna are arranged on the packaging molding, so that the packaging with the packaging antenna can be realized under the wire after the chip packaging is finished, the packaging chip is not limited in a packaging factory, and the packaging cost is reduced. Meanwhile, the flexibility and compatibility of chip application are enhanced, and independent packaging of the chip can be realized.
The on-chip antenna system disclosed by the invention adopts the modularized packaged antenna and the packaged chip, wherein the packaged antenna can be manufactured by a PCB (printed circuit board) factory, the cost is obviously reduced, the packaged chip is completed by a chip packaging company, and then the corresponding on-chip antenna system can be obtained after offline assembly, so that the packaging process is simplified, the packaging cost is reduced, the flexibility of the application of the on-chip antenna is enhanced, and different application scenes can be compatible.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
Fig. 1 is a schematic structural diagram of a packaged antenna provided in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of a packaged chip according to an embodiment of the present invention;
fig. 3 shows a schematic structural diagram of an antenna-on-chip system provided according to a first embodiment of the present invention;
fig. 4 is a schematic structural diagram of an antenna-on-chip system according to a second embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Fig. 1 shows a schematic structural diagram of a packaged antenna provided in the present invention. The packaged antenna 10 is manufactured by using a BGA (Ball Grid Array) packaging technology, for example, the antenna is designed on an independent PCB (Printed Circuit Board) Board, so that the antenna module in the antenna-on-chip system is independently packaged. Meanwhile, the packaged antenna 10 designed on the PCB is independent, can support batch customization and secondary development, and further can meet various scene requirements, so that a client of an application layer can flexibly design the antenna according to own use requirements.
In one possible embodiment of the invention, the packaged antenna 10 comprises: a first dielectric substrate 11, a ground plane 12, a second dielectric substrate 13, at least one antenna element 14, at least one feed via 15 and at least one first solder ball 16.
The first dielectric substrate 11 and the second dielectric substrate 13 are disposed opposite to each other.
In this embodiment, the first dielectric substrate 11 is a top dielectric substrate of the package antenna 10, and the second dielectric substrate 13 is a bottom dielectric substrate of the package antenna 10. In this embodiment, since the packaged antenna 10 is disposed on a separate PCB, the packaging of the antenna can be not limited to a chip packaging factory. Furthermore, the dielectric substrate used in the packaged antenna 10 according to the embodiment of the present invention may be a low-loss dielectric substrate such as a multilayer laminated board, and compared with a chip packaging factory that uses a packaging template, the cost of packaging a PCB substrate is lower, so that the packaging cost is reduced.
Further, the packaged antenna 10 of the present invention is disposed on a PCB board, and the packaged antenna 10 shown in fig. 1 is only an exemplary drawing drawn by way of example of a simple embodiment having a two-layer dielectric substrate. It should be understood that in other embodiments of the present invention, the dielectric substrate in the packaged antenna 10 may also be a multilayer structure with three or more layers. When the dielectric substrate in the package antenna 10 is a multi-layer structure, at least a portion of the circuit structure that is configured with the antenna unit 14 and the package antenna 10 may be integrated together in a package structure, which is further helpful to save the occupied area of other peripheral circuits.
In this embodiment, the dielectric substrates and the circuit structures except for the first dielectric substrate 11 and the second dielectric substrate 13 in the package antenna 10 are collectively referred to as a redistribution layer, and the redistribution layer includes at least one metal wiring layer (corresponding to a package layer of the circuit structure integrated in the package antenna 10) and a dielectric layer wrapping the metal wiring layer (corresponding to a package layer of the dielectric substrate except for the first dielectric substrate 11 and the second dielectric substrate 13 in the package antenna 10). The rewiring layer is located between the first dielectric substrate 11 and the second dielectric substrate 13, and may be specifically disposed between the first dielectric substrate 11 and the ground plate 12, or between the ground plate 12 and the second dielectric substrate 13.
Further, a via hole connecting the metal wiring layers is also formed in the rewiring layer.
The ground plate 12 is disposed between the first dielectric substrate 11 and the second dielectric substrate 13. In this embodiment, the ground plate 12 is, for example, a metal plate such as a copper clad plate. The ground plane 12 may provide for reflection of electromagnetic radiation, thereby enhancing the reception of electromagnetic radiation by the antenna element 14.
At least one antenna unit 14 is arranged on the surface of the first dielectric substrate 11 far away from the second dielectric substrate 13 at intervals. Preferably, at least one antenna unit 14 is disposed on the surface of the first dielectric substrate 11 at equal intervals, for example. In addition, the type and structure of the at least one antenna unit 14 are not limited in the present invention, and may be reasonably customized according to the actual application requirements.
At least one feed via 15 extends through the first dielectric substrate 11, the ground plane 12 and the second dielectric substrate 13. In this embodiment, the number of the feed vias 15 is equal to and corresponds to the number of the antenna elements 14 on the first dielectric substrate 11, and one end of each feed via 15 close to the first dielectric substrate 11 is electrically connected to a feed point on one antenna element 14, so as to implement feeding, i.e., electrical signal transmission, of the antenna elements 14. It will be appreciated that each feed via 15 is a metallised via.
At least one first solder ball 16 is disposed on a surface of the second dielectric substrate 13 away from the first dielectric substrate 11. In this embodiment, the number of the first solder balls 16 is equal to the number of the feed vias 15 and the number of the antenna units 14 on the first dielectric substrate 11, and the first solder balls 16 are in one-to-one correspondence, and each antenna unit of the at least one antenna unit 14 is electrically connected to one first solder ball 16 through one feed via 15. In the present embodiment, the first solder balls 16 are made of a metal material having electrical connection properties.
In another possible embodiment of the invention, the packaged antenna 10 comprises: and a support unit 17. The supporting unit 17 is disposed on a surface of the second dielectric substrate 13 away from the first dielectric substrate 11, that is, the supporting unit and the first solder balls 16 are located on the same surface of the second dielectric substrate 13, and a bottom end of the supporting unit 17 is flush with a bottom end of at least one first solder ball 16. The supporting unit 17 can provide supporting and isolating functions for the packaged antenna 10 when the packaged antenna 10 is integrated with other chips, so that a stable connection structure can be ensured between the packaged antenna 10 and the chips, and the stability of the finally integrated antenna-on-chip system is further ensured.
In this embodiment, the supporting unit 17 is a plurality of bumps arranged at intervals. And optionally, the bump is a ball bump or a stud bump.
Further, when the number of the first solder balls 16 in the packaged antenna 10 is two or more, at least one bump is disposed between every two adjacent first solder balls 16.
Alternatively, since the supporting unit 17 does not need electrical properties, the forming material of the supporting unit 17 may be a metal material, or may be a non-metal material with certain hardness, which is not limited in the present invention.
The antenna module designed on the PCB in the on-chip antenna system is independently packaged by adopting a BGA packaging process, wherein the geometric dimensions of each antenna unit 14 and each feed through hole 15 in the packaged antenna 10 can be confirmed in advance through simulation, and then the packaged antenna is processed by a PCB manufacturer, and after the packaged antenna is processed by the PCB manufacturer, ball planting operation is carried out at one end of each feed through hole 15 close to the second dielectric substrate 13, namely each feed through hole 15 on the surface of the second dielectric substrate 13, so that the packaged antenna 10 has the capability of being packaged again or integrated with other chips. The processing flow of the packaged antenna 10 in a PCB factory is completely the same as that of the prior art, only the ball mounting process is added in the last link, and the packaging flow is simple.
Further, the present invention also provides a packaged chip, which is used together with the packaged antenna 10 described above, to implement independent packaging of chip modules in the antenna-on-chip system, thereby enhancing flexibility and compatibility of chip applications.
As shown in fig. 2, the packaged chip 20 includes: a package substrate 23, a chip die 25, a package mold 22, at least one metal via 21, and a plurality of second solder balls 24.
Wherein the chip die 25 is disposed on the first surface of the package substrate 23; the package mold 22 encapsulates the chip die 25; at least one metal via 21 penetrates through the package mold 22, and one end of the at least one metal via 21 near the package substrate 23 is connected with a lead of the chip die 25; a plurality of second solder balls 24 are disposed on a second surface of the package substrate 23 opposite to the first surface.
The package substrate 23 may be a commonly used chip package material such as polyimide.
The number and the positions of the metal vias 21 correspond to the first solder balls 16 on the package antenna 10, and when the package chip 20 is integrated with or electrically connected to the package antenna 10, at least one of the metal vias 21 of the package chip 20 is electrically connected to at least one of the first solder balls 16 of the package antenna 10 in a one-to-one correspondence manner.
In the embodiment of the invention, the diameter of one end of each metal through hole 21, which is far away from the package substrate 23, of at least one metal through hole 21 is larger than the diameter of one end of the metal through hole 21, which is close to the package substrate 23, that is, the cross-sectional shape of each metal through hole 21 is a tapered structure. Therefore, on one hand, when the package chip 20 is integrated with or electrically connected to the package antenna 10, the contact area between the metal via 21 and the first solder ball 16 can be ensured, thereby enhancing the reliability of the integration or electrical connection between the package chip 20 and the package antenna 10; on the other hand, the packaging cost of the packaged chip 20 can be reduced.
The invention can adopt the same process as the existing chip packaging process to manufacture the packaged chip 20, and only needs to etch (for example, laser etching) the corresponding through hole on the packaging molding 22 after the chip packaging is finished, and then gold immersion treatment is carried out on the through hole formed by etching so as to metalize the etched through hole, thus forming the metal through hole 21 as shown in fig. 2. Optionally, the material deposited in the via hole when the via hole is subjected to the gold immersion treatment is, for example, gold or silver or other alloy materials.
After the chip is packaged, the required antenna-on-chip system can be obtained by assembling the packaged antenna 10, so that the package of the antenna-on-chip system is not limited to a chip packaging factory, and the packaging cost is reduced.
Further, when the packaged antenna 10 having the structure of the supporting unit 17 is integrally assembled with the packaged chip 20 shown in fig. 2, the antenna-on-chip system shown in the first embodiment of the present invention can be obtained. As shown in fig. 3, in the antenna-on-chip system, at least one metal via 21 of the packaged chip 20 is electrically connected to at least one first solder ball 16 of the packaged antenna 10 to realize signal transmission between the packaged chip 20 and the packaged antenna 10. Alternatively, the package antenna 10 may be soldered on top of the package chip 20 by using a Surface Mount Technology (SMT) process, so as to achieve electrical connection between the package chip 20 and the package antenna 10.
Referring to fig. 3, in this embodiment, a diameter of an end of each of the at least one metal via 21 away from the package substrate 23 is smaller than a diameter of the corresponding electrically connected first solder ball 16, so that when the at least one metal via 21 is electrically connected to the at least one first solder ball 16, each first solder ball 16 is at least partially located outside the metal via 21, and the package antenna 10 and the package chip 20 are supported and isolated from each other by the supporting unit 17. It can be appreciated that the integration process of the antenna-on-chip system is simple, and is more convenient and faster when the replacement of the packaged antenna 10 or the packaged chip 20 is required.
Further, when the packaged antenna 10 having no structure of the supporting unit 17 is integrally assembled with the packaged chip 20 shown in fig. 2, the antenna-on-chip system shown in the second embodiment of the present invention can be obtained. As shown in fig. 4, in the antenna-on-chip system, at least one metal via 21 of the packaged chip 20 is electrically connected to at least one first solder ball 16 of the packaged antenna 10 to realize signal transmission between the packaged chip 20 and the packaged antenna 10.
Referring to fig. 4, in this embodiment, a diameter of an end of each of the at least one metal via 21 away from the package substrate 23 is larger than a diameter of the corresponding electrically connected first solder ball 16, so that each first solder ball 16 is located inside the metal via 21 when the at least one metal via 21 is electrically connected to the at least one first solder ball 16. It can be understood that the volume of the antenna-on-chip system is smaller, and the performance of the electrical connection between the packaged antenna 10 and the packaged chip 20 is more stable and reliable.
In a conventional antenna-on-chip system, an antenna and a chip are all completed by a packaging factory, and the antenna is designed on a specific substrate, wherein different packaging companies adopt different materials, and an antenna structure needs to be specially designed. The encapsulation must also be done by the specific encapsulation company. The invention adopts the on-chip antenna system with the modularized design, the antenna module, namely the packaged antenna 10, can be manufactured by a PCB factory, the cost is obviously reduced, and the packaged antenna 10 packaged by BGA has the capability of being packaged again; the chip module, i.e. the package of the packaged chip 20, can be completed by a chip packaging company, and then the packaged antenna 10 and the packaged chip 20 are assembled by a SMT process only by a chip packaging company or a client line, so that the on-chip antenna system with higher compatibility can be obtained, the packaging process is simplified, the packaging cost is reduced, the flexibility of the on-chip antenna application is enhanced, and the on-chip antenna system can be compatible with different application scenes.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (12)
1. A packaged antenna, comprising:
the first dielectric substrate and the second dielectric substrate are oppositely arranged;
the antenna units are arranged on the surface of the first dielectric substrate far away from the second dielectric substrate at intervals;
the grounding plate is arranged between the first dielectric substrate and the second dielectric substrate;
at least one feed via passing through the first dielectric substrate, the ground plate and the second dielectric substrate;
at least one first solder ball arranged on the surface of the second dielectric substrate far away from the first dielectric substrate,
each antenna unit in the at least one antenna unit is electrically connected with one first solder ball through one feed through hole.
2. The packaged antenna of claim 1, wherein the packaged antenna further comprises:
and the rewiring layer comprises at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer, and is arranged between the first dielectric substrate and the grounding plate or between the grounding plate and the second dielectric substrate.
3. The packaged antenna of claim 2, wherein the redistribution layer has vias formed therein connecting the metal routing layers.
4. A packaged chip, comprising:
a package substrate;
a chip die disposed on the first surface of the package substrate;
a package mold encapsulating the chip die;
at least one metal via molded through the package and connected to leads of the chip die proximate an end of the package substrate;
a plurality of second solder balls disposed on a second surface of the package substrate opposite the first surface,
wherein, when the packaged chip is electrically connected to the packaged antenna according to any one of claims 1 to 3, the at least one metal via of the packaged chip is electrically connected to the at least one first solder ball of the packaged antenna in a one-to-one correspondence manner.
5. The packaged chip of claim 4, wherein the diameter of each of the at least one metal via at an end thereof distal from the package substrate is greater than the diameter of the end thereof proximal to the package substrate.
6. An on-chip antenna system, comprising:
a packaged antenna according to any one of claims 1-3; and
the packaged chip of any one of claims 4-5,
the at least one metal through hole of the packaged chip is electrically connected with the at least one first solder ball of the packaged antenna so as to realize signal transmission between the packaged chip and the packaged antenna.
7. The antenna-on-chip system of claim 6, wherein a diameter of an end of each of the at least one metal via, which is away from the package substrate of the packaged chip, is smaller than a diameter of the corresponding electrically connected first solder ball, such that each first solder ball is at least partially outside the metal via when the at least one metal via is electrically connected to the at least one first solder ball.
8. The antenna-on-chip system of claim 7, wherein the packaged antenna further comprises:
and the supporting unit is arranged on the surface of the second medium substrate far away from the first medium substrate, and the bottom end of the supporting unit is flush with the bottom end of the at least one first solder ball.
9. The antenna-on-chip system of claim 8, wherein the support element is a plurality of spaced apart bumps.
10. The antenna-on-chip system according to claim 9, wherein when the number of the first solder balls is two or more, at least one bump is provided between every two adjacent first solder balls.
11. The antenna-on-chip system of claim 10, wherein the bumps are ball bumps or stud bumps.
12. The antenna-on-chip system of claim 6, wherein a diameter of an end of each of the at least one metal via, which is away from the package substrate of the packaged chip, is larger than a diameter of the corresponding electrically connected first solder ball, such that each first solder ball is located inside the metal via when the at least one metal via is electrically connected to the at least one first solder ball.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111305384.4A CN113991285A (en) | 2021-11-05 | 2021-11-05 | Packaged antenna, packaged chip and antenna-on-chip system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111305384.4A CN113991285A (en) | 2021-11-05 | 2021-11-05 | Packaged antenna, packaged chip and antenna-on-chip system |
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| Publication Number | Publication Date |
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| CN113991285A true CN113991285A (en) | 2022-01-28 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109687165A (en) * | 2018-12-29 | 2019-04-26 | 瑞声科技（南京）有限公司 | Millimeter wave array antenna mould group and mobile terminal |
| CN109888458A (en) * | 2019-04-02 | 2019-06-14 | 中芯长电半导体（江阴）有限公司 | Antenna packages structure, packaging method and external antenna connection method |
| CN109994462A (en) * | 2019-03-29 | 2019-07-09 | 上海天马微电子有限公司 | Chip packaging structure and packaging method thereof |
| CN111276788A (en) * | 2020-02-04 | 2020-06-12 | Oppo广东移动通信有限公司 | Dual-frequency millimeter wave antenna module and electronic equipment |
| CN112713096A (en) * | 2019-10-25 | 2021-04-27 | 中芯长电半导体（江阴）有限公司 | Antenna packaging structure and packaging method |
-
2021
- 2021-11-05 CN CN202111305384.4A patent/CN113991285A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109687165A (en) * | 2018-12-29 | 2019-04-26 | 瑞声科技（南京）有限公司 | Millimeter wave array antenna mould group and mobile terminal |
| CN109994462A (en) * | 2019-03-29 | 2019-07-09 | 上海天马微电子有限公司 | Chip packaging structure and packaging method thereof |
| CN109888458A (en) * | 2019-04-02 | 2019-06-14 | 中芯长电半导体（江阴）有限公司 | Antenna packages structure, packaging method and external antenna connection method |
| CN112713096A (en) * | 2019-10-25 | 2021-04-27 | 中芯长电半导体（江阴）有限公司 | Antenna packaging structure and packaging method |
| CN111276788A (en) * | 2020-02-04 | 2020-06-12 | Oppo广东移动通信有限公司 | Dual-frequency millimeter wave antenna module and electronic equipment |
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