CN113988278A - Long-short-time memory autonomous switching circuit based on memristor cross array - Google Patents

Long-short-time memory autonomous switching circuit based on memristor cross array Download PDF

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CN113988278A
CN113988278A CN202111213175.7A CN202111213175A CN113988278A CN 113988278 A CN113988278 A CN 113988278A CN 202111213175 A CN202111213175 A CN 202111213175A CN 113988278 A CN113988278 A CN 113988278A
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resistor
terminal
operational amplifier
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twenty
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王小平
潘朝勋
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods

Abstract

The invention discloses a long-time and short-time memory autonomous switching circuit based on a memristor cross array, and belongs to the field of circuit design. The long-term stimulation judging circuit comprises a short-term memory network, a long-term stimulation judging circuit and a memory conversion circuit; the short-term memory network comprises a first memristive crossbar array, and the long-term memory network comprises a second memristive crossbar array. The computing speed of the network is greatly improved by utilizing the parallel processing capacity of the memristor cross array, and the memristor with the memory function provides a good implementation scheme for long-time memory conversion and short-time memory conversion; the programmable resistance of the memristor cross array enriches the application scene of the network, enables long-time memory conversion to be possible, and can be expanded into different neural network structures by utilizing the programmable resistance, so that the singleness of the function of the traditional network is broken; meanwhile, whether the external stimulation belongs to the long-term stimulation or not is judged by means of the long-term stimulation judging circuit, and the problem of conversion from short-term memory to long-term memory is solved through the memory conversion circuit.

Description

Long-short-time memory autonomous switching circuit based on memristor cross array
Technical Field
The invention belongs to the field of circuit design, and particularly relates to a long-time and short-time memory autonomous switching circuit based on a memristor cross array.
Background
In 1966, Milner concluded a conclusion from a study of amnesia after temporal lobe surgery on the brain: long-term memory and short-term memory are stored separately in the biological brain. In 1968, Atkinson and Shiffrin proposed a three-stage cognitive model of memory, and it was thought that only short-term memories processed by manipulation could be consolidated into long-term memories. The purpose of the long-time and short-time memory conversion is to encode the short-time memory into the long-time memory for storage under the action of long-time stimulation from the outside and to protect the original memory from being damaged. The difficulty of long-time memory conversion is the reading and writing of memory information. The memristor cross array is a good method for solving the problem of reading and writing memory information. The memristor is a nonlinear double-end nanometer device with a memory function, the resistance value of the memristor is changed by controlling the current and the voltage applied to the two ends of the device, the resistance value can be kept unchanged after the power is off, and the read-write problem of memory information is converted into the control of read-write voltage. When the voltage at two ends of the memristor exceeds the threshold value of the memristor, the resistance value of the memristor starts to change from the initial state until the stable state is reached, and the stable state is the memory information. Neural networks typically use resistors as weights, and once the weights are determined, the function of the network cannot be changed. Since a novel memristor with a plurality of nanoscale devices with excellent performance is predicted to exist in 1971 and a physical object is successfully prepared for the first time in 2008, the memristor is widely concerned by researchers, and the resistance change performance and the switch-like characteristic of the memristor enable the memristor to replace the traditional transistor device and is expected to solve the technical bottleneck problem.
In the development process of the neural network technology, the research of the hardware implementation technology is far lagged behind the application research, so that most of the current applications have to adopt a serial computer to carry out software simulation, and people applying the artificial neural network have not had an opportunity to really realize various advantages based on the parallel structure of the neural network for decades. The study on how to realize long-time and short-time memory conversion by using the memristors enables the weight of the neural network to be changed like biological synapses along with external stimulation, and has important significance.
Disclosure of Invention
Aiming at the defects of the related art, the invention provides a long-short time memory autonomous switching circuit based on a memristor cross array based on the parallel computing characteristic of the memristor cross array and the fact that the long-short time memory is stored in a biological long-short time memory partition, and aims to solve the problems that the long-short time memory switching cannot be realized by hardware and the parallel processing capability of a neural network cannot be fully exerted in the prior art.
In order to achieve the purpose, the invention provides a long-time memory autonomous switching circuit based on a memristor cross array, which comprises a short-time memory network, a long-time stimulation judging circuit and a memory switching circuit, wherein the short-time memory network is connected with the long-time memory network; the short-time memory network comprises a first memristive crossbar array, and the long-time memory network comprises a second memristive crossbar array;
the long-term stimulation judging circuit comprises n differential operation modules, n absolute value modules, a summation comparison module and a control module, wherein n is an integer greater than or equal to 3; the output ends of the n differential operation modules are correspondingly connected with the input ends of the n absolute value modules, the output ends of the n absolute value modules are connected to the input end of the summation comparison module, and the output end of the summation comparison module is connected with the input end of the control module; the output voltage of the control module determines whether the rows and columns of the first memristive crossbar array and the second memristive crossbar array are gated;
the memory conversion circuit comprises a reading circuit module, a long-time and short-time memory module and a writing circuit module which are sequentially connected; the reading circuit module reads short-time memory from the first memristor cross array and converts the short-time memory into short-time memory voltage, the long-time memory module converts the short-time memory voltage into long-time memory voltage, and the writing circuit module writes the long-time memory voltage into the second memristor cross array.
Furthermore, a first input end of each differential operation module is connected with an excitation function, a second input end of each differential operation module is connected with a comparison input voltage, an output value of the excitation function corresponds to an association result of the short-time memory network, and the comparison input voltage corresponds to external stimulation;
the n difference operation modules calculate n excitation function output values and n error values of each point of comparison input voltage;
the n absolute value modules calculate the absolute value of the error value of each point;
the summation comparison module sums the absolute values of the errors obtained by the points and compares the summation result with a first reference voltagePressure VrefComparing to obtain a judgment voltage;
the judgment voltage is input to the control module, and the output voltage of the control module changes.
Further, n is 3.
Further, the first differential operation module comprises a first operational amplifier A1A first resistor R1A second resistor R2A third resistor R3And a fourth resistor R4；
The first resistor R1Is connected to a first excitation function g1The first resistor R1The second terminal of (1), the second resistor R2And the first operational amplifier A1Is connected to the reverse input terminal of the first resistor, the third resistor R is connected to the reverse input terminal of the second resistor3Is connected to a first comparison input voltage VIN1Said third resistance R3And said fourth resistor R4Are all connected with the first operational amplifier A1Is connected to the positive input terminal of the fourth resistor R4Is grounded, and the second resistor R2And the first operational amplifier A1The output ends of the two are connected;
the second differential operation module comprises a fourth operational amplifier A4And a twelfth resistor R12A thirteenth resistor R13A fourteenth resistor R14And a fifteenth resistor R15；
The twelfth resistor R12Is connected to a second excitation function g2The twelfth resistor R12The second terminal of (1), the thirteen resistors R13And the fourth operational amplifier A4Is connected to the reverse input terminal of the fourth resistor R14Is connected to a second comparison input voltage VIN2The fourteenth resistance R14And the fifteenth resistor R15And the first ends of the first and second operational amplifiers A4Is connected to the positive input terminal of the first resistor, and the fifteenth resistor R15Is grounded, and the thirteenth resistor R13Second end and postThe fourth operational amplifier A4The output ends of the two are connected;
the third differential operation module comprises a seventh operational amplifier A7Twenty third resistor R23Twenty-fourth resistor R24Twenty-fifth resistor R25And a twenty-sixth resistor R26；
The twenty-third resistor R23Is connected to a third excitation function g3The twenty-three resistance R23Second terminal, twenty-fourth resistor R24And the seventh operational amplifier A7Is connected to the reverse input terminal of the first resistor, the twenty-fifth resistor R25Is connected to a third comparison input voltage VIN3The twenty-fifth resistor R25And said twenty-sixth resistor R26Are all connected with the seventh operational amplifier A7Is connected to the positive input terminal of the first resistor, and the twenty-sixth resistor R26Is grounded, the twenty-fourth resistor R24And the seventh operational amplifier a7Are connected with each other.
Further, the first absolute value module comprises a fifth resistor R5A sixth resistor R6A seventh resistor R7An eighth resistor R8A ninth resistor R9A tenth resistor R10An eleventh resistor R11A first diode D1A second diode D2A second operational amplifier A2And a third operational amplifier A3；
Ninth resistor R9First terminal and fifth resistor R5First terminal of (1) and first operational amplifier A1Is connected to the output terminal of the fifth resistor R5Second terminal, sixth resistor R6First terminal, first diode D1First terminal and second operational amplifier A2Is connected to the reverse input terminal of the seventh resistor R7First terminal and second operational amplifier A2Is connected to the positive input terminal of a first diode D1Second terminal, second diode D2First terminal and second operational amplifier A2Output of (2)End connection;
eighth resistor R8Second terminal, ninth resistor R9Second terminal, tenth resistor R10First terminal of and third operational amplifier A3Is connected to the reverse input terminal of the first resistor R11First terminal of and third operational amplifier A3Is connected to the positive input terminal of the tenth resistor R10Second terminal, thirty-fourth resistor R 34 and a third operational amplifier A3The output ends of the two are connected;
the second absolute value module comprises a sixteenth resistor R16Seventeenth resistor R17Eighteenth resistor R18Nineteenth resistor R19Twentieth resistor R20Twenty-first resistor R21A twenty-second resistor R22A third diode D3A fourth diode D4A fifth operational amplifier A5And a sixth operational amplifier A6；
Twentieth resistor R20First terminal and sixteenth resistor R16First terminal of and fourth operational amplifier A4Is connected to the sixteenth resistor R16A second terminal, a seventeenth resistor R17First terminal of, third diode D3First terminal of and fifth operational amplifier A5Is connected to the inverting input terminal of the eighth resistor R18, and a first terminal of the eighteenth resistor R18 is connected to the fifth operational amplifier a5Is connected to the positive input terminal of a third diode D3Second terminal, fourth diode D4First terminal of and fifth operational amplifier A5The output ends of the two are connected;
nineteenth resistor R19Second terminal, twentieth resistor R20Second terminal, twenty-first resistor R21First terminal of and sixth operational amplifier A6Is connected to the second twenty-second resistor R22First terminal of and sixth operational amplifier A6Is connected to the positive input terminal of the first resistor R21Second terminal, thirty-fifth resistor R35First terminal of and sixth operational amplifier A6The output ends of the two are connected;
the above-mentionedThe third absolute value module comprises a twenty-seventh resistor R27Twenty eighth resistor R28Twenty ninth resistor R29Thirty-th resistor R30And a thirty-first resistor R31Thirty-second resistor R32And a thirty-third resistor R33A fifth diode D5A sixth diode D6An eighth operational amplifier A8And a ninth operational amplifier A9；
A thirty-first resistor R31First terminal and twenty-seventh resistor R27Are all connected with a seventh operational amplifier A7Is connected to a twenty-seventh resistor R27Second terminal, twenty-eighth resistor R28First terminal of, fifth diode D5First terminal and eighth operational amplifier A8Is connected to the reverse input terminal of the first resistor R29First terminal and eighth operational amplifier A8Is connected to the positive input terminal of a fifth diode D5Second terminal, sixth diode D6First terminal and eighth operational amplifier A8The output ends of the two are connected;
thirtieth resistor R30Second terminal, thirty-first resistor R31Second terminal, thirty-second resistor R32First terminal and ninth operational amplifier A9Is connected to the reverse input terminal of the third resistor R33First terminal and ninth operational amplifier A9Is connected to the positive input terminal of the first resistor, a thirty-second resistor R32Second terminal, thirty-sixth resistor R36Is connected to the output of the ninth operational amplifier a 9;
a seventh resistor R7Second terminal, eleventh resistor R11Second terminal, eighteenth resistor R18Second terminal, twenty-second resistor R22Second terminal, twenty-ninth resistor R29Second terminal, thirty-third resistor R33Are all grounded.
Further, the summation comparison module comprises a thirty-fourth resistor R34Thirty-fifth resistor R35Thirty-sixth resistor R36Thirty-seventh resistor R37Thirty-eighth resistor R38Thirty-ninth resistor R39A tenth operational amplifier and an eleventh operational amplifier;
thirty-fourth resistor R34First terminal of and third operational amplifier A3Is connected to the thirty-fifth resistor R35First terminal of and sixth operational amplifier A6Is connected to the thirty-sixth resistor R36First terminal and ninth operational amplifier A9Is connected to the output terminal of the third resistor R34Second terminal, thirty-fifth resistor R35Second terminal, thirty-sixth resistor R36Second terminal, thirty-seventh resistor R37First terminal and tenth operational amplifier A10Is connected to the inverting input terminal of a tenth operational amplifier A10Is grounded, and a thirty-seventh resistor R37Second terminal, thirty-eighth resistor R38First terminal and tenth operational amplifier A10The output ends of the two are connected;
thirty-eighth resistor R38Second terminal of and eleventh operational amplifier A11Is connected to the reverse input terminal of the switch, a thirty-ninth resistor R39First terminal of (1) is connected to a first reference voltage VrefThirty-ninth resistor R39Second terminal of and eleventh operational amplifier A11Is connected to the positive input terminal.
Further, the control module comprises a fortieth resistor R40A forty-first resistor R41A forty-second resistor R42A forty-third resistor R43A forty-fourth resistor R44A forty-fifth resistor R45The twelfth operational amplifier A12Thirteenth operational amplifier A13And twentieth memristor MS2；
Fortieth resistor R40First terminal of and eleventh operational amplifier A11The output ends of the two are connected; fortieth resistor R40Second terminal, forty-first resistor R41Second terminal, forty-second resistor R42First terminal of and twelfth operational amplifier A12Is connected to the reverse input terminal of the first resistor R41First end of (2) is connected to a first enable voltage VENThe twelfth operational amplifier A12Is grounded, and a forty-second resistor R42Second terminal and a forty-third resistor R43First terminal of and twelfth operational amplifier A12The output ends of the two are connected;
a forty-third resistor R43Second terminal, forty-fourth resistor R44First terminal of and thirteenth operational amplifier A13Is connected to the inverting input terminal of a thirteenth operational amplifier A13Is grounded, and a forty-fourth resistor R44Second terminal, twentieth memristor MS2First terminal of and thirteenth operational amplifier A13The output ends of the two are connected;
twentieth memristor MS2Second terminal and a forty-fifth resistor R45Is connected as an output of the control module.
The invention provides a long-time and short-time memory autonomous conversion circuit based on a memristor cross array based on the parallel computing characteristic of the memristor cross array and the fact that long-time and short-time memory partitions are stored according to living beings. The computing speed of the network is greatly improved by utilizing the parallel processing capacity of the memristor cross array, and the memristor with the memory function provides a good implementation scheme for long-time memory conversion and short-time memory conversion; the programmable resistance of the memristor cross array enriches the application scene of the network, enables long-time memory conversion to be possible, and can be expanded into different neural network structures by utilizing the programmable resistance, so that the singleness of the function of the traditional network is broken; meanwhile, whether the external stimulation belongs to the long-term stimulation or not is judged by means of the long-term stimulation judging circuit, and the problem of conversion from short-term memory to long-term memory is solved through the memory conversion circuit. Through the technical scheme, compared with the prior art, the invention has the following beneficial effects:
(1) compared with the traditional Von Neumann serial computer, the cross array does not need to use an MOS (metal oxide semiconductor) tube any more, and the cross array uses memristors instead of resistors, so that the whole circuit structure is simpler, the power consumption is lower, and the volume is smaller.
(2) The invention can fully exert the parallel processing capability of the neural network and can realize the autonomous judgment on whether the external stimulation belongs to the long-term stimulation. Meanwhile, the flexibility of the whole circuit is improved by using the variability of the resistance values of the memristors, and the conversion from short-term memory to long-term memory can be realized by reading and writing the resistance values of the memristor cross array after the external stimulus is judged to belong to the long-term stimulus.
The invention can be applied to an ultra-large scale integrated circuit, and can be combined with the existing artificial intelligence chip to realize the function of the neuromorphic calculating chip.
Drawings
Fig. 1 is a schematic diagram of a long-term memory autonomous switching circuit based on a memristive crossbar array according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating three basic modes used in the long-term and short-term memory autonomous transformation experiment.
Fig. 3 is an experimental result of the long-term stimulus determination circuit, in which (a) is an associative memory result of the short-term memory network; (b) the error voltage sum obtained in the summation comparison module is obtained; (c) the decision voltage output by the comparison module is summed.
FIG. 4 is a diagram illustrating experimental results of long-term and short-term memory transformation.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The invention discloses a long-time and short-time memory autonomous switching circuit based on a memristor cross array by utilizing the characteristic that the memristor has a memory function, combining the network weight programmable capability of the memristor cross array and adopting a scheme of realizing long-time and short-time memory autonomous switching by a hardware circuit. The contents of the above embodiments will be described with reference to a preferred embodiment.
As shown in fig. 1, the present invention provides a long-time and short-time memory autonomous switching circuit based on a memristor crossbar array, including: first memristor M1The second memristor M2The third memristor M3The fourth memristor M4The fifth memristor M5The sixth memristor M6The seventh memristor M7The eighth memristor M8The ninth memristor M9The tenth memristor N1The eleventh memristor N2Twelfth memristor N3Thirteenth memristor N4Fourteenth memristor N5Fifteenth memristor N6Sixteenth memristor N7Seventeenth memristor N8Eighteenth memristor N9Nineteenth memristor MS1Twentieth memristor MS2A first operational amplifier A1A second operational amplifier A2A third operational amplifier A3A fourth operational amplifier A4A fifth operational amplifier A5A sixth operational amplifier A6A seventh operational amplifier A7An eighth operational amplifier A8The ninth operational amplifier A9The tenth operational amplifier A10Eleventh operational amplifier A11The twelfth operational amplifier A12Thirteenth operational amplifier A13And a fourteenth operational amplifier A14Fifteenth operational amplifier A15Sixteenth operational amplifier A16A first diode D1A second diode D2A third diode D3A fourth diode D4A fifth diode D5A sixth diode D6A first resistor R1A second resistor R2A third resistor R3A fourth resistor R4A fifth resistor R5A sixth resistor R6A seventh resistor R7An eighth resistor R8A ninth resistor R9A tenth resistor R10An eleventh resistor R11And a twelfth resistor R12A thirteenth resistor R13A fourteenth resistor R14A fifteenth resistor R15Sixteenth resistor R16Seventeenth resistor R17Eighteenth resistor R18Nineteenth resistor R19Twentieth resistor R20Twenty-first resistor R21A twenty-second resistor R22Twenty third resistor R23Twenty-fourth resistor R24Twenty-fifth resistor R25Twenty-sixth resistor R26Twenty-seventh resistor R27Twenty eighth resistor R28Twenty ninth resistor R29Thirty-th resistor R30And a thirty-first resistor R31Thirty-second resistor R32And a thirty-third resistor R33And a thirty-fourth resistor R34Thirty-fifth resistor R35Thirty-sixth resistor R36Thirty-seventh resistor R37Thirty-eighth resistor R38Thirty-ninth resistor R39A fortieth resistor R40A forty-first resistor R41A forty-second resistor R42A forty-third resistor R43A forty-fourth resistor R44A forty-fifth resistor R45A forty-sixth resistor R46And a forty-seventh resistor R47A forty-eighth resistor R48And a forty-ninth resistor R49A first activation function g1, a second activation function g2, a third activation function g3, a first comparison input voltage VIN1A second comparison input voltage VIN2Third comparison input voltage VIN3A first reference voltage VrefA first enable voltage VEN；
Preferably, the first activation function g1, the second activation function g2, and the third activation function g3 are sigmoid activation functions.
First memristor M1First end, fourth memristor M4First end and seventh memristor M7The first end of the first memristor M is connected with the first column gating unit and the second column gating unit2First end, fifth memristor M5First end and eighth memristor M8The first end of the first memristor M is connected with the first column gating unit, the second column gating unit and the third memristor M3First end, sixth memristor M6First terminal and ninth memristorMachine M9The first end of the first memory resistor is connected with the first column gating unit, the second column gating unit and the tenth memory resistor N1First end, thirteenth memristor N4First end and sixteenth memristor N7The first end of the first memristor is connected with the gating unit of the third column and the gating unit of the fourth column, and the eleventh memristor N2The first end and the fourteenth memristor N5First terminal and seventeenth memristor N8The first end of the first memory resistor is connected with the gating units of the third column and the fourth column, and the twelfth memory resistor N3First end, fifteenth memristor N6First end and eighteenth memristor N9The first end of the first gate is connected with the gating unit of the third column and the gating unit of the fourth column;
first memristor M1Second terminal, fourth memristor M4Second terminal and seventh memristor M7The second end of the first memristor M is connected with the first row strobe unit, the second row strobe unit and the second memristor M2Second terminal, fifth memristor M5Second terminal and eighth memristor M8The second end of the first memristor M is connected with the first row strobe unit, the second row strobe unit and the third memristor M3Second end, sixth memristor M6Second terminal and ninth memristor M9The second end of the first memristor N is connected with the first row strobe unit, the second row strobe unit and the tenth memristor N1Second terminal, thirteenth memristor N4Second terminal and sixteenth memristor N7The second end of the first memristor is connected with the third row gating unit and the fourth row gating unit, and the eleventh memristor N2Second terminal, fourteenth memristor N5Second terminal and seventeenth memristor N8The second end of the first memory resistor is connected with the third row gating unit and the fourth row gating unit, and the twelfth memory resistor N3Second end, fifteenth memristor N6Second terminal and eighteenth memristor N9The second end of the first gate is connected with the third row gating unit and the fourth row gating unit;
a first resistor R1Is connected to the output of the first activation function g1, a twelfth resistor R12Is connected to the output of the second activation function g2, a twenty-third resistor R23To (1) aOne end of the first activation function is connected with the output end of the third activation function g 3;
a first resistor R1Second terminal, second resistor R2First terminal of (1) and first operational amplifier A1Is connected to the reverse input terminal of the third resistor R3Second terminal, fourth resistor R4First terminal of (1) and first operational amplifier A1Is connected to the positive input terminal of the first resistor R, and a second resistor R2Second terminal, fifth resistor R5First terminal, ninth resistor R9First terminal of (1) and first operational amplifier A1The output ends of the two are connected;
twelfth resistor R12Second terminal, thirteenth resistor R13First terminal of and fourth operational amplifier A4Is connected to the fourteenth resistor R14Second terminal, fifteenth resistor R15First terminal of and fourth operational amplifier A4Is connected to the positive input terminal of the thirteenth resistor R13Second terminal, sixteenth resistor R16First terminal, twentieth resistor R20First terminal of and fourth operational amplifier A4The output ends of the two are connected;
a twenty-third resistor R23Second terminal, twenty-fourth resistor R24First terminal and seventh operational amplifier A7Is connected to the reverse input terminal of the resistor R, a twenty-fifth resistor R25Second terminal, twenty-sixth resistor R26First terminal and seventh operational amplifier A7Is connected to the positive input terminal of the switch, a twenty-fourth resistor R24Second terminal, twenty-seventh resistor R27First terminal, thirty-first resistor R31First terminal and seventh operational amplifier A7The output ends of the two are connected;
third resistor R3Is connected to a first comparison input voltage VIN1Fourteenth resistor R14First end of (d) is connected to a second comparison input voltage VIN2Twenty-fifth resistor R25Is connected to a third comparison input voltage VIN3；
Fifth resistor R5Second terminal, sixth resistor R6First terminal, first diode D1First ofTerminal and second operational amplifier A2Is connected to the reverse input terminal of the seventh resistor R7First terminal and second operational amplifier A2Is connected to the positive input terminal of a first diode D1Second terminal, second diode D2First terminal and second operational amplifier A2The output ends of the two are connected;
sixteenth resistor R16A second terminal, a seventeenth resistor R17First terminal of, third diode D3First terminal of and fifth operational amplifier A5Is connected to the eighteenth resistor R18First terminal of and fifth operational amplifier A5Is connected to the positive input terminal of a third diode D3Second terminal, fourth diode D4First terminal of and fifth operational amplifier A5The output ends of the two are connected;
twenty-seventh resistor R27Second terminal, twenty-eighth resistor R28First terminal of, fifth diode D5First terminal and eighth operational amplifier A8Is connected to the reverse input terminal of the first resistor R29First terminal and eighth operational amplifier A8Is connected to the positive input terminal of a fifth diode D5Second terminal, sixth diode D6First terminal and eighth operational amplifier A8The output ends of the two are connected;
a sixth resistor R6Second terminal, second diode D2Second terminal and eighth resistor R8Is connected to a seventeenth resistor R17Second terminal, fourth diode D4Second terminal and nineteenth resistor R19Is connected to the first terminal of the resistor R, a twenty-eighth resistor R28Second terminal, sixth diode D6Second terminal and thirtieth resistor R30Are connected with each other;
eighth resistor R8Second terminal, ninth resistor R9Second terminal, tenth resistor R10First terminal of and third operational amplifier A3Is connected to the reverse input terminal of the first resistor R11First terminal of and third operational amplifier A3Is connected to the positive input terminal of the tenth resistor R10Second terminal, thirty-fourth resistor R34First terminal of and third operational amplifier A3The output ends of the two are connected;
nineteenth resistor R19Second terminal, twentieth resistor R20Second terminal, twenty-first resistor R21First terminal of and sixth operational amplifier A6Is connected to the second twenty-second resistor R22First terminal of and sixth operational amplifier A6Is connected to the positive input terminal of the first resistor R21Second terminal, thirty-fifth resistor R35First terminal of and sixth operational amplifier A6The output ends of the two are connected;
thirtieth resistor R30Second terminal, thirty-first resistor R31Second terminal, thirty-second resistor R32First terminal and ninth operational amplifier A9Is connected to the reverse input terminal of the third resistor R33First terminal and ninth operational amplifier A9Is connected to the positive input terminal of the first resistor, a thirty-second resistor R32Second terminal, thirty-sixth resistor R36First terminal and ninth operational amplifier A9The output ends of the two are connected;
a fourth resistor R4Second terminal, seventh resistor R7Second terminal, eleventh resistor R11Second terminal, fifteenth resistor R15Second terminal, eighteenth resistor R18Second terminal, twenty-second resistor R22Second terminal, twenty-sixth resistor R26Second terminal, twenty-ninth resistor R29Second terminal, thirty-third resistor R33The second ends of the first and second terminals are grounded;
thirty-fourth resistor R34Second terminal, thirty-fifth resistor R35Second terminal, thirty-sixth resistor R36Second terminal, thirty-seventh resistor R37First terminal and tenth operational amplifier A10Is connected to the inverting input terminal of a tenth operational amplifier A10The positive input end of the resistor is grounded, and the resistor R is thirty-seven37Second terminal, thirty-eighth resistor R38First terminal and tenth operational amplifier A10The output ends of the two are connected;
thirty-eighth resistor R38Second terminal of and eleventh operational amplifier A11Is connected to the reverse input terminal of the switch, a thirty-ninth resistor R39First terminal of (1) is connected to a first reference voltage VrefThirty-ninth resistor R39Second terminal of and eleventh operational amplifier A11Is connected to the positive input terminal of the fourth resistor R40First terminal of and eleventh operational amplifier A11The output ends of the two are connected;
fortieth resistor R40Second terminal, forty-first resistor R41Second terminal, forty-second resistor R42First terminal of and twelfth operational amplifier A12Is connected to the reverse input terminal of the first resistor R41First end of (2) is connected to a first enable voltage VENThe twelfth operational amplifier A12Is grounded, and a forty-second resistor R42Second terminal and a forty-third resistor R43First terminal of and twelfth operational amplifier A12The output ends of the two are connected;
a forty-third resistor R43Second terminal, forty-fourth resistor R44First terminal of and thirteenth operational amplifier A13Is connected to the inverting input terminal of a thirteenth operational amplifier A13Is grounded, and a forty-fourth resistor R44Second terminal, twentieth memristor MS2First terminal of and thirteenth operational amplifier A13The output ends of the two are connected;
twentieth memristor MS2Second terminal, forty-fifth resistor R45Is connected with the first voltage control unit and the second voltage control unit, and a forty-fifth resistor R45The second terminal of (1) is grounded;
forty-sixth resistor R46First terminal of and fourteenth operational amplifier A14Is connected to the first row strobe unit, a fourteenth operational amplifier A14Is grounded, and a forty-sixth resistor R46The second end and the nineteenth memristor MS1The second terminal of (1) and the fourteenth operational amplifier A14The output ends of the two are connected; nineteenth memristorMachine MS1First terminal, forty-seventh resistor R47First terminal and fifteenth operational amplifier A15Is connected to the inverting input terminal of a fifteenth operational amplifier A15Is grounded, and a forty-seventh resistor R47Second terminal, fifteenth operational amplifier A15And the sixteenth operational amplifier A16Is connected to the positive input terminal of the switch, a forty-eighth resistor R48Second terminal, forty-ninth resistor R49First terminal and sixteenth operational amplifier A16Is connected to the reverse input terminal of the resistor R, a forty-eighth resistor R48Is grounded, and a forty-ninth resistor R49Is connected to the gate unit of the third column, and a sixteenth operational amplifier A16The output end of the first row gating unit is connected with the second row gating unit;
the input terminal of the first activation function g1 is connected to the second row strobe unit, and the output terminal of the first activation function g1 is connected to the first resistor R1Is connected to the first terminal of the first row strobe unit, the input terminal of the second activation function g2 is connected to the second row strobe unit, the output terminal of the second activation function g2 is connected to the twelfth resistor R12Is connected to the first terminal of the first row strobe unit, the input terminal of the third activation function g3 is connected to the second row strobe unit, the output terminal of the third activation function g3 is connected to the twenty-third resistor R23Are connected to each other.
The basic principle of the present invention is described below. The invention provides a long-term stimulation judging circuit, which is characterized in that according to a biological long-term memory and short-term memory conversion mechanism, when the same stimulation time is long enough, namely the repetition times are many enough, the neural network can generate autonomous conversion of long-term memory and short-term memory, and the long-term stimulation judging circuit comprises: the device comprises n difference operation modules, n absolute value modules, 1 summation comparison module and 1 control module; wherein n is an integer of 3 or more; the size of n can be selected according to the actual task requirement. Calculating error values of each point of n excitation function output values corresponding to a short-time memory network association result and n comparison input voltages corresponding to external stimulation through n difference operation modules, calculating absolute values of the error values of each point through n absolute value modules, summing the absolute values of the errors obtained by each point through a summation comparison module, and summing a summation result and a first reference voltageVoltage VrefComparing to obtain a determination voltage, and finally, the control module compares the obtained determination voltage with a first enabling voltage VENDetermines the twentieth memristor MS2Whether the resistance value is changed or not is judged, so that the change of the output voltage of the control module is judged, and whether the row and the column of the memristor cross array are gated or not is judged. Whether the external stimulus belongs to the long-term stimulus or not can be judged according to the judgment voltage, the initial value of the judgment voltage is negative, and as long as the value of the initial voltage is positive, the error of the result of the association between the external stimulus and the short-term memory network is very small, the input of the external stimulus is stored in the short-term memory network, and if the external stimulus is continuously input into the network, the external stimulus can be determined to be the long-term stimulus.
The invention is based on the programmable characteristic of memory resistance, has also provided a kind of memory switching circuit, including: the memory circuit comprises 1 reading circuit module, 1 long-time memory module and 1 writing circuit module, wherein the reading circuit module is responsible for reading short-time memory from a first memristor cross array and converting the short-time memory into voltage information, the long-time memory module is responsible for converting short-time memory voltage into long-time memory voltage, and when the short-time memory voltage is input into the long-time memory module, a nineteenth memristor MS is used for memorizing a resistor1The high resistance state is changed into the low resistance state, the output voltage of the long-time memory module and the short-time memory module gradually changes from small to large until stable, and the stable voltage is the long-time memory voltage. And then the writing circuit module is responsible for writing the long-term memory voltage information into the corresponding memristors of the second memristor cross array. Therefore, the whole process completes the writing of the resistance information corresponding to the short-time memory in the first memristor cross array into the memristor corresponding to the long-time memory in the second memristor cross array, and the function of long-time and short-time memory conversion is achieved.
The invention also provides a cross array circuit design based on the long-term stimulation judging circuit and the memory conversion circuit, in a large-scale cross array, any memristor unit needing to participate in operation can be selected through the externally connected row strobe unit and column strobe unit, and then corresponding read operation and write operation are completed through control of external voltage of the units.
The whole operation process of the long-time and short-time memory autonomous switching circuit based on the memristor cross array is divided into two steps:
the first step is a long-term stimulation determination process: by applying a voltage across the first resistor R1By applying the output voltage of the first activation function g1 across the twelfth resistor R12By applying the output voltage of the second activation function g2 across the twenty-third resistor R23By applying the output voltage of the third activation function g3 across the third resistor R3Is applied with a first comparison input voltage VIN1Through the fourteenth resistor R14Is applied with a second comparison input voltage VIN2By applying a voltage across said twenty-fifth resistor R25Is applied with a third comparison input voltage VIN3By applying a resistance R at said thirty ninth resistor39Is applied with a first reference voltage VrefThrough the forty-first resistor R41Is applied with a first enabling voltage VENThe nineteenth memristor MS1And the twentieth memristor MS2The initial states of the sensors are all high-impedance states, so that the judgment of whether the external stimulation belongs to long-term stimulation is completed.
The second step is a long-time memory conversion process: the twentieth memristor MS2The voltage of the second end is applied to the first voltage control unit and the second voltage control unit, the reading voltage is applied to the first column gating unit, the output voltage of the first row gating unit is applied to the fourteenth operational amplifier A14Said sixteenth operational amplifier a16The voltage of the output end is applied to the gating unit of the third row, and the output voltage of the gating unit of the third column is applied to the forty-ninth resistor R49The second end of (a).
Fig. 2 shows 3 basic patterns used in the long-term and short-term memory autonomous transformation experiment, namely, the letters "Z", "V" and "N", and the positions of neurons corresponding to pixel values of each point of an image of the letters are given, and the experiment adopts a9 × 9 cross array in the invention.
Fig. 3 is an experimental result of the long-term stimulation determination circuit, where (a) is an associative memory result of the short-term memory network, that is, the output of each activation function, and a letter corresponding to the voltage value finally output by the short-term memory network is "N"; (b) the value of the sum of the error voltages obtained by the summation and comparison module is decreased from large to small, which indicates that the similarity between the input image corresponding to the external stimulus and the associative memory result of the short-time memory network is higher and higher, and when the sum of the error voltages is smaller than a first reference voltage Vref (at the moment corresponding to a dotted line), the input image corresponding to the external stimulus is stored in the short-time memory network; (c) the judgment voltage output by the summation comparison module changes from negative to positive, namely, the external stimulation is judged to be long-term stimulation.
Fig. 4 shows the experimental result of the long-term memory conversion, when the resistance value of a certain memristor of a given short-term memory network is 0.375 kq, the resistance value of the memristor corresponding to the long-term memory network changes from large to small under the long-term stimulus input from the outside, and finally stabilizes near 0.375 kq, which indicates that the circuit realizes the long-term memory conversion.
In this experiment, the short-term memory network has 4 weighted values, 4 memristive resistance values correspond to the short-term memory network, the long-term memory conversion is realized through the designed circuit to obtain 4 memristive resistance values of the long-term memory network, and corresponding errors of the two are given.
Short-time memory network memristor resistance value (target value)/omega Long-term memory network memristor resistance value (write-in value)/omega Error/%)
375 375.033 0.00880
525 525.022 0.00419
675 674.911 0.01319
825 824.965 0.00424
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (7)

1. A long-time and short-time memory autonomous conversion circuit based on a memristor cross array is characterized by comprising a short-time memory network, a long-time stimulation judgment circuit and a memory conversion circuit; the short-time memory network comprises a first memristive crossbar array, and the long-time memory network comprises a second memristive crossbar array;
the long-term stimulation judging circuit comprises n differential operation modules, n absolute value modules, a summation comparison module and a control module, wherein n is an integer greater than or equal to 3; the output ends of the n differential operation modules are correspondingly connected with the input ends of the n absolute value modules, the output ends of the n absolute value modules are connected to the input end of the summation comparison module, and the output end of the summation comparison module is connected with the input end of the control module; the output voltage of the control module determines whether the rows and columns of the first memristive crossbar array and the second memristive crossbar array are gated;
the memory conversion circuit comprises a reading circuit module, a long-time and short-time memory module and a writing circuit module which are sequentially connected; the reading circuit module reads short-time memory from the first memristor cross array and converts the short-time memory into short-time memory voltage, the long-time memory module converts the short-time memory voltage into long-time memory voltage, and the writing circuit module writes the long-time memory voltage into the second memristor cross array.
2. The long-short term memory autonomous switching circuit according to claim 1, wherein a first input terminal of each differential operation module is connected to an excitation function, a second input terminal thereof is connected to a comparison input voltage, an output value of the excitation function corresponds to an association result of the short-term memory network, and the comparison input voltage corresponds to an external stimulus;
the n difference operation modules calculate n excitation function output values and n error values of each point of comparison input voltage;
the n absolute value modules calculate the absolute value of the error value of each point;
the summation comparison module sums the absolute values of the errors obtained by the points and compares the summation result with a first reference voltage VrefComparing to obtain a judgment voltage;
the judgment voltage is input to the control module, and the output voltage of the control module changes.
3. The long-short duration memory autonomous switching circuit of claim 1 wherein n-3.
4. The long-short term memory autonomous switching circuit of claim 3, wherein the first differential operation module comprises a first operational amplifier A1A first resistor R1A second resistor R2A third resistor R3And a fourth resistor R4；
The first resistor R1Is connected to a first excitation function g1The first resistor R1The second terminal of (1), the second resistor R2And the first operational amplifier A1Is connected to the reverse input terminal of the first resistor, the third resistor R is connected to the reverse input terminal of the second resistor3Is connected to a first comparison input voltage VIN1Said third resistance R3And said fourth resistor R4Are all connected with the first operational amplifier A1Is connected to the positive input terminal of the fourth resistor R4Is grounded, and the second resistor R2And the first operational amplifier A1The output ends of the two are connected;
the second differential operation module comprises a fourth operational amplifier A4And a twelfth resistor R12A thirteenth resistor R13A fourteenth resistor R14And a fifteenth resistor R15；
The twelfth resistor R12Is connected to a second excitation function g2The twelfth resistor R12The second terminal of (1), the thirteen resistors R13And the fourth operational amplifier A4Is connected to the reverse input terminal of the fourth resistor R14Is connected to a second comparison input voltage VIN2The fourteenth resistance R14And the fifteenth resistor R15And the first ends of the first and second operational amplifiers A4Is connected to the positive input terminal of the first resistor, and the fifteenth resistor R15Is grounded, and the thirteenth resistor R13And the fourth operational amplifier a4The output ends of the two are connected;
the third differential operation module comprises a seventh operational amplifier A7Twenty third resistor R23Twenty-fourth resistor R24Twenty-fifth resistor R25And a twenty-sixth resistor R26；
The twenty-third resistor R23Is connected to a third excitation function g3The twenty-three resistance R23Second terminal, twenty-fourth resistor R24And the seventh operational amplifier A7Is connected to the reverse input terminal of the first resistor, the twenty-fifth resistor R25Is connected to a third comparison input voltage VIN3Twenty-fifth resistanceR25And said twenty-sixth resistor R26Are all connected with the seventh operational amplifier A7Is connected to the positive input terminal of the first resistor, and the twenty-sixth resistor R26Is grounded, the twenty-fourth resistor R24And the seventh operational amplifier a7Are connected with each other.
5. The long-short term memory autonomous switching circuit of claim 4 wherein the first absolute value block comprises a fifth resistance R5A sixth resistor R6A seventh resistor R7An eighth resistor R8A ninth resistor R9A tenth resistor R10An eleventh resistor R11A first diode D1A second diode D2A second operational amplifier A2And a third operational amplifier A3；
Ninth resistor R9First terminal and fifth resistor R5First terminal of (1) and first operational amplifier A1Is connected to the output terminal of the fifth resistor R5Second terminal, sixth resistor R6First terminal, first diode D1First terminal and second operational amplifier A2Is connected to the reverse input terminal of the seventh resistor R7First terminal and second operational amplifier A2Is connected to the positive input terminal of a first diode D1Second terminal, second diode D2First terminal and second operational amplifier A2The output ends of the two are connected;
eighth resistor R8Second terminal, ninth resistor R9Second terminal, tenth resistor R10First terminal of and third operational amplifier A3Is connected to the reverse input terminal of the first resistor R11First terminal of and third operational amplifier A3Is connected to the positive input terminal of the tenth resistor R10Second terminal, thirty-fourth resistor R34First terminal of and third operational amplifier A3The output ends of the two are connected;
the second absolute value module comprises a sixteenth resistor R16Seventeenth resistor R17Eighteenth resistor R18Nineteenth resistor R19Twentieth resistor R20Twenty-first resistor R21A twenty-second resistor R22A third diode D3A fourth diode D4A fifth operational amplifier A5And a sixth operational amplifier A6；
Twentieth resistor R20First terminal and sixteenth resistor R16First terminal of and fourth operational amplifier A4Is connected to the sixteenth resistor R16A second terminal, a seventeenth resistor R17First terminal of, third diode D3First terminal of and fifth operational amplifier A5Is connected to the eighteenth resistor R18Is connected to the positive input terminal of a fifth operational amplifier a5, a third diode D3Second terminal, fourth diode D4First terminal of and fifth operational amplifier A5The output ends of the two are connected;
nineteenth resistor R19Second terminal, twentieth resistor R20Second terminal, twenty-first resistor R21First terminal of and sixth operational amplifier A6Is connected to the second twenty-second resistor R22First terminal of and sixth operational amplifier A6Is connected to the positive input terminal of the first resistor R21Second terminal, thirty-fifth resistor R35First terminal of and sixth operational amplifier A6The output ends of the two are connected;
the third absolute value module comprises a twenty-seventh resistor R27Twenty eighth resistor R28Twenty ninth resistor R29Thirty-th resistor R30And a thirty-first resistor R31Thirty-second resistor R32And a thirty-third resistor R33A fifth diode D5A sixth diode D6An eighth operational amplifier A8And a ninth operational amplifier A9；
A thirty-first resistor R31First terminal and twenty-seventh resistor R27Are all connected with a seventh operational amplifier A7Is connected to a twenty-seventh resistor R27Second terminal, twenty-eighth resistor R28First terminal of, fifth diode D5First terminal and eighth operational amplifier A8Is connected to the reverse input terminal of the first resistor R29First terminal and eighth operational amplifier A8Is connected to the positive input terminal of a fifth diode D5Second terminal, sixth diode D6First terminal and eighth operational amplifier A8The output ends of the two are connected;
thirtieth resistor R30Second terminal, thirty-first resistor R31Second terminal, thirty-second resistor R32First terminal and ninth operational amplifier A9Is connected to the reverse input terminal of the third resistor R33First terminal and ninth operational amplifier A9Is connected to the positive input terminal of the first resistor, a thirty-second resistor R32Second terminal, thirty-sixth resistor R36First terminal and ninth operational amplifier A9The output ends of the two are connected;
a seventh resistor R7Second terminal, eleventh resistor R11Second terminal, eighteenth resistor R18Second terminal, twenty-second resistor R22Second terminal, twenty-ninth resistor R29Second terminal, thirty-third resistor R33Are all grounded.
6. The self-sustained short-duration memory conversion circuit of claim 5, wherein the summation comparison module comprises a thirty-fourth resistor R34Thirty-fifth resistor R35Thirty-sixth resistor R36Thirty-seventh resistor R37Thirty-eighth resistor R38Thirty-ninth resistor R39A tenth operational amplifier and an eleventh operational amplifier;
thirty-fourth resistor R34First terminal of and third operational amplifier A3Is connected to the thirty-fifth resistor R35First terminal of and sixth operational amplifier A6Is connected to the thirty-sixth resistor R36First terminal and ninth operational amplifier A9Is connected to the output terminal of the third resistor R34Second terminal, thirty-fifth resistor R35Second terminal, thirty-sixth resistor R36Second terminal, thirty-seventh resistor R37First terminal and tenth operational amplifier A10Is connected to the inverting input terminal of a tenth operational amplifier A10Is grounded, and a thirty-seventh resistor R37Second terminal, thirty-eighth resistor R38First terminal and tenth operational amplifier A10The output ends of the two are connected;
thirty-eighth resistor R38Second terminal of and eleventh operational amplifier A11Is connected to the reverse input terminal of the switch, a thirty-ninth resistor R39First terminal of (1) is connected to a first reference voltage VrefThirty-ninth resistor R39Second terminal of and eleventh operational amplifier A11Is connected to the positive input terminal.
7. The autonomous long-short term memory conversion circuit according to claim 6, wherein said control module comprises a fortieth resistor R40A forty-first resistor R41A forty-second resistor R42A forty-third resistor R43A forty-fourth resistor R44A forty-fifth resistor R45The twelfth operational amplifier A12Thirteenth operational amplifier A13And twentieth memristor MS2；
Fortieth resistor R40First terminal of and eleventh operational amplifier A11The output ends of the two are connected; fortieth resistor R40Second terminal, forty-first resistor R41Second terminal, forty-second resistor R42First terminal of and twelfth operational amplifier A12Is connected to the reverse input terminal of the first resistor R41First end of (2) is connected to a first enable voltage VENThe twelfth operational amplifier A12Is grounded, and a forty-second resistor R42Second terminal and a forty-third resistor R43First terminal of and twelfth operational amplifier A12The output ends of the two are connected;
a forty-third resistor R43Second terminal, forty-fourth resistor R44First terminal of and thirteenth operational amplifier A13Is connected to the inverting input terminal of a thirteenth operational amplifier A13Is grounded, and a forty-fourth resistor R44Second terminal, twentieth memristor MS2First terminal of and thirteenth operational amplifier A13The output ends of the two are connected;
twentieth memristor MS2Second terminal and a forty-fifth resistor R45Is connected as an output of the control module.
CN202111213175.7A 2021-10-19 2021-10-19 Long-short-time memory autonomous switching circuit based on memristor cross array Pending CN113988278A (en)

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