CN113985955A - Band gap reference circuit and control method - Google Patents

Band gap reference circuit and control method Download PDF

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CN113985955A
CN113985955A CN202111462894.2A CN202111462894A CN113985955A CN 113985955 A CN113985955 A CN 113985955A CN 202111462894 A CN202111462894 A CN 202111462894A CN 113985955 A CN113985955 A CN 113985955A
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depletion type
drain electrode
tube
pipe
depletion
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杨士斌
黄照兴
丁懿慧
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Kaiqiang Technology Pingtan Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to a band gap reference circuit and a control method, wherein the band gap reference circuit comprises: the constant current power supply module at least comprises a starting unit and a current mirror unit, the compensation module comprises at least one enhancement type MOS tube and at least one depletion type MOS tube, the drain electrode of a PMOS tube MP5 is connected with the drain electrode of a first enhancement type MOS tube in the compensation module, and the source electrode of the first enhancement type MOS tube is connected with the drain electrode of a second depletion type MOS tube; or the drain electrode of the PMOS tube MP5 is connected with the drain electrode of the first depletion type MOS tube in the compensation module, and the source electrode of the first depletion type MOS tube is connected with the drain electrode of the second enhancement type MOS tube, so that the problems of large circuit power consumption and complex circuit existing in the prior art of constructing a zero-temperature band gap reference by adopting the negative temperature characteristic of the emitter-base voltage of the BJT tube are solved, and the effects of reducing power consumption and reducing the circuit area while realizing the zero temperature of the voltage are achieved.

Description

Band gap reference circuit and control method
Technical Field
The invention relates to the technical field of power supply, in particular to a band-gap reference circuit and a control method.
Background
The band-gap reference voltage source is an indispensable component in an analog integrated circuit, and plays a vital role in the design of integrated circuits such as a lithium battery protection chip, an LED driving chip, a linear voltage regulator (LDO), a power management chip, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a dynamic memory (DRAM), a Flash memory and the like.
Fig. 1 is a circuit diagram of a bandgap reference voltage source in the prior art, and as shown in fig. 1, the bandgap reference voltage source in the prior art adopts a negative temperature characteristic of emitter-base voltage of a bipolar transistor (BJT) to construct a zero-temperature bandgap reference, that is, two bipolar transistors are adopted to bias the bandgap reference voltage source at different current densities, a positive temperature current is generated through a base-emitter voltage difference value of the two transistors, the positive temperature current flows through a certain number of resistors to generate a positive temperature voltage, and the positive temperature voltage is superimposed with the base-emitter voltage (negative temperature voltage) of the bipolar transistor, so as to obtain a reference voltage unrelated to temperature.
In the prior art, a band-gap reference circuit adopts a bipolar transistor, so that the working current is large, the power consumption is high, and the extra loss is also caused by the flowing of current at the base of the bipolar transistor.
Disclosure of Invention
The invention aims to provide a band gap reference circuit and a control method to solve the defects in the prior art, and the technical problem to be solved by the invention is realized by the following technical scheme.
In a first aspect, an embodiment of the present invention provides a bandgap reference circuit, including: the constant current power supply module at least comprises a starting unit and a current mirror unit, the compensation module comprises at least one enhancement type MOS (metal oxide semiconductor) tube and at least one depletion type MOS tube, the enhancement type MOS tube is connected with the depletion type MOS tube in series, the starting unit is connected with the current mirror unit, and the source electrode of a PMOS (P-channel metal oxide semiconductor) tube MP5 in the current mirror unit is connected with a preset voltage;
the drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first enhancement type MOS tube in the compensation module, and the source electrode of the first enhancement type MOS tube is connected with the drain electrode of a second depletion type MOS tube;
or the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first depletion type MOS pipe in the compensation module, and the source electrode of the first depletion type MOS pipe is connected with the drain electrode of a second enhancement type MOS pipe.
Optionally, the compensation module comprises an enhancement NMOS transistor and a plurality of depletion NMOS transistors,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first depletion type NMOS pipe in the compensation module, the source electrode of the first depletion type NMOS pipe is connected with the drain electrode of a second enhancement type NMOS pipe, the source electrode of the second enhancement type NMOS pipe is connected with the drain electrode of a third depletion type NMOS pipe until the first depletion type NMOS pipe and the second enhancement type NMOS pipe are connected in series to an Nth depletion type NMOS pipe, wherein N is a natural number larger than 0.
Alternatively, the source electrode of the third depletion type NMOS tube and the drain electrode of the fourth depletion type NMOS tube are connected in series,
the source electrode of the fourth depletion type NMOS tube is connected with the drain electrode of the fifth depletion type NMOS tube in series,
the source electrode of the fifth depletion type NMOS tube is connected with the drain electrode of the sixth depletion type NMOS tube in series,
the source electrode of the sixth depletion type NMOS tube is connected with the drain electrode of the seventh depletion type NMOS tube in series,
the source electrode of the seventh depletion type NMOS tube is connected with the drain electrode of the eighth depletion type NMOS tube in series,
the source electrode of the eighth depletion type NMOS tube is connected with the drain electrode of the ninth depletion type NMOS tube in series,
the source electrode of the ninth depletion type NMOS tube is connected with the drain electrode of the tenth depletion type NMOS tube in series,
the source electrode of the tenth depletion type NMOS tube is connected with the drain electrode of the eleventh depletion type NMOS tube in series,
the source of the eleventh NMOS transistor M11 (depletion mode) is grounded.
Optionally, the compensation module comprises a depletion type NMOS transistor and a plurality of enhancement type NMOS transistors,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first enhancement type NMOS pipe in the compensation module, the source electrode of the first enhancement type NMOS pipe is connected with the drain electrode of a second depletion type NMOS pipe, the source electrode of the second depletion type NMOS pipe is connected with the drain electrode of a third enhancement type NMOS pipe until the first enhancement type NMOS pipe and the second enhancement type NMOS pipe are connected in series to an Mth enhancement type NMOS pipe, wherein M is a natural number larger than 0.
Optionally, the compensation module comprises an enhancement type PMOS tube and a plurality of depletion type PMOS tubes,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first depletion type PMOS pipe in the compensation module, the source electrode of the first depletion type PMOS pipe is connected with the drain electrode of a second enhancement type PMOS pipe, and the source electrode of the second enhancement type PMOS pipe is connected with the drain electrode of a third depletion type PMOS pipe until the first depletion type PMOS pipe and the second enhancement type PMOS pipe are connected in series to an X depletion type PMOS pipe, wherein X is a natural number larger than 0.
Optionally, the compensation module comprises a depletion type PMOS tube and a plurality of enhancement type PMOS tubes,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first enhancement type PMOS pipe in the compensation module, the source electrode of the first enhancement type PMOS pipe is connected with the drain electrode of a second depletion type PMOS pipe, the source electrode of the second depletion type PMOS pipe is connected with the drain electrode of a third enhancement type PMOS pipe until the first enhancement type PMOS pipe is connected with the drain electrode of a Y enhancement type PMOS pipe in series, wherein Y is a natural number larger than 0.
Optionally, the current mirror unit includes a MOS transistor MP1, a MOS transistor MP2, a MOS transistor MN1, a MOS transistor MN2, a MOS transistor MP3, and a MOS transistor MP5, where the MOS transistor MP1 and the MOS transistor MP2 are current mirror structures, the MOS transistor MN1 and the MOS transistor MN2 are current mirror structures, and the MOS transistor MP3 and the MOS transistor MP5 are current mirror structures;
the starting unit comprises an MOS tube MP3, an MOS tube MN3, an MOS tube MN4, an MOS tube MN5, an MOS tube MP4, an MOS tube MN6 and an MOS tube MN 7.
Optionally, a fuse is connected in parallel to the series branch of the enhancement MOS transistor or the series branch of the depletion MOS transistor.
Optionally, the compensation module comprises a depletion type NMOS transistor and an enhancement type NMOS transistor, or two depletion type NMOS transistors and an enhancement type NMOS transistor.
In a second aspect, an embodiment of the present invention provides a control method for a bandgap reference circuit, where the control method includes:
acquiring a negative temperature voltage value of a depletion type MOS tube grid source voltage and an enhancement type MOS tube grid source voltage;
determining positive temperature coefficient voltage according to the difference value of the negative temperature voltage value and the grid-source voltage;
determining a positive temperature current according to the positive temperature coefficient voltage and the linear region resistance of the enhanced MOS tube;
determining a positive temperature voltage according to the positive temperature current and the linear region resistance of the enhancement type MOS tube;
and adjusting a proportionality coefficient according to the positive temperature voltage and the negative temperature voltage of the grid source voltage of the depletion type MOS tube so that the zero temperature coefficient of the voltage is smaller than a preset value.
The embodiment of the invention has the following advantages:
the band gap reference circuit and the control method provided by the embodiment of the invention comprise: the bandgap reference circuit includes: the constant current power supply module at least comprises a starting unit and a current mirror unit, the compensation module comprises at least one enhancement type MOS (metal oxide semiconductor) tube and at least one depletion type MOS tube, the enhancement type MOS tube is connected with the depletion type MOS tube in series, the starting unit is connected with the current mirror unit, and the source electrode of a PMOS (P-channel metal oxide semiconductor) tube MP5 in the current mirror unit is connected with a preset voltage; the drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first enhancement type MOS tube in the compensation module, and the source electrode of the first enhancement type MOS tube is connected with the drain electrode of a second depletion type MOS tube; or the drain electrode of the PMOS tube MP5 is connected with the drain electrode of the first depletion type MOS tube in the compensation module, and the source electrode of the first depletion type MOS tube is connected with the drain electrode of the second enhancement type MOS tube, so that the problems of large circuit power consumption and complex circuit existing in the prior art of constructing a zero-temperature band gap reference by adopting the negative temperature characteristic of the emitter-base voltage of the BJT tube are solved, and the effects of reducing power consumption and reducing the circuit area while realizing the zero temperature of the voltage are achieved.
Drawings
FIG. 1 is a circuit diagram of a conventional bandgap reference voltage source in the prior art;
FIG. 2 is a schematic diagram of a bandgap reference circuit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a depletion NMOS transistor and enhancement NMOS transistor series branch according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a depletion NMOS transistor and an enhancement NMOS transistor in series according to yet another embodiment of the present invention;
FIG. 5 is a circuit diagram of a depletion NMOS transistor and an enhancement NMOS transistor in series branch according to another embodiment of the present invention;
FIG. 6 is a circuit diagram of a depletion mode PMOS transistor and an enhancement mode PMOS transistor in series branch according to an embodiment of the present invention;
fig. 7 is a circuit diagram of a depletion type PMOS transistor and an enhancement type PMOS transistor series branch according to still another embodiment of the invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 2, a schematic diagram of a bandgap reference circuit according to an embodiment of the present invention is shown, where the bandgap reference circuit includes: the constant current power supply module at least comprises a starting unit and a current mirror unit, the compensation module comprises at least one enhancement type MOS (metal oxide semiconductor) tube and at least one depletion type MOS tube, the enhancement type MOS tube is connected with the depletion type MOS tube in series, the starting unit is connected with the current mirror unit, and the source electrode of a PMOS (P-channel metal oxide semiconductor) tube MP5 in the current mirror unit is connected with a preset Voltage (VDD);
the drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first enhancement type MOS tube in the compensation module, and the source electrode of the first enhancement type MOS tube is connected with the drain electrode of a second depletion type MOS tube;
or the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of the first depletion type MOS pipe in the compensation module, and the source electrode of the first depletion type MOS pipe is connected with the drain electrode of the second enhancement type MOS pipe.
Specifically, the embodiment of the present invention provides a bandgap reference circuit, which includes a group of constant current sources (constant gm current sources), that is, a constant current source module, where the constant current source module does not change with voltage, the constant current source module includes a starting unit and a current mirror unit, the starting unit is connected to the current mirror unit, the current mirror unit includes a MOS transistor MP1, a MOS transistor MP2, a MOS transistor MN1, a MOS transistor MN2, a MOS transistor MP3, and a MOS transistor MP5, and the MOS transistors MP1 and MP2 are current mirror structures, the MOS transistors MN1 and MN2 are current mirror structures, and the transistors MP3 and MP5 are current mirror structures;
the starting unit comprises a MOS tube MP3, a MOS tube MN3, a MOS tube MN4, a MOS tube MN5, a MOS tube MP4, a MOS tube MN6 and a MOS tube MN 7.
The compensation module includes at least one enhancement type MOS transistor and at least one depletion type MOS transistor, where the enhancement type MOS transistor and the depletion type MOS transistor are connected in series, for example, the compensation module may include one enhancement type MOS transistor and a plurality of depletion type MOS transistors, or may include one depletion type MOS transistor and a plurality of enhancement type MOS transistors, in an embodiment of the present invention, the plurality of enhancement type MOS transistors refers to two or more, and the MOS transistors may be NMOS transistors or PMOS transistors, which is not limited specifically herein.
As an alternative implementation, the compensation module may include a depletion type MOS transistor and a plurality of enhancement type MOS transistors, the drain of the PMOS transistor MP5 is connected to the drain of the first enhancement type MOS transistor in the compensation module, the source of the first enhancement type MOS transistor is connected to the drain of the second depletion type MOS transistor, the source of the second depletion type MOS transistor is connected to the drain of the third depletion type MOS transistor, and in this way, the depletion type MOS transistors are connected in series;
as another optional implementation, the compensation module comprises an enhancement type MOS transistor and a plurality of depletion type MOS transistors, wherein a drain of the PMOS transistor MP5 is connected to a drain of a first depletion type MOS transistor in the compensation module, a source of the first depletion type MOS transistor is connected to a drain of a second enhancement type MOS transistor, and a source of the second enhancement type MOS transistor is connected to a drain of a third enhancement type MOS transistor, and in this way, the compensation module is connected in series with the plurality of enhancement type MOS transistors.
A transistor group formed by connecting enhancement type MOS tubes in series with depletion type MOS tubes is added to compensate the constant current power supply module.
As shown in fig. 4, the serial branch of the depletion type NMOS transistor and the enhancement type NMOS transistor in the embodiment of the present invention is formed by connecting one enhancement type NMOS transistor (M2) in series with a plurality of depletion type NMOS transistors (M1, M3, M4, M5, M6, M7, M8, M9, M10, and M11), and the gate-source voltage Vgs of the NMOS transistor is superimposed, and the proportionality coefficient is adjusted to realize the zero temperature coefficient of voltage.
Specifically, the compensation module comprises an enhancement NMOS transistor and a plurality of depletion NMOS transistors,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first depletion type NMOS pipe in the compensation module, the source electrode of the first depletion type NMOS pipe is connected with the drain electrode of a second enhancement type NMOS pipe, and the source electrode of the second enhancement type NMOS pipe is connected with the drain electrode of a third depletion type NMOS pipe until the first depletion type NMOS pipe and the second enhancement type NMOS pipe are connected in series to an Nth depletion type NMOS pipe, wherein N is a natural number larger than 0.
Specifically, the source electrode of the third depletion type NMOS tube and the drain electrode of the fourth depletion type NMOS tube are connected in series,
the source electrode of the fourth depletion type NMOS tube is connected with the drain electrode of the fifth depletion type NMOS tube in series,
the source electrode of the fifth depletion type NMOS tube is connected with the drain electrode of the sixth depletion type NMOS tube in series,
the source electrode of the sixth depletion type NMOS tube is connected with the drain electrode of the seventh depletion type NMOS tube in series,
the source electrode of the seventh depletion type NMOS tube is connected with the drain electrode of the eighth depletion type NMOS tube in series,
the source electrode of the eighth depletion type NMOS tube is connected with the drain electrode of the ninth depletion type NMOS tube in series,
the source electrode of the ninth depletion type NMOS tube is connected with the drain electrode of the tenth depletion type NMOS tube in series,
the source electrode of the tenth depletion type NMOS tube is connected with the drain electrode of the eleventh depletion type NMOS tube in series,
and the source electrode of the eleventh depletion type NMOS tube is grounded.
In fig. 4, the drain of MP5 of the constant current source is connected to the drain of the first NMOS transistor M1 (depletion type), the source of the first NMOS transistor M1 (depletion type) is connected in series with the drain of the second NMOS transistor M2 (enhancement type), the source of the second NMOS transistor M2 (enhancement type) is connected in series with the drain of the third NMOS transistor M3 (depletion type), the source of the third NMOS transistor M3 (depletion type) is connected in series with the drain of the fourth NMOS transistor M4 (depletion type), the source of the fourth NMOS transistor M4 (depletion type) is connected in series with the drain of the fifth NMOS transistor M5 (depletion type), the source of the fifth NMOS transistor M5 (depletion type) is connected in series with the drain of the sixth NMOS transistor M6 (depletion type), the source of the sixth NMOS transistor M6 (depletion type) is connected in series with the drain of the seventh NMOS transistor M7 (depletion type), the drain of the seventh NMOS transistor M7 (depletion type) is connected in series with the drain of the eighth NMOS transistor M8, the drain of the ninth NMOS transistor M8 (depletion type), the source electrode of the ninth NMOS tube M9 (depletion type) is connected in series with the drain electrode of the tenth NMOS tube M10 (depletion type), the source electrode of the tenth NMOS tube M10 (depletion type) is connected in series with the drain electrode of the eleventh NMOS tube M11 (depletion type), the source electrode of the eleventh NMOS tube M11 (depletion type) is grounded, current is converted into voltage, the superposition compensation of positive temperature coefficient voltage generated by the enhancement type NMOS tube and grid source voltage with negative temperature coefficient of the depletion type) NMOS tube is realized, and the superposed zero temperature coefficient voltage is output.
As shown in fig. 5, the compensation module includes a depletion NMOS transistor and a plurality of enhancement NMOS transistors, the drain of the PMOS transistor MP5 is connected to the drain of the first enhancement NMOS transistor in the compensation module, the source of the first enhancement NMOS transistor is connected to the drain of the second depletion NMOS transistor, the source of the second depletion NMOS transistor is connected to the drain of the third enhancement NMOS transistor, and so on, until the mth enhancement NMOS transistor is connected in series, where M is a natural number greater than 0.
That is, the embodiment of the present invention provides a serial branch of a depletion type NMOS transistor and an enhancement type NMOS transistor, which is formed by connecting a depletion type NMOS transistor (M2) to a plurality of enhancement type NMOS transistors (M1, M3, M4, M5, M6, M7, M8, M9, M10, and M11) in series, and superimposes a gate-source voltage Vgs of the NMOS transistor, thereby adjusting a proportionality coefficient and realizing a zero-temperature-coefficient of voltage.
As shown in fig. 6, optionally, the compensation module comprises an enhancement PMOS transistor and a plurality of depletion PMOS transistors,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first depletion type PMOS pipe in the compensation module, the source electrode of the first depletion type PMOS pipe is connected with the drain electrode of a second enhancement type PMOS pipe, and the source electrode of the second enhancement type PMOS pipe is connected with the drain electrode of a third depletion type PMOS pipe until the drain electrodes are connected with an X depletion type PMOS pipe in series, wherein X is a natural number larger than 0.
Specifically, under the process of only a depletion type PMOS transistor, the embodiment of the present invention provides a depletion type PMOS transistor and an enhancement type PMOS transistor in series, where the depletion type PMOS transistor and the enhancement type PMOS transistor are connected in series, and the depletion type PMOS transistor and the enhancement type PMOS transistor are formed by connecting one enhancement type PMOS transistor (M2) in series with a plurality of depletion type PMOS transistors (M1, M3, M4, M5, M6, M7, M8, M9, M10, and M11), and gate-source voltages Vgs of the PMOS transistors are superimposed to adjust a proportionality coefficient, so that a zero temperature coefficient of voltage can also be achieved.
As shown in fig. 7, the compensation module includes a depletion PMOS transistor and a plurality of enhancement PMOS transistors, the drain of the PMOS transistor MP5 is connected to the drain of the first enhancement PMOS transistor in the compensation module, the source of the first enhancement PMOS transistor is connected to the drain of the second enhancement PMOS transistor, the source of the second depletion PMOS transistor is connected to the drain of the third enhancement PMOS transistor, and so on, until the drain is connected to the Y enhancement PMOS transistor in series, where Y is a natural number greater than 0.
Specifically, in the process of only using a depletion type PMOS transistor, the serial branch of the depletion type PMOS transistor and the enhancement type PMOS transistor provided in the embodiment of the present invention is formed by connecting a plurality of enhancement type PMOS transistors (M1, M3, M4, M5, M6, M7, M8, M9, M10, and M11) in series with one depletion type PMOS transistor (M2), and the gate-source voltage Vgs of the PMOS transistor is superimposed to adjust the proportionality coefficient, so that the zero temperature coefficient of the voltage can also be realized.
Optionally, a fuse is connected in parallel to the series branch of the enhancement type MOS transistor or the series branch of the depletion type MOS transistor.
The embodiment of the invention also provides a simple fuse trimming mode, and the fuse can be easily blown by laser or power-on mode by only designing the size of the binary NMOS tube on the serial branch of the depletion type NMOS tube and the enhancement type NMOS tube, so that the trimming of the reference voltage can be easily completed.
Optionally, the compensation module comprises one depletion type NMOS transistor and one enhancement type NMOS transistor, or two depletion type NMOS transistors and one enhancement type NMOS transistor.
As shown in fig. 3, the bandgap reference circuit of the embodiment of the invention has low power consumption and simple circuit, and can be implemented by only using one or two depletion NMOS transistors and one enhancement NMOS transistor in series, so that the bandgap reference circuit is widely applied to devices such as a lithium battery protection chip, an LED driving chip DC-DC converter, a digital-to-analog converter, an analog-to-digital converter, and the like, and has strong practicability.
The embodiment of the invention also provides a control method based on the band-gap reference circuit, which comprises the following steps:
acquiring a negative temperature voltage value of a depletion type MOS tube grid source voltage and an enhancement type MOS tube grid source voltage;
determining positive temperature coefficient voltage according to the difference value of the negative temperature voltage value and the grid-source voltage;
determining a positive temperature current according to the positive temperature coefficient voltage and the linear region resistance of the enhanced MOS tube;
determining a positive temperature voltage according to the positive temperature current and the linear region resistance of the enhanced MOS tube;
and adjusting the proportionality coefficient according to the positive temperature voltage and the negative temperature voltage of the grid source voltage of the depletion type MOS tube so that the zero temperature coefficient of the voltage is smaller than a preset value.
Specifically, as shown in the circuit diagram of fig. 2, when the current in the branches of MN1, MN2, MP1, MP2, and MP5 is too low or 0, MP3 also enters the cut-off region, so that the gate voltage of MN6 is reduced to 0V to cut off MN6, and the gate voltage of MN7 is raised to enter the threshold region, so that the gate voltages of MP1 and MP2 can be pulled down to enter the threshold region. Once the gate voltages of MP1 and MP2 enter the threshold region, MP3 also enters the threshold region to make the start-up circuit no longer restart, and the constant current source circuit current-voltage characteristic can be expressed as:
Figure BDA0003388098380000091
wherein, I0Representing reverse saturation current, ξ representing a non-ideality factor, greater than 1,
VGSthe gate source voltage of the MOS tube is shown, VT is thermal voltage, VT is KT/q, K is Boltzmann constant, and q is electron charge quantity.
Two pairs of current mirror structures are formed by the Keschefflf voltage laws MN1 and MN2, and can be listed as follows:
VGS1＝VGS2+ID2×R1………(2)
substituting the uppermost formula (1) into formula (2) can result in the following:
Figure BDA0003388098380000092
wherein ID1Base current flowing through MN 1;
ID2base current flowing through MN 2;
VT1represents the thermal voltage of MN 1;
VT2indicating the voltage of heat;
μnelectron drift rate;
COXoxide layer capacitance value;
k: boltzmann constant;
Figure BDA0003388098380000101
the ratio of the length to the width of the MOS tube,
by finishing the formula (3), the compound
Figure BDA0003388098380000102
The current irrelevant to VDD is obtained after (4) is square of two sides and term shift,
Figure BDA0003388098380000103
but still related to the temperature, the zero temperature coefficient of voltage can be adjusted by adding the serial branch proportions of the depletion type MOS tube and the enhancement type MOS tube together. ,
the method comprises the steps of utilizing the negative temperature characteristic of the grid source voltage of a depletion type MOS tube connected with a drain electrode and a grid electrode to generate positive temperature coefficient voltage according to the difference value of the grid source voltage Vgs of an enhancement type NMOS tube, dividing the positive temperature coefficient voltage by the resistance of a linear region NMOS tube to obtain positive temperature current, multiplying the positive temperature current by the resistance of the linear region NMOS tube to obtain positive temperature voltage, superposing the negative temperature voltage Vgs of the grid source voltage of the depletion type NMOS tube, adjusting the proportional coefficient, and realizing the zero temperature coefficient of voltage.
The band gap reference circuit and the control method provided by the embodiment of the invention have the following advantages that: the bandgap reference circuit includes: the constant current power supply module at least comprises a starting unit and a current mirror unit, the compensation module comprises at least one enhancement type MOS (metal oxide semiconductor) tube and at least one depletion type MOS tube, the enhancement type MOS tube is connected with the depletion type MOS tube in series, the starting unit is connected with the current mirror unit, and the source electrode of a PMOS (P-channel metal oxide semiconductor) tube MP5 in the current mirror unit is connected with a preset voltage; the drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first enhancement type MOS tube in the compensation module, and the source electrode of the first enhancement type MOS tube is connected with the drain electrode of a second depletion type MOS tube; or the drain electrode of the PMOS tube MP5 is connected with the drain electrode of the first depletion type MOS tube in the compensation module, and the source electrode of the first depletion type MOS tube is connected with the drain electrode of the second enhancement type MOS tube, so that the problems of large circuit power consumption and complex circuit existing in the prior art of constructing a zero-temperature band gap reference by adopting the negative temperature characteristic of the emitter-base voltage of the BJT tube are solved, and the effects of reducing power consumption and reducing the circuit area while realizing the zero temperature of the voltage are achieved.
It should be noted that the above detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. Furthermore, it will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in other sequences than those illustrated or otherwise described herein.
Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may also be oriented in other different ways, such as by rotating it 90 degrees or at other orientations, and the spatially relative descriptors used herein interpreted accordingly.
In the foregoing detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, like numerals typically identify like components, unless context dictates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A bandgap reference circuit, comprising: the constant current power supply module at least comprises a starting unit and a current mirror unit, the compensation module comprises at least one enhancement type MOS (metal oxide semiconductor) tube and at least one depletion type MOS tube, the enhancement type MOS tube is connected with the depletion type MOS tube in series, the starting unit is connected with the current mirror unit, and the source electrode of a PMOS (P-channel metal oxide semiconductor) tube MP5 in the current mirror unit is connected with a preset voltage;
the drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first enhancement type MOS tube in the compensation module, and the source electrode of the first enhancement type MOS tube is connected with the drain electrode of a second depletion type MOS tube;
or the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first depletion type MOS pipe in the compensation module, and the source electrode of the first depletion type MOS pipe is connected with the drain electrode of a second enhancement type MOS pipe.
2. The bandgap reference circuit of claim 1, wherein the compensation module comprises an enhancement NMOS transistor and a plurality of depletion NMOS transistors,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first depletion type NMOS pipe in the compensation module, the source electrode of the first depletion type NMOS pipe is connected with the drain electrode of a second enhancement type NMOS pipe, the source electrode of the second enhancement type NMOS pipe is connected with the drain electrode of a third depletion type NMOS pipe until the first depletion type NMOS pipe and the second enhancement type NMOS pipe are connected in series to an Nth depletion type NMOS pipe, wherein N is a natural number larger than 0.
3. The bandgap reference circuit of claim 2,
the source electrode of the third depletion type NMOS tube is connected with the drain electrode of the fourth depletion type NMOS tube in series,
the source electrode of the fourth depletion type NMOS tube is connected with the drain electrode of the fifth depletion type NMOS tube in series,
the source electrode of the fifth depletion type NMOS tube is connected with the drain electrode of the sixth depletion type NMOS tube in series,
the source electrode of the sixth depletion type NMOS tube is connected with the drain electrode of the seventh depletion type NMOS tube in series,
the source electrode of the seventh depletion type NMOS tube is connected with the drain electrode of the eighth depletion type NMOS tube in series,
the source electrode of the eighth depletion type NMOS tube is connected with the drain electrode of the ninth depletion type NMOS tube in series,
the source electrode of the ninth depletion type NMOS tube is connected with the drain electrode of the tenth depletion type NMOS tube in series,
the source electrode of the tenth depletion type NMOS tube is connected with the drain electrode of the eleventh depletion type NMOS tube in series,
the source of the eleventh NMOS transistor M11 (depletion mode) is grounded.
4. The bandgap reference circuit of claim 1, wherein said compensation module comprises a depletion type NMOS transistor and a plurality of enhancement type NMOS transistors,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first enhancement type NMOS pipe in the compensation module, the source electrode of the first enhancement type NMOS pipe is connected with the drain electrode of a second depletion type NMOS pipe, the source electrode of the second depletion type NMOS pipe is connected with the drain electrode of a third enhancement type NMOS pipe until the first enhancement type NMOS pipe and the second enhancement type NMOS pipe are connected in series to an Mth enhancement type NMOS pipe, wherein M is a natural number larger than 0.
5. The bandgap reference circuit of claim 1, wherein the compensation module comprises an enhancement PMOS transistor and a plurality of depletion PMOS transistors,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first depletion type PMOS pipe in the compensation module, the source electrode of the first depletion type PMOS pipe is connected with the drain electrode of a second enhancement type PMOS pipe, and the source electrode of the second enhancement type PMOS pipe is connected with the drain electrode of a third depletion type PMOS pipe until the first depletion type PMOS pipe and the second enhancement type PMOS pipe are connected in series to an X depletion type PMOS pipe, wherein X is a natural number larger than 0.
6. The bandgap reference circuit of claim 1, wherein the compensation module comprises a depletion type PMOS transistor and a plurality of enhancement type PMOS transistors,
the drain electrode of the PMOS pipe MP5 is connected with the drain electrode of a first enhancement type PMOS pipe in the compensation module, the source electrode of the first enhancement type PMOS pipe is connected with the drain electrode of a second depletion type PMOS pipe, the source electrode of the second depletion type PMOS pipe is connected with the drain electrode of a third enhancement type PMOS pipe until the first enhancement type PMOS pipe is connected with the drain electrode of a Y enhancement type PMOS pipe in series, wherein Y is a natural number larger than 0.
7. The bandgap reference circuit of claim 1, wherein the current mirror unit comprises a MOS transistor MP1, a MOS transistor MP2, a MOS transistor MN1, a MOS transistor MN2, a MOS transistor MP3, and a MOS transistor MP5, and the MOS transistor MP1 and the MOS transistor MP2 are current mirror structures, the MOS transistor MN1 and the MOS transistor MN2 are current mirror structures, and the MOS transistor MP3 and the MOS transistor MP5 are current mirror structures;
the starting unit comprises an MOS tube MP3, an MOS tube MN3, an MOS tube MN4, an MOS tube MN5, an MOS tube MP4, an MOS tube MN6 and an MOS tube MN 7.
8. The bandgap reference circuit according to any of claims 1 to 7, wherein a fuse is connected in parallel to the series branch of the enhancement type MOS transistor or the series branch of the depletion type MOS transistor.
9. The bandgap reference circuit of claim 1, wherein the compensation module comprises one depletion type NMOS transistor and one enhancement type NMOS transistor, or two depletion type NMOS transistors and one enhancement type NMOS transistor.
10. A control method based on the bandgap reference circuit as claimed in any one of claims 1 to 9, wherein the control method comprises:
acquiring a negative temperature voltage value of a depletion type MOS tube grid source voltage and an enhancement type MOS tube grid source voltage;
determining positive temperature coefficient voltage according to the difference value of the negative temperature voltage value and the grid-source voltage;
determining a positive temperature current according to the positive temperature coefficient voltage and the linear region resistance of the enhanced MOS tube;
determining a positive temperature voltage according to the positive temperature current and the linear region resistance of the enhancement type MOS tube;
and adjusting a proportionality coefficient according to the positive temperature voltage and the negative temperature voltage of the grid source voltage of the depletion type MOS tube so that the zero temperature coefficient of the voltage is smaller than a preset value.
CN202111462894.2A 2021-12-02 2021-12-02 Band gap reference circuit and control method Pending CN113985955A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115357090A (en) * 2022-08-02 2022-11-18 深圳市诚芯微科技股份有限公司 Zero-power-consumption double-path self-starting circuit and method for band-gap reference regulator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115357090A (en) * 2022-08-02 2022-11-18 深圳市诚芯微科技股份有限公司 Zero-power-consumption double-path self-starting circuit and method for band-gap reference regulator

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