CN113985442A - Terahertz wave readout circuit - Google Patents
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
- G01S17/88—Lidar systems specially adapted for specific applications
- G01S17/89—Lidar systems specially adapted for specific applications for mapping or imaging
- G01S17/894—3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
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- G01S7/4865—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/491—Details of non-pulse systems
- G01S7/4912—Receivers
- G01S7/4915—Time delay measurement, e.g. operational details for pixel components; Phase measurement
Abstract
The present disclosure provides a terahertz wave readout circuit, including: the detector model (A) is used for simulating an input terahertz modulated photocurrent signal to obtain a first analog signal, demodulating the first analog signal and sampling to obtain a sampling signal; the integral amplification module (B) is used for carrying out integral amplification on the sampling signal to obtain an amplified signal; the integrated signal sampling module (C) is used for collecting the terahertz signal value of the amplified signal in an integration period to obtain a sampling integrated signal; the analog-to-digital conversion module (D) is used for converting the sampling integral signal into a digital signal; the sampling signal and the analog terahertz photocurrent signal have phase offset. The readout circuit disclosed by the invention can effectively detect and amplify weak terahertz wave signals, and realizes accurate detection of the weak terahertz waves in TOF imaging.
Description
Technical Field
The utility model relates to a TOF three-dimensional imaging technology field especially relates to a terahertz wave reading circuit.
Background
The TOF (Time of Flight) three-dimensional imaging technology acquires distance information by measuring and calculating the Time of Flight of light. The terahertz wave is an electromagnetic wave with a wave band between millimeter waves and far infrared light and a frequency within the range of 0.1THz to 10 THz. The terahertz wave signal is used as the last window of research in the electromagnetic spectrum, and has important research significance in addition to a plurality of unique properties of the terahertz wave signal.
Terahertz waves detected by the prior art are generally weak, easily submerged by 1/f noise and white noise, and the changed frequency is too high to be easily captured. Ideally, as long as there is a light radiation signal, the signal can be detected by using the detection circuit, but when the detected signal is very weak, the situation that the signal cannot be detected often occurs, so that the design of the terahertz wave reading circuit with a simple structure, strong adaptability, low noise, high linearity and high sensitivity has great research significance.
Disclosure of Invention
Technical problem to be solved
In view of the prior art, the present disclosure provides a terahertz wave readout circuit for at least partially solving the above technical problems.
(II) technical scheme
The present disclosure provides a terahertz wave readout circuit, including: the detector model A is used for simulating an input terahertz modulated photocurrent signal to obtain a first analog signal, demodulating the first analog signal and sampling to obtain a sampling signal; the integral amplification module B is used for carrying out integral amplification on the sampling signal to obtain an amplified signal; the integrated signal sampling module C is used for collecting a terahertz signal value of the amplified signal in an integration period to obtain a sampling integrated signal; the analog-to-digital conversion module D is used for converting the sampling integral signal into a digital signal; the sampling signal and the analog terahertz photocurrent signal have phase offset.
Optionally, the detector model a comprises: first field effect transistor M1 and alternating current source Itof(ii) a Wherein, the AC current source ItofAn AC current source I connected in parallel between the drain and source of the first field effect transistor M1tofThe method is used for simulating a terahertz modulation photocurrent signal to obtain a first simulationA control signal is loaded on the gate of the first field effect transistor M1, the control signal is used for demodulating the first analog signal to obtain a sampling signal, and the source of the first field effect transistor M1 is loaded with a dc bias voltage Vbias; the frequency of the first analog signal is the same as the frequency of the control signal, and the first analog signal and the control signal have a phase offset.
Optionally, the control signal is a rectangular gate control signal, an alternating current source ItofHaving a dc signal component and a continuous wave or pulsed wave ac signal component.
Optionally, the integrating and amplifying module B includes: a first amplifier a1, a reset switch SW1 and a variable integrating capacitor Cf1 connected in parallel with each other; the negative input end of the first amplifier A1 is connected with the output end of the detector model A, and the positive input end of the first amplifier A1 is connected with the reference voltage Vref; the first amplifier a1 and the variable integrating capacitor Cf1 cooperate to perform integral amplification on the sampled signal.
Optionally, the first amplifier a1 is a single-ended output folded cascode structure; the single-ended output folded cascode structure includes: the differential input cascode structure, the differential output active load and the cascode current drive tube.
Optionally, the integrated signal sampling module C comprises: a single slip unit C1 and a sampling circuit unit C2; wherein, the single slip unit C1 is used to convert the amplified signal into a differential signal; the sampling circuit unit C2 is configured to obtain a reset signal and an integrated signal of the differential signal in an integration period, and obtain a sampling integrated signal; the sampling circuit unit C2 includes: a second amplifier a2, a sampling switch SW2 and a variable capacitor Cf2 connected in parallel with each other; wherein the second amplifier a2 samples the differential signal in cooperation with the variable capacitance Cf 2.
Optionally, the single slip unit C1 comprises: a first sampling capacitance Cs0 and a second sampling capacitance Cs 1; the first sampling capacitor Cs0 is used to collect a reset signal, the second sampling capacitor Cs1 is used to collect an integrated signal, and the first sampling capacitor Cs0 and the second sampling capacitor Cs1 are also used to perform charge transfer on the reset signal and the integrated signal.
Optionally, the second amplifier a2 is a differential input-differential output two-stage operational amplifier structure; the differential input-differential output two-stage operational amplifier structure comprises: the first-stage folded cascode amplifying structure A21, the second-stage source follow amplifying structure A22 and the common-mode feedback circuit A23, and the first-stage folded cascode amplifying structure A21 comprises a chopper amplifier for eliminating flicker noise in the second amplifier A2.
Optionally, the analog-to-digital conversion module D includes: the system comprises an integrating amplifier unit I, a quantizer unit J and a feedback unit DAC; the integrating amplifier unit I is used for clearing a residual signal after digital-to-analog conversion by using a reset signal, the quantizer unit J is used for converting an output signal of the integrating amplifier unit I into a digital single-bit signal, and the feedback unit DAC is used for converting part of the digital single-bit signal into a second analog signal and feeding the second analog signal back to the integrating amplifier unit I.
Optionally, the analog-to-digital conversion module D is a three-order cascade integral feedback modulation structure, and includes three integral amplifier units I, one quantizer unit J, and two feedback units DAC; the quantizer unit J includes a dynamic comparator for resetting or amplifying the differential input signal according to the relative magnitude of the bias voltages at the input terminals of the differential input signal and the digital power supply signal, and a latch for latching the amplified differential input signal.
(III) advantageous effects
The utility model provides a terahertz wave reading circuit, carry out the integral amplification to the terahertz light current signal of simulation through the integral amplification module after, convert differential signal and carry out the integral signal sampling in the integral signal sampling module to and convert the integral signal into digital signal in the analog-to-digital conversion module, realized the accurate detection to weak terahertz wave in the TOF formation of image.
By loading the stable direct current bias voltage Vbias on the source electrode of the first field effect transistor M1, the input transconductance of the integral amplification module is close to infinity, the integral amplification module is not influenced by the input analog terahertz photocurrent, and the sensitivity is high.
The integral signal sampling module adopts a single slip structure, converts a single-end output signal into a differential signal to acquire an integral signal, further reduces circuit noise and improves the signal-to-noise ratio.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
fig. 1 schematically illustrates a terahertz wave readout circuit diagram according to an embodiment of the present disclosure;
fig. 2 schematically illustrates a circuit diagram of a first amplifier a1 according to an embodiment of the present disclosure;
fig. 3a schematically shows a circuit diagram of a single slip unit according to an embodiment of the present disclosure;
fig. 3b schematically shows a circuit diagram of a second amplifier a2 according to an embodiment of the present disclosure;
fig. 4 schematically illustrates a circuit diagram of an analog-to-digital conversion module according to an embodiment of the disclosure;
fig. 5a schematically shows a circuit diagram of a dynamic comparator in a quantizer unit according to an embodiment of the disclosure;
FIG. 5b schematically illustrates a circuit diagram of a latch in a quantizer unit according to an embodiment of the disclosure;
fig. 6 schematically illustrates a phase sampling diagram of an indirect four-sample demodulation delay phase method based on continuous wave modulation according to an embodiment of the present disclosure;
fig. 7 schematically illustrates a phase sampling diagram of an indirect double-sampling demodulation delay phase method based on continuous wave modulation according to an embodiment of the present disclosure.
[ description of reference ]
A-detector model
B-integral amplifying module
C-integral signal sampling module
C1-Single slip Unit
C2-sampling circuit unit
D-analog-to-digital conversion module
I-integrator amplifier unit
J-quantizer unit
DAC-feedback unit
M1-first field effect transistor
Itof-a source of alternating current
Vbias-DC bias voltage
Vref-reference Voltage
A1-first Amplifier
A2-second Amplifier
A21-first stage folded cascode amplification structure
A22-second stage source stage following amplifying structure
A23-common mode feedback circuit
SW 1-reset switch
SW 2-sampling switch
Cfi-variable integral capacitance
Cf 2-variable capacitance
Cs 0-first sampling capacitor
Cs 1-second sampling capacitor
Detailed Description
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
It should be noted that in the drawings or description, the same drawing reference numerals are used for similar or identical parts. Features of the embodiments illustrated in the description may be freely combined to form new embodiments without conflict, and each claim may be individually referred to as an embodiment or features of the claims may be combined to form a new embodiment, and in the drawings, the shape or thickness of the embodiment may be enlarged and simplified or conveniently indicated. Further, elements or implementations not shown or described in the drawings are of a form known to those of ordinary skill in the art. Additionally, while exemplifications of parameters including particular values may be provided herein, it is to be understood that the parameters need not be exactly equal to the respective values, but may be approximated to the respective values within acceptable error margins or design constraints.
Unless a technical obstacle or contradiction exists, the above-described various embodiments of the present disclosure may be freely combined to form further embodiments, which are all within the scope of protection of the present disclosure.
While the present disclosure has been described in connection with the accompanying drawings, the embodiments disclosed in the drawings are intended to be illustrative of the preferred embodiments of the disclosure, and should not be construed as limiting the disclosure. The dimensional proportions in the drawings are merely schematic and are not to be understood as limiting the disclosure.
Although a few embodiments of the present general inventive concept have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the claims and their equivalents.
The "cascode structure", "source follower structure", "common mode feedback structure", "comparator structure", "cross-coupled structure", "locker structure", and "cascade feedback structure" referred to in the present disclosure are circuit structures generally understood in the art to realize corresponding functions, and should not be construed as being limited to the circuit structures employed in the embodiments of the present disclosure.
Fig. 1 schematically shows a terahertz wave readout circuit diagram according to an embodiment of the present disclosure.
According to an embodiment of the present disclosure, as shown in fig. 1, a terahertz wave readout circuit includes, for example: a detector model; an integral amplification module, namely a CSA integral module; an integrated signal sampling module, i.e., CDS module; and the analog-to-digital conversion module is an I-ADC module. The terahertz detector model samples terahertz photocurrent signals, then is connected to the CSA integration module, integrates and amplifies the input sampled photocurrent signals, and then converts the sampled integration signals into digital signals through the CDS module and the I-ADC module to be output. The digital signal obtained after four-phase or two-phase sampling can be used for TOF three-dimensional imaging after being processed by an external computer.
According to the embodiment of the disclosure, a detector model (terahertz detector model) is used for simulating and sampling a detected terahertz photocurrent signal and sampling the terahertz photocurrentThe signal is transmitted to the CSA integration module. The terahertz detector model comprises a first field effect transistor (NMOS) M1 and an alternating current source I connected in paralleltof. The alternating current source is used for simulating a continuous wave or pulse wave modulated terahertz photocurrent signal, and the continuous wave can be a sine wave or a square wave (for example, a rectangular wave with a duty ratio of 50%). The modulation frequency of the ac current source is for example 20MHz, the dc component is for example 0.5-5uA, and there is a certain phase delay from the original transmitted signal, which may be for example a phase offset of 90 °. The first field effect transistor (NMOS) M1 includes a source, a drain, and a gate. The grid of the first field effect transistor M1 is used as a sampling control port, the signal frequency is the same as the frequency of the modulated photocurrent signal on the alternating current source, and the signal frequency has a certain phase offset, and the first field effect transistor M1 is used for demodulating the terahertz photocurrent signal and filtering part of high-frequency noise signals. A grid electrode of the M1 is connected with a grid voltage end Vg, a square wave control signal of four-phase or two-phase sampling is loaded on a grid electrode of the field effect transistor M1, the frequency is 20MHz for example, the amplitude is 0.3V-0.9V for example, and when the grid electrode voltage of the M1 is 0.3V, the responsivity of the transistor to the terahertz photocurrent signal is almost zero; when the gate voltage of M1 is 0.9V, a high response at the transistor drain is obtained. And the square wave control signal has a certain phase offset with the original emission signal, for example, phase offset conditions of 0 degrees, 90 degrees, 180 degrees and 270 degrees exist, when the alternating current source simulates a continuous wave modulation photocurrent signal, the square wave control signal with the phase offset of 0 degrees, 90 degrees, 180 degrees and 270 degrees is loaded, and when the alternating current source simulates a pulse wave signal, the square wave control signal with the phase offset of 0 degrees and 180 degrees is loaded. Source of M1 and AC current source ItofAre connected to a dc bias voltage terminal Vbias, set for example to 0.6V, the drain of M1 and an ac current source ItofThe output terminals of the two-way detector are connected with the CSA integration module, namely the drain of the field effect transistor M1 is used for outputting the detected terahertz signal to the CSA integration module.
According to an embodiment of the present disclosure, the CSA is a Charge Sensitive Amplifier (CSA). The CSA integration module is used for carrying out integration amplification on the terahertz photocurrent sampling signal and transmitting the terahertz photocurrent amplification signal to the CDS module.The CSA integration module is provided with a CSA integration circuit unit, wherein A1 is an amplifier, SW1 is a reset switch, Cf1 is a variable integration capacitor, and VrefIs a reference voltage terminal, providing stable read bias voltage control for the first amplifier a1, further reducing noise in the signal. The positive input end (+) of the first amplifier A1 is connected with the reference voltage end VrefThe negative input end (-) is respectively connected with one end of a reset switch SW1, one end of a variable integrating capacitor Cf1 and the output end of the detector model, the other end of the reset switch SW1 and the other end of the variable integrating capacitor Cf1 are both connected with the output end of a first amplifier A1, and the output end of the first amplifier A1 outputs an integrated amplified photocurrent signal Itof(Itof1To Itof4) To the CDS module. When the reset switch SW1 is closed, the CSA integration block is in the reset phase, its negative input is connected to the output, and the variable integration capacitor Cf1 is shorted. When the reset switch SW1 is turned off, the CSA integration module is in the integration phase and performs the integration amplification of the input photocurrent signal. By controlling the size of the field effect transistor and the like, the input transconductance of the amplifier A1 in the CSA integration module can be improved, and further, the thermal noise caused by the leakage current of the detector is weakened. The CSA integration module is a variable gain integration module, namely the variable integration capacitor Cf1 can adjust the size of the accessed capacitor according to the size of the input modulated photocurrent, can adapt to detection signals with different light intensities, and increases the adaptability of the reading circuit. Therefore, the method has the advantages of simple system, high precision, low cost and the like.
Fig. 2 schematically illustrates a circuit diagram of a first amplifier a1 according to an embodiment of the disclosure.
According to an embodiment of the present disclosure, as shown in fig. 2, the first amplifier a1 employs, for example, a single-ended output folded cascode structure. AVDD is an analog power supply voltage end, N0-N7 are all PMOS tubes, N8-N11 are all NMOS tubes, VBP and VBP1, VBN and VBN1 are bias voltage ends, Vi is a terahertz detector model output end, and Vo is an integral amplification photocurrent signal output end. The MOS transistors N2, N3, N8 and N9 form a differential input cascode structure, N4, N5, N6 and N7 are active loads of differential output, and N10 and N11 are cascode current drive transistors. The positive and negative input ends of the first amplifier A1 are respectively connected to the reference voltage Vref and the terahertz detector model output ends Vi, VBN1, VBP and VBP1 to provide stable bias voltages for the MOS tubes of the circuit. The value of the reference voltage Vref is, for example, the same as the dc bias voltage Vbias.
According to the embodiment of the disclosure, the CDS module is used for sampling the reset signal and the integration end signal value of the terahertz photocurrent amplification signal in the integration period thereof, so as to acquire the integrated signal value to form a sampling integrated signal and transmit the sampling integrated signal to the I-ADC module. The CDS module includes, for example, a single-slip unit and a CDS circuit unit, wherein the CDS circuit unit includes a second amplifier a2, a Sampling switch SW2, and a variable capacitor Cf2, and an output signal of the CSA integration module is input to the second amplifier a2 through the single-slip unit in the CDS (Correlated Double Sampling) module. Two input ends of the second amplifier A2 are connected with one end of the variable capacitor Cf2 and the sampling switch, and the other end of the variable capacitor Cf2 and the sampling switch are connected with the output end of the second amplifier A2. And when the single slip unit does not complete conversion, the SW2 is closed, the CDS circuit unit is in an idle state, otherwise, the SW2 is opened, and the CDS circuit unit is in a working state, so that the sampled terahertz signal value of the detector model in the integration period is obtained.
Fig. 3a schematically shows a circuit diagram of a single slip unit according to an embodiment of the present disclosure.
According to the embodiment of the disclosure, as shown in fig. 3a, Vsig is an output signal of the CSA integration block, Vcm is a common-mode voltage, VIP and VIN are converted differential signals, S0 to S2 are switches, and Cs0 and Cs1 are sampling capacitors. When the CSA integration module is in a reset state, the switch S0 is closed, S1 and S2 are opened, and the left and right plates of the sampling capacitor Cs0 collect a reset signal and a common-mode level signal respectively. When the CSA integration module is in an integration state and finishes an integration period, S1 is closed, S0 and S2 are opened, the left and right polar plates of the sampling capacitor Cs1 collect an integration signal and a common-mode level signal respectively, then S2 is closed, S0 and S1 are opened, the sampling capacitors Cs0 and Cs1 carry out charge transfer again, and the function of converting a single-ended output signal of the CSA integration circuit module into a differential signal is achieved.
Fig. 3b schematically shows a circuit diagram of a second amplifier a2 according to an embodiment of the disclosure.
According to the embodiment of the disclosure, as shown in fig. 3b, AVDD is an analog power voltage terminal, GND is an analog ground terminal, P1, P2, P7 to P15, and P23 to P30 are all PMOS transistors, P3 to P6, P16, P17, and P19 to P22 are all NMOS transistors, C1, C2, and C3 are capacitors, R1 to R4 are resistors, chopper 1 and chopper 2 are chopper amplifiers, VBP1, VBP2, VBN1, and VB are bias voltage terminals, CMFB is a common mode feedback voltage terminal, VIP VIN and VIN are output terminals of a single-slip signal, and VOP and VON are output terminals CDS of the amplifier. The second amplifier a2 adopts, for example, a two-stage operational amplifier structure of differential input-differential output, MOS transistors P1 to P12 constitute a first-stage folded cascode amplifier, MOS transistors P19 to P30, a compensation capacitor Cc1, load capacitors C2, C3 and load resistors R1 to R4 constitute a second-stage source follower amplifier, MOS transistors P13 to P17 constitute a common-mode feedback circuit, chopper 1 and chopper 2 are chopper amplifiers, and can further separate noise in signals and eliminate flicker noise of the amplifier.
According to an embodiment of the present disclosure, an I-ADC module is used to convert the sampled integrated signal to a high precision digital output signal. Namely, the differential output signal of the CDS circuit module is connected to an I-ADC (Incremental Analog-Digital Converter) module, and converted into a final Digital output signal.
Fig. 4 schematically shows a circuit diagram of an analog-to-digital conversion module according to an embodiment of the disclosure.
According to the embodiment of the disclosure, as shown in fig. 4, Vin + and Vin-are positive and negative input end signals, Dout is an output digital signal, a 1-a 3 are proportionality coefficients, and Reset is a Reset control signal. The I-ADC module is a single-bit incremental ADC adopting a three-order cascade integral feedback modulation structure, has the characteristics of high precision, high linearity and low noise, converts an analog input signal into a digital output and can be collected by an external FPGA (field programmable gate array). The I-ADC module includes, for example: three integrating amplifier units, one quantizer unit and two DAC units. Each integrating amplifier unit adopts a two-stage cascode amplifier structure, for example, and includes a reset signal for clearing a residual signal after each analog-to-digital conversion of a signal, a quantizer unit for converting the signal passed through the integrating amplifier unit into a final digital single-bit output signal, and a DAC unit for converting a digital signal at an output end into an analog signal and feeding the analog signal back to an input end.
Fig. 5a schematically shows a circuit diagram of a dynamic comparator in a quantizer unit according to an embodiment of the disclosure.
Fig. 5b schematically shows a circuit diagram of a latch in a quantizer unit according to an embodiment of the disclosure.
According to the embodiment of the present disclosure, the quantizer unit includes, for example, a dynamic comparator and a latch, as shown in fig. 5a and 5b, DVDD is a digital power voltage terminal, DVSS is a digital ground terminal, PH1X and PH1XB are bias voltage terminals, Q, QB is an output signal terminal, W0 to W2, W5 to W8, W12 to W15 are NMOS transistors, and W3 to W4, W9 to W11, and W16 to W19 are all PMOS transistors. When PH1X is low PH1XB in fig. 5a is high, the dynamic comparator operates in a reset state, W11 and W0 are turned off, W3 and W4 are turned on, drains of W1 and W2 are precharged to high DVDD, gates of W5 and W8 are turned on, Q and QB are pulled down to ground, and the previous output of the latch in fig. 5b is kept unchanged. When PH1X is high level PH1XB is low level, the dynamic comparator works in an amplification state, W11 and W0 are conducted, differential input signals Vin and Vip are amplified through W1 and W2 tubes and then amplified through a cross-coupled inverter formed by W5-W10, output signals Q and QB are input into the latch, and PB and P are output of the latch.
Fig. 6 schematically illustrates a continuous wave modulation based indirect four-sample demodulation time-of-flight method phase sampling diagram according to an embodiment of the disclosure.
According to an embodiment of the present disclosure, T is shown in FIG. 6tofFor the flight time, the emission signal is a transmission signal (terahertz modulation optical signal), the reflected signal is a reflection signal (reflection signal of the on-chip antenna to the terahertz modulation optical signal), Vg 0-Vg 3 are first to fourth sampling signals, the sampling values are S0-S3 in sequence, and the phase offset from the carrier signal is 0 °, 90 °, 180 ° and 270 ° in sequence. Obtaining the flight time T of the terahertz wave signaltofAnd depth information D are shown in formulas (1) to (2).
Wherein T represents the period of transmitting a single frequency signal, TtofThe time of flight is represented as a function of time,
for the corresponding delay phase, D represents the calculated distance, and c is the signal propagation rate, approximated by the speed of light. The flight time of the terahertz wave signal can be calculated through signal sampling after phase offset, so that the depth of field information of the measured object is obtained, and finally the reading of imaging information is realized.
Fig. 7 schematically illustrates a phase sampling diagram of an indirect double-sampling demodulation time-of-flight method based on continuous wave modulation according to another embodiment of the present disclosure.
According to an embodiment of the present disclosure, T is shown in FIG. 7tofFor the time of flight, an emission signal (terahertz modulation optical signal), a reflected signal (reflection signal of an on-chip antenna to the terahertz modulation optical signal), Vg0 and Vg2 are a first sampling signal and a third sampling signal, two sampling control signal values are selectively selected every 1S, for example, sampling values obtained after sampling by a field effect transistor M1 in a terahertz detector are S respectively0、S2Selecting signal values under the condition of 0-degree and 180-degree 2 phase shift with the transmitted signal to obtain the flight time T of the terahertz wave signaltofAnd depth information D are as shown in equations (3) to (4).
Wherein T represents the period of transmitting a single frequency signal, TtofThe time of flight is represented as a function of time,
d represents the calculated distance for the corresponding delay phase, α is the duty cycle of the pulse wave, and c is the signal propagation rate, which is approximately the speed of light. The flight time of the terahertz wave signal can be calculated through signal sampling after phase offset, so that the depth of field information of the measured object is obtained, and finally the reading of imaging information is realized.
To sum up, the embodiment of the present disclosure provides a terahertz wave readout circuit. After the analog terahertz photocurrent signal is subjected to integral amplification by the CSA integration module, the analog terahertz photocurrent signal is converted into a differential signal in the CDS module and subjected to integral signal sampling, and the integral signal is converted into a high-precision digital signal in the I-ADC module. The reading circuit disclosed by the invention can effectively detect and amplify weak terahertz wave signals, can realize effective reading of reflected signals in a three-dimensional TOF imaging technology, and is suitable for reading signals with different light intensities. The readout circuit can be manufactured on the same CMOS chip, is simple in design principle, low in cost and easy to integrate on a large scale.
It should be understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not intended to be limited to the specific order or hierarchy.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", etc., mentioned in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes, sizes and positional relationships of the components in the drawings do not reflect the actual sizes, proportions and actual positional relationships.
In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, the disclosure may lie in less than all features of a single disclosed embodiment. Thus, the following claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the disclosure.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. To the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim. Any use of the term "or" in the specification of the claims is intended to mean a "non-exclusive or".
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A terahertz wave readout circuit, comprising:
the detector model (A) is used for simulating an input terahertz modulated photocurrent signal to obtain a first analog signal, demodulating the first analog signal and sampling to obtain a sampling signal;
the integral amplification module (B) is used for carrying out integral amplification on the sampling signal to obtain an amplified signal;
the integrated signal sampling module (C) is used for collecting a terahertz signal value of the amplified signal in an integration period to obtain a sampling integrated signal;
an analog-to-digital conversion module (D) for converting the sampled integrated signal into a digital signal;
wherein the sampling signal has a phase offset from the simulated terahertz photocurrent signal.
2. The terahertz-wave readout circuit according to claim 1, wherein the detector model (a) includes:
a first field effect transistor (M1) and an alternating current source (I)tof)；
Wherein the alternating current source (I)tof) The alternating current source (I) is connected between the drain electrode and the source electrode of the first field effect transistor (M1) in paralleltof) The terahertz modulation photocurrent signal is simulated to obtain the first analog signal, a control signal is loaded on the gate of the first field effect transistor (M1), the control signal is used for demodulating the first analog signal to obtain the sampling signal, and a direct current bias voltage (Vbias) is loaded on the source of the first field effect transistor (M1);
the frequency of the first analog signal is the same as the frequency of the control signal, and the first analog signal and the control signal have a phase offset.
3. The terahertz-wave readout circuit according to claim 2, wherein the control signal is a rectangular gate control signal, and the alternating current source (I) istof) Having a dc signal component and a continuous wave or pulsed wave ac signal component.
4. The terahertz-wave readout circuit according to claim 1, wherein the integrating-amplifying module (B) includes:
a first amplifier (A1), a reset switch (SW1) and a variable integration capacitor (Cf1) which are connected in parallel with each other;
wherein a negative input of the first amplifier (A1) is connected to an output of the detector model (A), and a positive input of the first amplifier (A1) is connected to a reference voltage (Vref);
the first amplifier (a1) and the variable integrating capacitor (Cf1) cooperate to perform integral amplification on the sampled signal.
5. The terahertz-wave readout circuit according to claim 4, wherein the first amplifier (A1) is a single-ended output folded cascode structure;
the single-ended output folded cascode structure comprises:
the differential input cascode structure, the differential output active load and the cascode current drive tube.
6. The terahertz-wave readout circuit according to claim 1, wherein the integrated-signal sampling module (C) includes:
a single slip unit (C1) and a sampling circuit unit (C2);
wherein the single slip unit (C1) is configured to convert the amplified signal into a differential signal;
the sampling circuit unit (C2) is used for acquiring a reset signal and an integrated signal of the differential signal in an integration period to obtain a sampling integrated signal;
the sampling circuit unit (C2) comprises:
a second amplifier (A2), a sampling switch (SW2) and a variable capacitor (Cf2) which are connected in parallel with each other;
wherein the second amplifier (A2) samples the differential signal in cooperation with the variable capacitance (Cf 2).
7. The terahertz-wave readout circuit according to claim 6, wherein the single-slip unit (C1) includes:
a first sampling capacitor (Cs0) and a second sampling capacitor (Cs 1);
wherein the first sampling capacitor (Cs0) is used for collecting the reset signal, the second sampling capacitor (Cs1) is used for collecting the integrated signal, and the first sampling capacitor (Cs0) and the second sampling capacitor (Cs1) are also used for carrying out charge transfer on the reset signal and the integrated signal.
8. The terahertz-wave readout circuit according to claim 6, wherein the second amplifier (A2) is a differential input-differential output two-stage operational amplifier structure;
the differential input-differential output two-stage operational amplifier structure comprises:
a first stage folded cascode amplification structure (A21), a second stage source follower amplification structure (A22) and a common mode feedback circuit (A23), the first stage folded cascode amplification structure (A21) comprising a chopper amplifier for cancelling flicker noise in the second amplifier (A2).
9. The terahertz-wave readout circuit according to claim 1, wherein the analog-to-digital conversion module (D) includes:
an integrating amplifier unit (I), a quantizer unit (J) and a feedback unit (DAC);
the integrating amplifier unit (I) is used for clearing a residual signal after digital-to-analog conversion by using a reset signal, the quantizer unit (J) is used for converting an output signal of the integrating amplifier unit (I) into a digital single-bit signal, and the feedback unit (DAC) is used for converting part of the digital single-bit signal into a second analog signal and feeding back the second analog signal to the integrating amplifier unit (I).
10. The terahertz wave readout circuit according to claim 9, wherein the analog-to-digital conversion module (D) is a third-order cascaded integrating feedback modulation structure comprising three integrating amplifier units (I), one quantizer unit (J) and two feedback units (DACs);
the quantizer unit (J) comprises a dynamic comparator and a latch, wherein the dynamic comparator is used for resetting or amplifying the differential input signal according to the relative magnitude of the bias voltage of the differential input signal and the digital power supply signal input end, and the latch is used for latching the amplified differential input signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116470889A (en) * | 2023-04-10 | 2023-07-21 | 北京大学 | Comparator circuit, analog-digital converter and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116470889A (en) * | 2023-04-10 | 2023-07-21 | 北京大学 | Comparator circuit, analog-digital converter and electronic equipment |
| CN116470889B (en) * | 2023-04-10 | 2024-04-16 | 北京大学 | Comparator circuit, analog-digital converter and electronic equipment |
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