CN113985356A

CN113985356A - Method for realizing radar signal pulse description word sorting function

Info

Publication number: CN113985356A
Application number: CN202111270053.1A
Authority: CN
Inventors: 李晃; 李继锋; 朱文明; 陈浩
Original assignee: Yangzhou Yuan Electronic Technology Co Ltd
Current assignee: Yangzhou Yuan Electronic Technology Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2022-01-28
Anticipated expiration: 2041-10-29
Also published as: CN113985356B

Abstract

The invention discloses a method for realizing a radar signal pulse description word sorting function, and belongs to the technical field of radar signal reconnaissance. The invention comprises the following steps: acquiring a Pulse Description Word (PDW) generated by a digital receiver; establishing a functional module for sorting PDW message data generated by a digital receiver in a real-time operating system; confirming task priority and data flow direction of the functional module; and acquiring a radiation source description word (EDW) obtained after sorting processing, and displaying the EDW on an upper computer as a part of a reconnaissance result of the radar signal system. The invention provides a sorting function, which can enable the whole sorting process to form a pipeline processing mode, improve the execution efficiency of the whole processing process, fully exert the processing performance of a CPU, and utilize a real-time operating system to replace a bare computer development mode for sorting, so that the number of tasks is not limited by the number of CPU cores.

Description

Method for realizing radar signal pulse description word sorting function

Technical Field

The invention relates to the technical field of radar signal reconnaissance, in particular to a method for realizing a radar signal pulse description word sorting function.

Background

In the radar signal reconnaissance system, Pulse Description Words (PDW) generated by a digital receiver are required to be sorted according to a specific sorting algorithm to obtain radiation source Description Words (EDW) which are used as a part of a reconnaissance result of the system to be displayed on an upper computer, and the processing speed of the Pulse Description Words of the radar signal is an important technical index of the radar signal reconnaissance system.

At present, a common radar signal reconnaissance system deploys a sorting function in a special information processing board card or a specific central processing unit Chip (CPU) and a Digital Signal Processing (DSP) chip, and a Software implementation scheme of the system is mostly bare computer Development directly based on a Software Development Kit (SDK) provided by a processor manufacturer.

However, the requirement of the current radar signal reconnaissance system on the signal sorting module includes a communication function with other modules besides the operation of the sorting algorithm, in addition, a more efficient development mode is to divide the sorting processing flow into a plurality of parallel tasks, the relation between a producer and a consumer is realized between the tasks through specific data structures such as FIFO buffering, message queues, a ring buffer area, a shared memory area and the like, and the whole processing flow is a multi-task parallel pipeline structure.

Although it is possible to implement multitasking by bare-die development using inter-core interrupts in a widely-used Multi-core CPU, that is, one core runs one task, the flexibility of the system is far from the multitasking development method under an operating system supporting a Symmetric Multi-Processing SMP (Symmetric Multi-Processing) architecture. In addition, the traditional SDK development mode basically does not support a task scheduling strategy of combining preemptive task scheduling based on priority and time slice rotation with the same priority, and the CPU control right of a task with a low priority can be preempted in time after the task with a high priority reaches a ready state by setting different priorities for different tasks is difficult to realize.

In addition, in the current technical means, in order to simultaneously implement multitasking and data pipeline processing and exert the advantages of a multi-core CPU, a bare computer is generally adopted to develop and execute different tasks on each core of the CPU, wherein a task on one core is a main task, and communication between tasks is realized through interruption and shared memory space between the tasks, but the number of the tasks is limited by the number of cores of the CPU, and meanwhile, the communication mode between the tasks is not flexible and diverse as the communication mode between the tasks provided by a real-time operating system, and the development difficulty is relatively high.

Disclosure of Invention

The invention aims to provide a method for realizing a radar signal pulse description word sorting function, so as to solve the problems in the background technology.

In order to solve the technical problems, the invention provides the following technical scheme: a method for realizing a radar signal pulse description word sorting function comprises the following steps:

s1, acquiring a Pulse Description Word (PDW) generated by the digital receiver;

s2, establishing a functional module for the PDW message generated by the digital receiver to carry out sorting processing;

s3, establishing task priority and data flow direction of the functional module in the real-time operating system;

and S4, acquiring the radiation source description word (EDW) obtained after sorting, and displaying the EDW on the upper computer as a part of the reconnaissance result of the radar signal system.

In step S2, the sorting processing task is deployed on one field programmable gate array, namely FPGA, and two general CPUs, all of which support RapidIO and are connected to the same RapidIO switch chip, and data transmission between FPGA and CPU is performed through RapidIO;

the two general CPUs are respectively marked as CPU _ A and CPU _ B.

According to the above technical solution, the functional module on the FPAG includes: the PDW message receiving module, the PDW message processing module, the PDW message FIFO buffer module and the PDW message sending module;

the PDW message receiving module is used for receiving a PDW message from a digital receiver; the PDW message processing module is used for filtering out information which is not needed by main sorting, shortening the message length and reducing the workload of the subsequent processing process; the PDW message FIFO buffer module is used for reading and writing PDW messages in the FIFO buffer and counting the amount of PDW messages in the current buffer; the PDW message sending module is used for sending all PDW message data cached in the current PDW message FIFO buffer module to the CPU _ A when receiving a PDW request doorbell message of the CPU _ A, and then sending the doorbell message containing the number of the sent PDW messages;

the PDW data received by the PDW message receiving module is output to a PDW message processing module; the PDW message processing module processes PDW data and then generates a PDW short message and outputs the PDW short message to the PDW message FIFO cache module; the PDW short message stored in the PDW message FIFO cache module is output to a PDW message sending module; and the data output by the PDW message sending module is output to a PDW message receiving module of the CPU _ A through the SRIO.

According to the above technical solution, the functional module on the CPU _ a includes: the device comprises a PDW message request receiving module, a PDW pre-sorting module and a PDW sending module;

the PDW message request receiving module is used for receiving PDW message data sent by the FPGA and doorbell messages containing the number of the PDW message data messages, storing the received PDW message data into a specified memory window, setting global variables of the number of the received PDW data by using a doorbell callback function, and sending semaphores SEM _1 of the received PDW message data; semaphore SEM _1 wakes up the PDW pre-sorting module blocked by the request semaphore SEM _1, so that the PDW pre-sorting module starts to operate, the PDW pre-sorting module is used for traversing the received PDW message data and counting each item of data in each PDW message data, the received abnormal PDW message data is removed in a PDW pre-sorting module according to a statistical result, and then according to FREQ and DOA of the PDW message data, wherein, the FREQ is frequency, the DOA is arrival direction, PDW message data are respectively stored in a specific TOA group and a specific DOA group, the TOA is the arrival time, each group corresponds to a memory area with the depth consistent with the FIFO cache depth in the PDW message FIFO buffer module, storing the counting variables of the number of PDWs in the memory area, updating the counting variables, and storing the subscript of the PDW for identifying the moment in the annular cache area when the counting variables reach a specific threshold value each time; the PDW sending module is used for waiting for the CPU _ B to request a group of semaphores SEM _2 of PDWs with the quantity meeting the threshold value, leaving the blocking state when the PDW sending module receives the semaphores SEM _2, entering the ready state or preempting other tasks with low priority to execute, reading PDW message subscripts meeting the threshold value from the annular cache area, sending a group of corresponding PDW messages to the CPU _ B, and sending doorbell messages containing the quantity of the PDW messages to be sent; the semaphore SEM _2 is sent by a corresponding callback function in the CPU _ A after the doorbell requesting the PDW data is sent by the CPU _ B;

the PDW message request receiving module outputs PDW data received by the SRIO to the PDW pre-sorting module; the PDW pre-sorting module processes PDW data and outputs the PDW data to a group of specific TOA and DOA; and the PDW sending module sends the PDW data in the group of the specific TOA and the DOA of which the PDW data quantity meets the processing threshold value to a PDW message receiving module of the CPU _ B through the SRIO.

When the CPU _ A receives the PDW data volume sent by the FPGA and is the maximum FIFO cache depth in the PDW message FIFO buffer module, the PDW possibly lost between the data requested next time and the data requested this time is indicated, if the lost PDW exists, the TOAs of the PDW data requested twice are not continuous any more, so that the PDW data in each group grouped according to the DOA and FREQ intervals are emptied after the CPU _ A pre-sorting module finishes processing the PDW data received this time, and the next batch of PDW data with continuous TOAs is ready to be received; and if the lost PDW does not exist, the operation is normal.

According to the technical scheme, the functional modules on the CPU _ B comprise a PDW receiving module, a PDW main sorting module, an EDW merging module and an EDW sending module;

the PDW receiving module is used for receiving a group of PDWs sent by the CPU _ A, storing the PDWs in a designated memory area, receiving doorbell messages of the CPU _ A, updating global variables by PDW data volumes in a doorbell in a corresponding doorbell callback function, and sending and receiving a group of PDW data signal volumes SEM _ 3; after receiving the semaphore SEM _3, the PDW main sorting module performs main sorting processing on PDW data, then sends doorbell information to the CPU _ A to request a next group of PDW data meeting a threshold, and the PDW main sorting module is in a blocking state before receiving the next group of PDW data; the EDW merging module is used for completing merging of EDW data, generating a corresponding EDW message and adding the message into a TCP (transmission control protocol) sending message queue of the EDW sending module, the EDW merging module sleeps for a fixed time length after executing a task each time, and the EDW merging module is ready to execute or seizes other low-priority tasks to execute after the dormancy is finished; the EDW sending module is a TCP server, and a request is initiated by an upper computer or a TCP client of other modules to establish connection; the EDW merging module adds the EDW message into a message queue, and can wake up a TCP sending task in a blocking state to enter a ready state or seize other tasks with low priority to execute;

the PDW message receiving module outputs PDW data received by the SRIO to the PDW main sorting module; the PDW main sorting module processes PDW data to generate EDW data and outputs the EDW data to the EDW storage area; the EDW merging module carries out batching processing on the EDW data in the EDW storage area to generate batched EDW data and outputs the batched EDW data to a message queue of the EDW sending module; the EDW sending module outputs the EDW data after the batch in the message queue through the TCP.

According to the technical scheme, the PDW main sorting module is mainly used for finishing the processing of a batch of PDWs with DOA and FREQ within a certain range and generating one or more EDWs, wherein the processing flow of the main sorting comprises the following steps:

s7-1, sorting the PDWs to be processed in the batch in an ascending order according to TOA, making a cumulative histogram of the sorted PDWs according to TOA, and obtaining a potential repetition period value when a value of a corresponding channel in the histogram meets a threshold value;

s7-2, retrieving PDWs in the batch of PDWs according to the TOA, wherein the PDWs meet the potential repetition frequency period in the step S7-1, and generating corresponding EDWs according to the retrieved PDWs after the number of the retrieved PDWs meets a threshold value;

s7-3, repeating the steps S7-1 and S7-2 for the remaining PDWs until the number of the remaining PDWs does not meet the minimum number for primary sorting.

The PDW main sorting module also comprises a data structure which is maintained in a CPU _ B for the PDW which is not processed by the main sorting and is similar to the data structure which is maintained in the CPU _ A and carries out grouping according to the FREQ frequency and the DOA of the PDW, and unprocessed PDW data can be gathered together with the PDW of the corresponding grouping sent in the subsequently received CPU _ A to participate in the main sorting. The PDW master sort module then sends doorbell information to CPU _ a requesting the next set of PDW data that meets the threshold and requesting the semaphore for the received PDW data to be in a blocking state before the next set of PDW data is received.

According to the technical scheme, the EDW merging module mainly completes merging processing of a batch of EDWs generated by the PDW main sorting module in a fixed processing time period, merges EDWs belonging to the same radar, and the merging processing flow comprises the following steps:

s8-1, screening out a group of EDWs with DOAs and PRIs within a tolerance range, wherein the PRIs are repetition frequency periods;

s8-2, determining the situation of heavy frequency spread according to the difference value after the TOA of the EDW is screened to carry out remainder on the PRI;

s8-3, counting PW and FREQ of the EDW obtained through screening, and determining the frequency diversity condition, wherein the PW is the pulse width;

s8-4, repeating the steps S8-1 to S8-3 for the rest of EDWs until the process of merging all EDWs is completed.

According to the above technical solution, the task priority of the functional module includes:

in the FPGA, all modules are executed in parallel;

in CPU _ a, the task priorities of three functional modules: the PDW message request receiving module is highest, the PDW sending module is next to the PDW sending module, and the PDW pre-sorting module is lowest;

in the CPU _ B, the task priorities of the four functional modules are a PDW receiving module, an EDW merging module, an EDW sending module and a PDW main sorting module from high to low in sequence;

in the FPGA, the data flow direction among the modules is as follows in sequence: the PDW message receiving module, the PDW message processing module, the PDW message FIFO cache module and the PDW message sending module;

in the CPU _ a, the data flow between the modules is, in order: the device comprises a PDW message request receiving module, a PDW pre-sorting module and a PDW sending module;

in the CPU _ B, the data flow between the modules is in order: the device comprises a PDW receiving module, a PDW main sorting module, an EDW merging module and an EDW sending module. The data flow in the CPU appears to the adjacent modules as producer and consumer relationships through shared data structures. The data structure between the PDW message request receiving module and the PDW pre-sorting module in the CPU _ A is a memory window which is maintained by the PDW message request receiving module and used for receiving the PDW message. The data structure between the PDW pre-sorting module and the PDW sending module in the CPU _ A is a data structure for storing PDW which is grouped according to different DOA and FREQ intervals. The data structure between the PDW receiving module and the PDW main sorting module in the CPU _ B is a memory window which is maintained by the PDW receiving module and used for receiving the PDW message. And the data structure between the PDW main sorting module and the EDW merging module in the CPU _ B is an EDW array generated by the PDW main sorting module. The data structure between the EDW merging module and the EDW sending module in the CPU _ B is a sending message queue of a TCP server side, and the operations of the producer task and the consumer task on the shared data structure are both located in a critical area.

Compared with the prior art, the invention has the following beneficial effects:

1. according to the invention, the sorting process is decomposed into different sub-function modules according to the characteristics of a hardware platform, and each sub-function module is interacted through a shared data structure, so that the whole sorting process forms a pipeline processing mode, the execution efficiency of the whole processing process is improved, and the processing performance of a CPU is fully exerted;

2. for a real-time operating system based on priority preemptive scheduling, the invention sets different priorities for tasks of different sub-modules divided by a sorting function, so that the tasks needing to be processed preferentially can preempt the execution of processing tasks with low priority when meeting the ready state, and the tasks can respond immediately when a PDW receiving module requires PDW data and doorbell messages to arrive;

3. the invention establishes a sorting function under a real-time operating system, replaces a bare computer development mode, and solves the problem between cores and tasks in the bare computer development, for example, in the bare computer development, each core of a CPU executes different tasks, wherein the task on one core is a main task, the tasks realize communication between the tasks through interruption and shared memory space, and the sorting function is decomposed into a plurality of sub-function modules according to the number of the cores based on the mode, and the multi-task processing can be realized when the sorting function runs on different cores, but the number of the tasks is limited by the number of the cores of the CPU;

4. the technical scheme of the invention is based on the sorting function performed under the real-time operating system, and the reliable inter-task communication between different sub-function modules is ensured by utilizing the semaphore, the annular buffer area and the message queue provided by the real-time operating system;

5. in the software implementation scheme provided by the invention, each sub-function module executes fixed operation in an internal cycle, each cycle operates small-batch data, the time for operating once is short, the transmission speed of pipeline data is high, the system throughput is increased, and the processing speed of PDW is improved;

6. in the invention, for signals that unprocessed PDW in a group of PDW data subjected to main sorting possibly belongs to a longer repetition frequency period, a data structure similar to the data structure for storing the pre-sorting result in the CPU _ A is arranged to store and sort the unprocessed PDW data, and the unprocessed PDW data is merged with other batches of PDW data to perform main sorting processing.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic diagram of task priorities and data flow directions of modules of a method for implementing a radar signal pulse description word sorting function according to the present invention;

fig. 2 is a schematic step diagram of a method for implementing a radar signal pulse description word sorting function according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-2, the present invention provides the following technical solutions: a method for realizing a radar signal pulse description word sorting function comprises the following steps:

s1, acquiring a Pulse Description Word (PDW) generated by the digital receiver;

s2, establishing a functional module for the PDW message data generated by the digital receiver to carry out sorting processing;

s3, confirming the task priority and the data flow direction of the functional module in the real-time operating system;

the two general CPUs are respectively marked as CPU _ A and CPU _ B.

The functional modules on the FPAG comprise: the PDW message receiving module, the PDW message processing module, the PDW message FIFO buffer module and the PDW message sending module;

The functional modules on the CPU _ A comprise: the device comprises a PDW message request receiving module, a PDW pre-sorting module and a PDW sending module;

In the CPU _ a, there is a case that TOAs of PDW data requested by two adjacent requests are discontinuous, so after the CPU _ a pre-sorting module finishes processing the PDW data received this time, PDW data in each group grouped according to the DOA and FREQ intervals are emptied to prepare for receiving PDW data of a next batch of TOAs continuous.

The functional modules on the CPU _ B comprise a PDW receiving module, a PDW main sorting module, an EDW merging module and an EDW sending module;

The PDW main sorting module is mainly used for finishing the processing of a batch of PDWs with DOA and FREQ within a certain range and generating one or more EDWs, wherein the processing flow of main sorting comprises the following steps:

The EDW merging module mainly completes merging processing of a batch of EDWs generated by the PDW main sorting module in a fixed processing time period, merges EDWs belonging to the same radar, and the merging processing flow comprises the following steps:

The task priority of the functional module comprises:

in the FPGA, all modules are executed in parallel;

in the CPU _ B, the data flow between the modules is in order: the device comprises a PDW receiving module, a PDW main sorting module, an EDW merging module and an EDW sending module.

In this embodiment:

the system is provided with a radar signal reconnaissance system and a digital receiver;

acquiring a Pulse Description Word (PDW) generated by a digital receiver;

sorting PDW, and deploying the sorting task on a Field Programmable Gate Array (FPGA) and two general CPUs (central processing units) which are respectively marked as CPU _ A and CPU _ B;

all the three support RapidIO and are connected to the same RapidIO switch chip, and data transmission between the FPGA and the CPU is carried out through RapidIO;

the functional modules on the FPAG include: the PDW message receiving module, the PDW message processing module, the PDW message FIFO buffer module and the PDW message sending module;

the pulse description word generated by the digital receiver is received by the PDW message receiving module, and the PDW message receiving module outputs the received PDW data to the PDW message processing module; the PDW message processing module processes the PDW message, filters out unnecessary information, shortens the message length and outputs the generated PDW short message to the PDW message FIFO cache module;

the PDW message FIFO cache module reads, writes and caches the received PDW short message, and outputs the PDW short message to the PDW message sending module; the PDW message sending module outputs the PDW message to a PDW message request receiving module of the CPU _ A through the SRIO;

in the CPU _ A, the functional modules established based on the real-time operating system comprise: the device comprises a PDW message request receiving module, a PDW pre-sorting module and a PDW sending module; each functional module has different priorities, wherein the PDW message request receiving module is highest, the PDW sending module is next to the PDW sending module, and the PDW pre-sorting module is lowest;

the PDW message request receiving module receives PDW message data sent by the FPGA and doorbell messages containing the PDW message data message quantity, stores the received PDW message data into a specified memory window, sets global variables of the received PDW quantity by using a doorbell callback function, and sends the semaphore SEM _1 of the received PDW message data;

awakening a PDW pre-sorting module blocked by a request semaphore SEM _1 through semaphore SEM _1 to enable the PDW pre-sorting module to start working, traversing the PDW message data received this time by the PDW pre-sorting module, counting various data in each PDW message data, eliminating abnormal PDW message data received this time in the PDW pre-sorting module according to a counting result, respectively storing the PDW message data into specific TOA and DOA groups according to FREQ and DOA of the PDW message data, storing a memory area with the depth consistent with the FIFO cache depth in the PDW FIFO message buffer module corresponding to each group, storing a counting variable of the number of PDWs in the memory area, updating the counting variable, and storing a subscript identifying the PDW at the moment in an annular cache area when the counting variable reaches a specific threshold;

a semaphore SEM _2 is set, and the semaphore SEM _2 is sent by a corresponding callback function in a CPU _ A after a doorbell requesting PDW data is sent by a CPU _ B; when receiving the semaphore SEM _2, the PDW sending module leaves a blocking state, enters a ready state or seizes other tasks with low priority to execute, reads a PDW message subscript meeting a threshold value from the annular cache region, sends a group of corresponding PDW messages to a CPU _ B, and sends a doorbell message containing the number of the sent PDW messages;

in the CPU _ B, the functional modules established based on the real-time operating system comprise a PDW receiving module, a PDW main sorting module, an EDW merging module and an EDW sending module; each functional module has different priorities, and the task priorities of the four functional modules are a PDW receiving module, an EDW merging module, an EDW sending module and a PDW main sorting module from high to low in sequence;

the PDW receiving module receives a group of PDWs sent by the CPU _ A, stores the PDWs in a designated memory area, receives doorbell messages of the CPU _ A, updates global variables by PDW data volume in a doorbell in a corresponding doorbell callback function, and sends and receives a group of PDW data signal volume SEM _ 3;

after receiving the semaphore SEM _3, the PDW main sorting module performs main sorting processing on PDW data, then sends doorbell information to the CPU _ A to request a next group of PDW data meeting a threshold, and the PDW data is in a blocking state before receiving the next group of PDW data;

in a PDW main sorting module, sequencing PDWs to be processed in the batch in an ascending order according to TOA, making a cumulative histogram of the sequenced PDWs according to the TOA, and obtaining a potential repetition frequency period value when a value of a corresponding channel in the histogram meets a threshold value; retrieving PDWs which meet the potential repetition frequency period in the batch of PDWs according to the TOA, and generating corresponding EDWs according to the retrieved PDWs after the number of the retrieved PDWs meets a threshold value;

the EDW merging module is used for completing merging of EDW data, generating a corresponding EDW message and adding the message to a TCP (transmission control protocol) message sending queue of the EDW sending module;

screening out a group of EDWs with DOA and PRI within a tolerance range in an EDW merging module, wherein the PRI is a repetition frequency period; determining the condition of the repetition frequency spread according to the difference value after the TOA of the EDW is screened and the PRI is subjected to residue taking; counting PW and FREQ of the screened EDW to determine the frequency diversity condition, wherein the PW is the pulse width; repeating the steps on the rest EDWs until all the EDWs are combined and processed;

the EDW sending module is a TCP server;

the EDW merging module carries out batching processing on the EDW data in the EDW storage area to generate EDW data after batching, and the EDW data is output to a message queue of the EDW sending module; and the EDW sending module outputs the EDW data after the completion of the batch in the message queue through the TCP and displays the EDW data on the upper computer as a part of the reconnaissance result of the radar signal system.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for realizing a radar signal pulse description word sorting function is characterized by comprising the following steps: the method comprises the following steps:

s1, acquiring a Pulse Description Word (PDW) generated by the digital receiver;

2. The method for implementing the radar signal pulse description word sorting function according to claim 1, wherein: in step S2, the sorting processing task is deployed on one field programmable gate array, namely FPGA, and two general CPUs, all of which support RapidIO and are connected to the same RapidIO switch chip, and data transmission between FPGA and CPU is performed through RapidIO;

the two general CPUs are respectively marked as CPU _ A and CPU _ B.

3. The method for implementing the radar signal pulse description word sorting function according to claim 2, wherein: the functional modules on the FPAG comprise: the PDW message receiving module, the PDW message processing module, the PDW message FIFO buffer module and the PDW message sending module;

4. The method for implementing the radar signal pulse description word sorting function according to claim 3, wherein: the functional modules on the CPU _ A comprise: the device comprises a PDW message request receiving module, a PDW pre-sorting module and a PDW sending module;

5. The method for implementing the radar signal pulse description word sorting function according to claim 4, wherein: when the CPU _ A receives the PDW data volume sent by the FPGA and is the maximum FIFO cache depth in the PDW message FIFO buffer module, the PDW possibly lost between the data requested next time and the data requested this time is indicated, if the lost PDW exists, the TOAs of the PDW data requested twice are not continuous any more, so that the PDW data in each group grouped according to the DOA and FREQ intervals are emptied after the CPU _ A pre-sorting module finishes processing the PDW data received this time, and the next batch of PDW data with continuous TOAs is ready to be received; and if the lost PDW does not exist, the operation is normal.

6. The method for implementing the radar signal pulse description word sorting function according to claim 4, wherein: the functional modules on the CPU _ B comprise a PDW receiving module, a PDW main sorting module, an EDW merging module and an EDW sending module;

7. The method for implementing the radar signal pulse description word sorting function according to claim 6, wherein: the PDW main sorting module is mainly used for finishing the processing of a batch of PDWs with DOA and FREQ within a certain range and generating one or more EDWs, wherein the processing flow of main sorting comprises the following steps:

8. The method for implementing the radar signal pulse description word sorting function according to claim 7, wherein: the EDW merging module mainly completes merging processing of a batch of EDWs generated by the PDW main sorting module in a fixed processing time period, merges EDWs belonging to the same radar, and the merging processing flow comprises the following steps:

9. The method for implementing the radar signal pulse description word sorting function according to claim 1, wherein: the task priority and data flow of the functional module comprise:

in the FPGA, all modules are executed in parallel;