CN113971974A - Low-power-consumption large-capacity CAM circuit structure - Google Patents

Abstract

The invention provides a low-power-consumption large-capacity CAM circuit structure, which is characterized in that the circuit structure of the existing CAM is changed, the working process of the large-capacity CAM is divided into a plurality of pipeline stages, the pipeline stages are sequentially searched, addressed and latched in a partitioning mode, and finally all addressing results are uniformly encoded to generate result addresses and output the result addresses, so that the transient large power consumption of the CAM is distributed in the plurality of pipeline stages, and the requirement on the transient high current of a chip power supply network is reduced. The invention has important application value in large-scale low-power consumption SoC using CAM IP.

Description

Low-power-consumption large-capacity CAM circuit structure

Technical Field

The invention relates to the field of microelectronic technology and memories, in particular to a low-power-consumption large-capacity CAM circuit structure.

Background

The CAM circuit is used as a content-addressable memory, has higher search efficiency and inevitably higher power consumption, particularly has a prominent problem of transient power consumption for the CAM circuit with larger capacity, and may bring serious influence on the power integrity of an IP (Internet protocol) or the whole SoC (System on chip). In the existing CAM design technology, in order to improve the access speed of the circuit, three processes of data search, match result generation and match address encoding are generally put in the same clock cycle, and the match query operation is performed on the whole memory array.

A CAM is a branch of RAM that enables lookup operations in addition to the read and write functions of RAM. One of the main functions of the RAM is to read data, that is, to input address information to obtain data stored in the RAM; the main function of CAM is to search data, i.e. inputting the search data can obtain the matching address and the matching signal, and the function is shown in fig. 1.

The CAM mainly comprises the following five parts: CAM memory cells M, sense amplifiers SA, search line SL drivers, address decoders and priority encoders. The simplified structure is shown in a block diagram in FIG. 2, and the structure of the CAM array is shown in FIG. 5. Where the CAM memory cells are the core of the CAM, each row of which constitutes a word, and each cell that constitutes a word is called a bit. The device is mainly responsible for storing and comparing data, the comparison result is represented by the voltage change of a matched line ML and then is amplified by SA, and finally, the priority encoder outputs the highest priority matching result. In addition, the SL driver is used for loading search data to the SL, and the address decoder is used for address decoding in read-write operation.

The CAM is classified into a NOR type CAM and a NAND type CAM according to the connection manner of memory cells, and typical transistor-level circuit diagrams thereof are shown in fig. 3 and 4. NOR-type CAMs are mounted in parallel on one ML and behave as logical or operations, whereas NAND-type CAMs behave as logical and operations by connecting a plurality of MLs in series.

As shown in fig. 3, the NOR-type CAM cell implements a comparison operation of stored data (D, D #) and search data (SL, SL #) using four pipes M1 to M4, wherein "#" represents "not". M1-M4 implement the XNOR operation through dynamic logic circuits, as described in detail below. When SL and D are equal or match, M1, M4 or M2, M3 are turned off, ML remains high at the time of precharge; when SL does not match D, M1, M3 or M2, M4 turn on and ML discharges to ground. For a word, ML is high only if each stored bit matches the corresponding search bit, i.e. the entire word matches, called full match; otherwise, ML is pulled low, called word mismatch.

As shown in FIG. 4, the NAND type CAM cell adopts three tubes M1-M3 to realize the comparison operation of stored data and search data, when SL is matched with D, M2 or M3 is conducted, the level of a point B is pulled high by SL, and then M1 tube is opened, and ML continues to propagate to a lower level cell; otherwise, the B point level is pulled low by SL, the M1 tube is turned off, and MLn +1 is left floating. Therefore, all the NAND-type CAM cells in one word are connected in series by a plurality of MLs, and the NAND operation of the MLs is realized.

The NOR CAM has no transistors connected in series on the match line, and has no voltage drop caused by the transistors, so that a longer match line can be supported, and thus a larger memory capacity and a higher speed can be obtained. NAND-type CAMs, in which each memory cell is connected in series with a transistor on the match line, result in the match line not being too long, the capacity not being too large and the series discharge speed being slow, have the advantage that if one transistor on the match line is not conducting, the entire match line is no longer discharged, and thus have the advantage of lower transient power consumption. To sum up, in order to support large-capacity CAM, NOR-type CAM architecture is generally adopted.

Disclosure of Invention

Aiming at the problem that instantaneous power consumption is larger when a Content Addressable Memory (CAM) is used for high-speed searching in the prior art, the invention provides a low-power-consumption large-capacity CAM circuit structure.

The invention is realized by the following technical scheme:

a low-power-consumption large-capacity CAM circuit structure comprises a CAM array, a search driving module, a time sequence control module, an encoder and a plurality of latches; the CAM array comprises a plurality of parallel storage blocks; a matched line ML is arranged in each memory block; the input end of the search driving module is connected with the output end of the data query module, and the output end of the search driving module is correspondingly connected to the storage blocks through the search lines SL; the method comprises the steps that query data are correspondingly transmitted to a plurality of storage blocks through a plurality of search lines SL for matching comparison, matching results are correspondingly transmitted to latches through matching lines ML of the storage blocks, a time sequence control module is respectively and correspondingly provided with time sequence switches Sel on the matching lines ML of the storage blocks according to address ranges corresponding to the storage blocks, the time sequence switches Sel are sequentially turned on in each clock cycle, the matching lines ML of the storage blocks are respectively queried, matching results correspondingly completed on the matching lines ML are transmitted to the corresponding latches for latching for standby in each clock cycle, the output end of each latch is connected to an encoder, and after all the storage blocks are queried, the encoder uniformly encodes the results in the latches and then generates corresponding matching addresses for output in the next clock cycle.

Preferably, the CAM array divides the plurality of memory blocks according to an address sequence, the timing control module performs an inquiry operation on one of the memory blocks in each clock cycle according to the clock sequence, and generates a selection signal on the timing switch Sel according to the block address to realize the switching control of the timing switch Sel by the timing control module.

Preferably, the match lines ML in the memory blocks include a plurality of match lines, the query data is input to the corresponding memory blocks through the search lines SL for matching, and the match results are transmitted through the plurality of match lines ML in the memory blocks.

Preferably, in each clock cycle, the search driving module transmits the data on the search line SL to a corresponding one of the memory blocks for matching comparison.

Preferably, when query data is correspondingly transmitted to the match lines ML of the memory blocks through the search lines SL for match comparison, when one or more bits of data in all bits of the query data are inconsistent with the data in the memory blocks, the match lines ML in the memory blocks output a low level; when all the bits in the query data match all the data in the memory block, the match line ML in the memory block outputs a high level.

Preferably, the matching result transmitted by the match line ML is latched in a partition manner, the matching result after being queried is latched in the corresponding latch for standby in a clock cycle, and after all the memory blocks in the CAM array structure are queried, the latched matching result is uniformly encoded in the encoder in a subsequent clock cycle to generate the matching address.

Preferably, a memory block in the CAM array structure is queried in each clock cycle, and the matching result of the memory block is transmitted to a latch through the match line ML for latching.

Preferably, the timing control module performs timing control on each memory block in the CAM array structure through the pipeline control circuit.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention provides a low-power-consumption large-capacity CAM circuit structure, which is characterized in that the circuit structure of the existing CAM is changed, the working process of the large-capacity CAM is divided into a plurality of pipeline stages, the pipeline stages are sequentially searched, addressed and latched in a partitioning mode, and finally all addressing results are uniformly encoded to generate result addresses and output the result addresses, so that the transient large power consumption of the CAM is distributed in the plurality of pipeline stages, and the requirement on the transient high current of a chip power supply network is reduced. The invention has important application value in large-scale low-power consumption SoC using CAM IP.

Furthermore, the CAM array is divided into a plurality of storage blocks according to the address sequence, and the transient high power consumption in the CAM query operation process is balanced in the storage blocks in each clock period, so that the transient power consumption of the CAM is effectively reduced, and the effect of reducing the load of a circuit power supply network is achieved.

Furthermore, the query data on the search line SL is distributed to a corresponding one of the memory blocks in each clock cycle, and the other memory blocks do not work, so that only one memory block in the CAM array works in each clock cycle, and the transient current is effectively reduced.

Furthermore, after the last memory block is queried, all matching results are coded in the next clock cycle, so that the matching address result of the whole memory is generated, the integral matching address result is ensured, and the instantaneous high-current requirement on a chip power supply network is effectively reduced.

Furthermore, the transient power consumption of the large-capacity CAM memory is reduced by adopting a pipeline hierarchical working mode.

Drawings

FIG. 1 is a diagram illustrating a function comparison between a RAM and a CAM in the prior art;

FIG. 2 is a block diagram of a simplified CAM structure of the prior art;

FIG. 3 is a prior art circuit diagram of a typical NOR type CAM cell transistor level;

FIG. 4 is a prior art transistor level circuit diagram of a typical NAND type CAM cell;

FIG. 5 is a prior art CAM array structure;

FIG. 6 is a schematic diagram of a low power consumption large capacity CAM circuit according to the present invention;

FIG. 7 is a CAM bank array structure according to the present invention;

FIG. 8 is a flow chart of CAM partitioning pipeline operation according to the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The invention is described in further detail below with reference to the accompanying drawings:

in one embodiment of the invention, a low-power-consumption large-capacity CAM circuit structure is provided, and the transient large power consumption of the CAM is distributed in a plurality of pipeline stages through a circuit structure for performing pipeline searching according to address partitions, so that the transient high-current requirement on a chip power supply network is reduced.

Specifically, the low-power-consumption large-capacity CAM circuit structure, as shown in fig. 6, includes a CAM array, a search driving module, a timing control module, an encoder, and a plurality of latches; the CAM array comprises a plurality of parallel storage blocks; each memory block is provided with a match line ML, as shown in fig. 7; the input end of the search driving module is connected with the output end of the data query module, and the output end of the search driving module is correspondingly connected to the storage blocks through the search lines SL; the method comprises the steps that query data are correspondingly transmitted to a plurality of storage blocks through a plurality of search lines SL for matching comparison, matching results are transmitted to latches through matching lines ML of the storage blocks, a time sequence control module is respectively and correspondingly provided with time sequence switches Sel on the matching lines ML of the storage blocks according to address ranges corresponding to the storage blocks, the time sequence switches Sel are sequentially turned on in each clock cycle, the matching lines ML of the storage blocks are respectively queried, matching results correspondingly completed on the matching lines ML are transmitted to corresponding latches for latching for standby in each clock cycle, the output end of each latch is connected to an encoder, and after all the storage blocks are queried, the encoder uniformly encodes the results in the latches and then generates corresponding matching addresses to output in the next clock cycle.

Specifically, the CAM array divides a plurality of memory blocks according to an address sequence, the timing control module performs query operation on one of the memory blocks in each clock period according to the clock sequence, and generates a selection signal on the timing switch Sel according to the block address, so that the timing control module controls the timing switch Sel to be switched on and off.

Specifically, the match lines ML in the memory blocks include a plurality of match lines, the query data is input to the corresponding memory blocks through the search lines SL for matching comparison, and the match results are transmitted through the plurality of match lines ML in the memory blocks.

Specifically, in each clock cycle, the search driving module transmits data on the search line SL to a corresponding one of the memory blocks for matching and comparison.

Specifically, when query data is correspondingly transmitted to match lines ML of a plurality of memory blocks through a plurality of search lines SL for matching comparison, when one or more bits of data in all bits of the query data are inconsistent with the data in the memory blocks, the match lines ML in the memory blocks output a low level; when all the bits in the query data match all the data in the memory block, the match line ML in the memory block outputs a high level.

Specifically, the matching result transmitted by the match line ML is latched in a partition manner, the matching result after being queried is latched in the corresponding latch for standby in a clock cycle, and after all the memory blocks in the CAM array structure are queried, the latched matching result is uniformly encoded in an encoder in a subsequent clock cycle to generate a matching address.

Specifically, one memory block in the CAM array structure is queried in each clock cycle, and the matching result of the memory block is transmitted to a latch through the match line ML for latching.

Specifically, the timing control module implements timing control on each memory block in the CAM array structure through the pipeline control circuit, as shown in fig. 8.

In the invention, the CAM matrix result is a conventional CAM with a data bit width of m and an address depth of n, when matching query is carried out, data is input from m search lines SL and is compared with data of all units in the array, and n match lines reflect matching results, namely when 1 bit or more of all m bits of input data are inconsistent with the data stored in the row, the match line ML of the row outputs low level, otherwise, if all m bits are matched, the match line ML outputs high level.

Examples

Referring to fig. 6, when performing an inquiry operation on an m-bit inquiry data in the CAM, the inquiry data is sent to the search driving module of the CAM circuit, and the inquiry data is sent to the CAM array through m search lines SL _1.. search line SL _ m; at the moment, the time sequence control module sequentially turns on the time sequence switch Sel _1 to the time sequence switch Sel _ x in each clock cycle according to the clock sequence, respectively carries out query operation on a plurality of storage blocks of the CAM array, and sends matching results on the correspondingly finished match lines MLx _1-MLx _ n to the corresponding latches x for latching in each clock cycle; after the query operation of all the storage block arrays is completed, in the next clock cycle, all the results of the latches 1-x are uniformly encoded through the encoder to generate corresponding matched address output, so that the whole query operation is completed.

In the process, as the storage array of the large-capacity CAM is divided into a plurality of storage blocks, the transient large power consumption in the CAM inquiry operation process is balanced in the storage blocks in each clock period, the transient power consumption of the CAM is effectively reduced, and the effect of reducing the load of a circuit power supply network is achieved.

In summary, the invention provides a low-power-consumption large-capacity CAM circuit structure, which changes the circuit structure of the existing CAM, divides the working process of the large-capacity CAM into a plurality of pipeline stages, sequentially searches for addresses and latches in a partitioning mode, and finally uniformly encodes all addressing results to generate result addresses and output the result addresses, so that the transient large power consumption of the CAM is distributed in the plurality of pipeline stages, and the requirement on the transient high current of a chip power supply network is reduced. The invention has important application value in large-scale low-power consumption SoC using CAM IP.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.

Claims (8)

1. A low-power-consumption large-capacity CAM circuit structure is characterized by comprising a CAM array, a search driving module, a time sequence control module, an encoder and a plurality of latches; the CAM array comprises a plurality of parallel storage blocks; a matched line ML is arranged in each memory block; the input end of the search driving module is connected with the output end of the data query module, and the output end of the search driving module is correspondingly connected to the storage blocks through the search lines SL; the method comprises the steps that query data are correspondingly transmitted to a plurality of storage blocks through a plurality of search lines SL for matching comparison, matching results are correspondingly transmitted to latches through matching lines ML of the storage blocks, a time sequence control module is respectively and correspondingly provided with time sequence switches Sel on the matching lines ML of the storage blocks according to address ranges corresponding to the storage blocks, the time sequence switches Sel are sequentially turned on in each clock cycle, the matching lines ML of the storage blocks are respectively queried, matching results correspondingly completed on the matching lines ML are transmitted to the corresponding latches for latching for standby in each clock cycle, the output end of each latch is connected to an encoder, and after all the storage blocks are queried, the encoder uniformly encodes the results in the latches and then generates corresponding matching addresses for output in the next clock cycle.

2. The CAM circuit structure of claim 1, wherein the CAM array is configured to divide the plurality of blocks according to an address sequence, the timing control module performs a lookup operation on one of the blocks in each clock cycle according to the clock sequence, and the block address generates a selection signal on the timing switch Sel to control the timing switch Sel.

3. A low-power-consumption large-capacity CAM circuit structure according to claim 1, wherein the match lines ML in the memory blocks include a plurality of lines, the query data is input to the corresponding memory block through the search line SL for match comparison, and the match results are transmitted through the plurality of match lines ML in the memory block.

4. A low-power-consumption large-capacity CAM circuit structure according to claim 1, wherein the search driving module transmits data on the search line SL to a corresponding one of the memory blocks for match comparison in each clock cycle.

5. The CAM circuit structure of claim 1, wherein when the query data is transmitted to the match lines ML of the memory blocks via the search lines SL for match comparison, the match lines ML of the memory blocks output a low level when one or more of all the bits of the query data are inconsistent with the data in the memory blocks; when all the bits in the query data match all the data in the memory block, the match line ML in the memory block outputs a high level.

6. The CAM circuit structure of claim 1, wherein the match results transmitted by the match lines ML are latched in different areas, the match results after being queried are latched in corresponding latches for standby in a clock cycle, and after all the memory blocks in the CAM array structure are queried, the latched match results are uniformly encoded in an encoder in a subsequent clock cycle to generate the match addresses.

7. A low-power-consumption large-capacity CAM circuit structure, according to claim 1, characterized in that, in each clock cycle, a memory block in the CAM array structure is queried, and the matching result of the memory block is transmitted to the latch through the match line ML for latching.

8. The CAM structure of claim 1, wherein the timing control module is configured to control timing of each memory block in the CAM array structure via a pipeline control circuit.

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