CN113971157A - Code sharing method and device for multi-core SOC, multi-core SOC and medium - Google Patents
Code sharing method and device for multi-core SOC, multi-core SOC and medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a code sharing method and device of a multi-core SOC, a multi-core SOC and a medium. The method comprises the following steps: acquiring uniform code class information corresponding to the multi-core SOC and data class information corresponding to each kernel in the multi-core SOC; linking the uniform code information to a first logic address, and respectively linking each data information to a second logic address; storing the uniform code information in a uniform storage space, and storing the data information in independent storage spaces corresponding to the kernels respectively; and respectively allocating the physical addresses of the unified storage space and each independent storage space to the matched kernels. The scheme of the embodiment of the invention solves the problems that the sharing of the codes and the data of the multi-core SOC cannot be realized and the expenditure of the memory space is increased in the prior art, realizes the sharing of the codes and the data of the multi-core SOC and reduces the expenditure of the memory space.
Description
Technical Field
The embodiment of the invention relates to the technical field of embedded development, in particular to a code sharing method and device of a multi-core SOC, the multi-core SOC and a medium.
Background
With the continuous development of the field of embedded development, multi-core SOC (System on Chip) is widely used.
Currently, on a multi-core SOC, an independent instruction bank (code bank) and data bank are generally provided for each core, so as to avoid conflicts due to data sharing.
However, for a symmetric multi-core architecture (homogeneous or heterogeneous) having related instruction sets and not belonging to the same cluster, since the consistency of data cannot be guaranteed and each core needs to operate independently, the method cannot realize the sharing of codes and data, and increases the overhead of memory space.
Disclosure of Invention
The embodiment of the invention provides a code sharing method and device of a multi-core SOC, the multi-core SOC and a medium, so that the code and data of the multi-core SOC are shared, and the expenditure of a memory space is reduced.
In a first aspect, an embodiment of the present invention provides a code sharing method for a multi-core SOC, including:
acquiring uniform code class information corresponding to the multi-core SOC and data class information corresponding to each core in the multi-core SOC;
linking the uniform code class information to a first logic address, and linking each data class information to a second logic address respectively;
storing the uniform code information in a uniform storage space, and storing the data information in independent storage spaces corresponding to the cores respectively;
and respectively allocating the physical addresses of the unified storage space and each independent storage space to the matched kernels.
In a second aspect, an embodiment of the present invention further provides a code sharing apparatus for a multi-core SOC, including:
the information acquisition module is used for acquiring uniform code class information corresponding to the multi-core SOC and data class information corresponding to each core in the multi-core SOC;
the information linking module is used for linking the uniform code information to a first logic address and linking each data information to a second logic address respectively;
the information storage module is used for storing the uniform code information into a uniform storage space and storing the data information into independent storage spaces respectively corresponding to the kernels;
and the address allocation module is used for allocating the physical addresses of the unified storage space and each independent storage space to the matched kernel respectively.
In a third aspect, an embodiment of the present invention further provides a multi-core SOC, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the code sharing method of the multi-core SOC according to any embodiment of the present invention.
In a fourth aspect, the embodiments of the present invention further provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are used to perform the code sharing method of the multi-core SOC according to any one of the embodiments of the present invention.
The embodiment of the invention obtains the uniform code information corresponding to the multi-core SOC and the data information corresponding to each kernel in the multi-core SOC; linking the uniform code information to a first logic address, and linking each data information to a second logic address respectively; storing the uniform code information in a uniform storage space, and storing the data information in independent storage spaces corresponding to the kernels respectively; the physical addresses of the unified storage space and each independent storage space are respectively allocated to the matched kernels, so that the problems that the code and data of the multi-core SOC cannot be shared and the expenditure of the memory space is increased in the prior art are solved, the code and data of the multi-core SOC are shared, and the expenditure of the memory space is reduced.
Drawings
FIG. 1 is a flowchart of a code sharing method for a multi-core SOC according to a first embodiment of the present invention;
FIG. 2 is a flowchart of a code sharing method for a multi-core SOC according to a second embodiment of the present invention;
FIG. 3 is a flowchart of a code sharing method for a multi-core SOC according to a third embodiment of the present invention;
FIG. 4 is a flowchart of a code sharing method for a multi-core SOC according to a fourth embodiment of the present invention;
FIG. 5 is a diagram illustrating code sharing of a multi-core SOC according to a fourth embodiment of the present invention;
fig. 6 is a schematic structural diagram of a code sharing apparatus of a multi-core SOC according to a fifth embodiment of the present invention;
fig. 7 is a schematic structural diagram of a multi-core SOC in the sixth embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad invention. It should be further noted that, for convenience of description, only some structures related to the embodiments of the present invention are shown in the drawings, not all of the structures are shown.
Example one
Fig. 1 is a flowchart of a code sharing method for a multi-core SOC according to a first embodiment of the present invention, where the present embodiment is applicable to a case of code sharing for a multi-core SOC, and the method may be executed by a code sharing apparatus for a multi-core SOC, where the apparatus may be implemented by software and/or hardware and integrated in a multi-core SOC chip. Specifically, referring to fig. 1, the method specifically includes the following steps:
The SOC is a chip of an integrated circuit, and can effectively reduce the development cost of electronic information system products. From a narrow sense, the SOC is the chip integration of the core of the information system, and is the integration of the key components of the system on one chip; in a broad sense, the SOC is a micro-miniature system, and if the CPU (Central Processing Unit) is the brain, the SOC is a system including the brain, the heart, the eyes, and the hands. The academic circles at home and abroad generally tend to define the SOC as a system in which a microprocessor, an analog IP (Internet Protocol) core, a digital IP core and a memory (or off-chip memory control interface) are integrated on a single chip, and the SOC is usually customized by a customer or is a standard product oriented to a specific application. The multi-core SOC according to the embodiment of the present invention may include a plurality of cores, for example, 4, 8, or 16 cores, which is not limited in this embodiment.
In a specific implementation, on a multi-core SOC platform, more and more cores having the same instruction set and being independent of each other have the same basic tasks, and especially, the platform code portions may run the identical basic codes.
The advantage of this arrangement is that it provides a basis for implementing the sharing of code and data for a multi-core SOC.
It can be understood that, in the multi-core SOC, the data class information corresponding to each core, that is, the different portion in the executable code of each core, may include RW-data (initialized readable and writable variable) or ZI-data (Zero Write data, un-initialized readable and writable variable), which is not limited in the embodiment of the present invention.
In an optional implementation manner of the embodiment of the present invention, after obtaining the uniform code class information corresponding to the multi-core SOC and the data class information corresponding to each core in the multi-core SOC, the uniform code class information may be linked to the first logic address, and each data class information may be linked to the second logic address.
It should be noted that the first logical address and the second logical address related in the embodiment of the present invention may be any one logical address, and the embodiment of the present invention is not limited thereto. For example, the logical address range may be 0x0000000 to 0x 4000000.
It should be noted that, the references to the first logical address and the "first" and "second" in the second logical address in the embodiments of the present invention are only for indicating that the uniform code class information and the data class information are linked to different logical addresses, and are not limiting to the embodiments of the present invention.
The unified storage space and the independent storage space are respectively located in the memory.
In an optional implementation manner of the embodiment of the present invention, after the obtained code class information is connected to the first logical address and the data class information is connected to the second logical address, the unified code class information may be further stored in the unified storage space, and the data class information are stored in the storage spaces respectively corresponding to the cores.
For example, in the embodiment of the present invention, after the obtained code class information is connected to the first logical address and each piece of data class information is connected to the second logical address, the unified code class information may be stored in the first storage space of the memory, and the data class information may be stored in the second storage space, the third storage space, …, the nth storage space, and the like, which correspond to each kernel, respectively, where N is any positive integer greater than four. It should be noted that the terms "first", "second", …, and "N" are only used to distinguish the storage spaces, and are not limited to the embodiment of the present invention.
It should be noted that, if the multi-core SOC according to the embodiment of the present invention includes 4 cores, the data class information corresponding to the 4 cores may be stored in the independent storage spaces corresponding to the 4 cores, respectively; if the multi-core SOC according to the embodiment of the present invention includes 32 cores, the data class information corresponding to each of the 32 cores may be stored in the independent storage space corresponding to each of the 32 cores.
And step 140, respectively allocating the physical addresses of the unified storage space and each independent storage space to the matched kernel.
In an optional implementation manner of the embodiment of the present invention, after the unified code class information is stored in the unified storage space, and the data type information is stored in the independent storage spaces corresponding to the cores, the physical addresses of the unified storage space and the independent storage spaces may be further allocated to the matched cores.
For example, a physical address a of the unified memory space and a physical address B of the first independent memory space may be allocated to a first core of the multi-core SOC; allocating a physical address A of the unified storage space and a physical address C of a second independent storage space to a second core of the multi-core SOC; the physical address a of the unified memory space and the physical address D of the third independent memory space are allocated to the third core of the multi-core SOC, and so on, which are not limited in the embodiment of the present invention.
In the scheme of this embodiment, uniform code class information corresponding to the multi-core SOC and data class information corresponding to each core in the multi-core SOC are obtained; linking the uniform code information to a first logic address, and respectively linking each data information to a second logic address; storing the uniform code information into a uniform storage space, and respectively storing the uniform code information and the data information into independent storage spaces respectively corresponding to each kernel; the physical addresses of the unified storage space and each independent storage space are respectively allocated to the matched kernels, so that the problems that the code and data of the multi-core SOC cannot be shared and the expenditure of the memory space is increased in the prior art are solved, the code and data of the multi-core SOC are shared, and the expenditure of the memory space is reduced.
Example two
Fig. 2 is a flowchart of a code sharing method for a multi-core SOC in a second embodiment of the present invention, where this embodiment is a further refinement of the foregoing technical solutions, and the technical solutions in this embodiment may be combined with various alternatives in one or more of the foregoing embodiments. As shown in fig. 2, the code sharing method of the multi-core SOC may include the steps of:
In an optional implementation manner of the embodiment of the present invention, at the compiling stage of the kernel code, the executable instructions corresponding to each kernel in the multi-kernel SOC may be decomposed into code information and data information, respectively; the code information comprises RO-data, and the data information comprises RW-data and ZI-data.
For example, if the multi-core SOC includes 4 cores, the executable codes corresponding to the 4 cores may be decomposed into code class information and data class information at the compiling stage of the core code.
In an optional implementation manner of the embodiment of the present invention, at the compiling stage of the kernel code, after the executable instructions corresponding to each kernel in the multi-kernel SOC are respectively decomposed into the code class information and the data class information, if it is determined that the code class information of each kernel is the same, the code class information of any kernel may be obtained as the uniform code class information.
For example, if the multi-core SOC includes 4 cores, in the compiling stage of the core code, after the executable codes corresponding to the 4 cores are respectively decomposed into code class information and data class information, if it is determined that the code class information of the 4 cores are the same, the code class information of any one of the 4 cores may be acquired as uniform code class information.
and step 250, respectively allocating the physical addresses of the uniform storage space and each independent storage space to the matched kernel.
In the scheme of this embodiment, in response to a compiling instruction of a kernel code, an executable instruction corresponding to each kernel in the multi-kernel SOC is decomposed into code class information and data class information, respectively; if the code information of each kernel is the same, any code information is acquired as uniform code information, the uniform code information can be quickly acquired, and a basis is provided for realizing the sharing of codes and data in the multi-core SOC.
EXAMPLE III
Fig. 3 is a flowchart of a code sharing method for a multi-core SOC in a third embodiment of the present invention, where this embodiment is a further refinement of the foregoing technical solutions, and the technical solution in this embodiment may be combined with various alternatives in one or more of the foregoing embodiments. As shown in fig. 3, the code sharing method of the multi-core SOC may include the steps of:
and step 320, if the code class information of each kernel is the same, acquiring any code class information as uniform code class information.
and 350, respectively allocating the physical addresses of the unified storage space and each independent storage space to the matched kernel.
The target core may be any one or more cores in the multi-core SOC, which is not limited in the embodiment of the present invention.
In an optional implementation manner of the embodiment of the present invention, after the physical addresses of the unified storage space and each independent storage space are respectively allocated to the matched cores, when a start instruction of a target core in the multi-core SOC is received, the independent storage space corresponding to the target core may be mapped to the second logical address, and the unified storage space may be mapped to the first logical address.
For example, if the target core is any core of the multi-core SOC, when receiving a start instruction of the target core, the independent memory space corresponding to the target core may be mapped to the second logic address, and the unified memory space may be mapped to the first logic address; if the target kernel is any two kernels of the multi-kernel SOC, when receiving the start instruction of the target kernel, the target kernel may map two independent memory spaces corresponding to the target kernel to the second logic address, and map the unified memory space to the first logic address.
In an optional implementation manner of the embodiment of the present invention, mapping the independent storage space corresponding to the target kernel to the second logical address may include: the independent Memory space corresponding to the target kernel is mapped to the second logical address by an MMU (Memory Management Unit).
In the scheme of this embodiment, after allocating the physical addresses of the unified storage space and each independent storage space to the matched kernels, the method may further include: in response to a starting instruction of a target kernel in the multi-core SOC, mapping an independent storage space corresponding to the target kernel to a second logic address; and mapping the unified storage space to the first logic address, so that the starting of each kernel of the multi-core SOC is not influenced on the basis of realizing the sharing of codes and data in the multi-core SOC.
Example four
Fig. 4 is a flowchart of a code sharing method for a multi-core SOC in a fourth embodiment of the present invention, where this embodiment is a further refinement of the foregoing technical solutions, and the technical solutions in this embodiment may be combined with various alternatives in one or more of the foregoing embodiments. As shown in fig. 4, the code sharing method of the multi-core SOC may include the steps of:
and step 420, if the code class information of each kernel is the same, acquiring any code class information as uniform code class information.
and 450, respectively allocating the physical addresses of the unified storage space and each independent storage space to the matched kernel.
In an optional implementation manner of the embodiment of the present invention, the independent storage space corresponding to the target kernel is mapped to the second logical address; after the unified storage space is mapped to the first logic address, namely after the target kernel is started, the unified code class information corresponding to the target kernel can also be determined through the first logic address; and determining the data class information corresponding to the target kernel through the second logical address.
According to the scheme of the embodiment, after a target kernel in the multi-core SOC is started, unified code class information corresponding to the target kernel can be determined through a first logic address; the data type information corresponding to the target kernel is determined through the second logic address, so that the unified code type information and the data type information corresponding to the target kernel can be determined under the condition of the known logic address, and a basis is provided for normal operation of the multi-core SOC.
In order to make those skilled in the art better understand the code sharing method of the multi-core SOC of the present embodiment, a specific example is used below for description, and the specific process includes:
1. code (containing ro-data), RW and ZI data are separated in a compiling and linking stage and linked to a specified logical address (the segment address is aligned according to a page table);
2. a DDR (Double Data Rate) runtime space (physical address) is planned for each core: the system comprises a code area, a RW area and a ZI data area, wherein multiple cores in the code area share one part of data, and each core in the RW/ZI area is independently designed.
3. Each core maps the physical addresses of the RW and ZI data areas to the logical addresses of the RW and ZI data areas through the MMU at startup.
4. Each core parses and moves RW and ZI data to logical addresses according to the elf format, where the logical addresses are the same, but the physical addresses are different.
5. Each core operates independently, and when RW/ZI data are accessed through the same logical address, different physical addresses are accessed, so that code sharing and data separation are achieved.
Fig. 5 shows a schematic diagram of code sharing of the multi-core SOC. FIG. 5 includes 3 cores, core 1(510), core 2(520), and core 3 (530); 540 is the physical address, 541 is the Unicode class information of these 3 kernels; 542 is data information of the kernel 1; 543 is data information of kernel 2; 544 is data information of the core 3; 550 is a logical address, 551 is a first logical address, and 552 is a second logical address.
The embodiment adopts a mode of separating instructions and data, and realizes code sharing and data separation by combining MMU address mapping.
EXAMPLE five
Fig. 6 is a schematic structural diagram of a code sharing apparatus for a multi-core SOC according to a fifth embodiment of the present invention, where the apparatus may perform the code sharing method for the multi-core SOC according to the foregoing embodiments. Referring to fig. 6, the apparatus includes: an information acquisition module 610, an information linking module 620, an information storage module 630 and an address assignment module 640.
An information obtaining module 610, configured to obtain uniform code class information corresponding to the multi-core SOC and data class information corresponding to each core in the multi-core SOC;
the information linking module 620 is configured to link the uniform code class information to the first logical address, and link each data class information to the second logical address respectively;
the information storage module 630 is configured to store the uniform code class information in a uniform storage space, and store the data class information in independent storage spaces corresponding to the cores, respectively;
and the address allocation module 640 is configured to allocate physical addresses of the unified storage space and each independent storage space to the matched kernels respectively.
In the scheme of this embodiment, uniform code class information corresponding to the multi-core SOC and data class information corresponding to each core in the multi-core SOC are acquired by the information acquisition module; linking the uniform code information to a first logic address through an information linking module, and respectively linking each data information to a second logic address; the unified code information is stored in the unified storage space through the information storage module, and the data information is respectively stored in the independent storage space corresponding to each kernel; the physical addresses of the unified storage space and each independent storage space are respectively allocated to the matched kernels through the address allocation module, so that the problems that the code and data of the multi-core SOC cannot be shared and the expenditure of the memory space is increased in the prior art are solved, the code and data of the multi-core SOC are shared, and the expenditure of the memory space is reduced.
Optionally, the information obtaining module is specifically configured to respond to a compiling instruction of the kernel code, and decompose an executable instruction corresponding to each kernel in the multi-kernel SOC into code information and data information, respectively;
and if the code class information of each kernel is the same, acquiring any code class information as the conventional code class information.
Optionally, the code sharing apparatus of the multi-core SOC further includes: a first mapping module and a second mapping module; the first mapping module is used for responding to a starting instruction of a target kernel in the multi-core SOC and mapping an independent storage space corresponding to the target kernel to a second logic address;
and the second mapping module is used for mapping the uniform storage space to the first logic address.
Optionally, the first mapping module is specifically configured to map, through the MMU, the independent storage space corresponding to the target kernel to the second logical address.
Optionally, the code sharing apparatus of the multi-core SOC further includes: the information determining module is used for determining uniform code class information corresponding to a target kernel through a first logic address after the target kernel in the multi-core SOC is started; and determining the data class information corresponding to the target kernel through the second logical address.
Optionally, the uniform code class information related in the embodiment of the present invention includes an executable code and a read-only constant RO-data; the data class information includes: an initialized readable and writable variable RW-data and/or an uninitialized readable and writable variable ZI-data.
The multi-core SOC code sharing device provided by the embodiment of the invention can execute the multi-core SOC code sharing method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
EXAMPLE six
Fig. 7 is a schematic structural diagram of a multi-core SOC in a sixth embodiment of the present invention, and as shown in fig. 7, the apparatus/terminal/server includes a processor 70, a memory 71, an input device 72, and an output device 73; the number of processors 70 in the device/terminal/server may be one or more, and one processor 70 is taken as an example in fig. 7; the processor 70, the memory 71, the input device 72 and the output device 73 in the device/terminal/server may be connected by a bus or other means, which is exemplified in fig. 7.
The memory 71 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the code sharing method of the multi-core SOC in the embodiment of the present invention (for example, the information acquisition module 610, the information linking module 620, the information storage module 630, and the address assignment module 640 in the code sharing apparatus of the multi-core SOC). The processor 70 executes various functional applications and data processing of the device/terminal/server by running software programs, instructions, and modules stored in the memory 71, that is, implements the code sharing method of the multi-core SOC described above.
The memory 71 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 71 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 71 may further include memory remotely located from the processor 70, which may be connected to the device/terminal/server via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 72 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the device/terminal/server. The output device 73 may include a display device such as a display screen.
EXAMPLE seven
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a code sharing method for a multi-core SOC, where the method includes:
acquiring uniform code class information corresponding to the multi-core SOC and data class information corresponding to each core in the multi-core SOC;
linking the uniform code class information to a first logic address, and linking each data class information to a second logic address respectively;
storing the uniform code information in a uniform storage space, and storing the data information in independent storage spaces corresponding to the cores respectively;
and respectively allocating the physical addresses of the unified storage space and each independent storage space to the matched kernels.
Of course, the storage medium containing the computer-executable instructions provided by the embodiments of the present invention is not limited to the method operations described above, and may also perform related operations in the code sharing method for a multi-core SOC provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for a person skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the code sharing apparatus for a multi-core SOC, each included unit and each included module are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, the specific names of the functional units are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions without departing from the scope of the invention. Therefore, although the present invention has been described in more detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A code sharing method of a multi-core system-on-chip (SOC) is characterized by comprising the following steps:
acquiring uniform code class information corresponding to the multi-core SOC and data class information corresponding to each kernel in the multi-core SOC;
linking the uniform code information to a first logic address, and linking the data information to a second logic address respectively;
storing the uniform code information in a uniform storage space, and storing the data information in independent storage spaces corresponding to the kernels respectively;
and respectively allocating the physical addresses of the unified storage space and each independent storage space to the matched kernels.
2. The method of claim 1, wherein obtaining uniform code class information corresponding to the multi-core SOC and data class information corresponding to each core in the multi-core SOC comprises:
decomposing executable instructions corresponding to each kernel in the multi-kernel SOC into code class information and data class information respectively in response to a compiling instruction of the kernel code;
and if the code class information of the kernels is the same, acquiring any code class information as the uniform code class information.
3. The method according to claim 1 or 2, wherein after allocating the physical addresses of the unified memory space and the independent memory spaces to the matched kernels respectively, the method further comprises:
in response to a starting instruction of a target kernel in the multi-core SOC, mapping an independent storage space corresponding to the target kernel to the second logical address;
and mapping the unified storage space to the first logical address.
4. The method of claim 3, wherein mapping the independent memory space corresponding to the target core to the second logical address comprises:
and mapping the independent storage space corresponding to the target kernel to the second logical address through a Memory Management Unit (MMU).
5. The method of claim 3, further comprising:
after a target kernel in the multi-core SOC is started, determining the uniform code class information corresponding to the target kernel through the first logic address;
and determining the data class information corresponding to the target kernel through the second logical address.
6. The method of claim 1,
the uniform code class information comprises an executable code and a read-only constant RO-data;
the data class information includes: an initialized readable and writable variable RW-data and/or an uninitialized readable and writable variable ZI-data.
7. A code sharing apparatus of a multi-core SOC, comprising:
the information acquisition module is used for acquiring uniform code class information corresponding to the multi-core SOC and data class information corresponding to each core in the multi-core SOC;
the information linking module is used for linking the uniform code information to a first logic address and linking each data information to a second logic address respectively;
the information storage module is used for storing the uniform code information into a uniform storage space and storing the data information into independent storage spaces respectively corresponding to the kernels;
and the address allocation module is used for allocating the physical addresses of the unified storage space and each independent storage space to the matched kernel respectively.
8. The apparatus according to claim 7, wherein the information obtaining module is specifically configured to, in response to a compiling instruction of a kernel code, decompose an executable instruction corresponding to each kernel in the multi-kernel SOC into code class information and data class information, respectively;
and if the code class information of the kernels is the same, acquiring any code class information as the uniform code class information.
9. A multi-core SOC comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the code sharing method of the multi-core SOC of any one of claims 1-6 when executing the program.
10. A storage medium containing computer-executable instructions for performing the code sharing method of the multi-core SOC of any one of claims 1-6 when executed by a computer processor.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114741137A (en) * | 2022-05-09 | 2022-07-12 | 潍柴动力股份有限公司 | Software starting method, device, equipment and storage medium based on multi-core microcontroller |
| CN114741137B (en) * | 2022-05-09 | 2024-02-20 | 潍柴动力股份有限公司 | Software starting method, device, equipment and storage medium based on multi-core microcontroller |
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