CN113965705A - CMOS pixel addressing module and method - Google Patents
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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Abstract
The embodiment of the application discloses a CMOS pixel addressing module and a method, wherein the CMOS pixel addressing module is connected with a CMOS pixel array structure; the CMOS pixel array structure includes: a plurality of CMOS pixel array blocks; the CMOS pixel addressing module includes: the device comprises an address control module and a plurality of row address decoders which are connected with the address control module; the address control module is connected with each CMOS pixel array block; each CMOS pixel array block corresponds to a row address decoder and is connected with the corresponding row address decoder. By the scheme of the embodiment, the block direct addressing is realized, the addressing speed is increased, and the overall yield and reliability are improved.
Description
Technical Field
Embodiments of the present disclosure relate to photodiode detector design technologies, and more particularly, to a CMOS pixel addressing module and method.
Background
The current flat panel detector has reached wafer level and can be spliced on three sides, and more than 90% of the whole flat panel is a CMOS (complementary metal oxide semiconductor) pixel array. The main working modes of the product are a full frame mode and an ROI (Region of Interest) mode. The ROI mode requires addressing to a designated detector area and reading out its charge. The prior addressing technique utilizes a conventional shift register chain approach as shown in fig. 1.
In fig. 1, CLK is a clock terminal, D is a register data terminal, ROW _ SEL is a shift register chain output terminal, and is responsible for gating the CMOS pixel of a designated address, and RST is a CMOS pixel reset signal. For example, to gate a CMOS pixel controlled by ROW _ SEL [2], it is necessary to shift a high level 1 from the D terminal through ROW _ SEL [0], ROW _ SEL [1] to ROW _ SEL [2] in sequence.
Currently, there is an ROI addressing technology, where an addressed shift register chain penetrates through a whole CMOS pixel array, and when a flat panel detector has a large area and the scale of the CMOS pixel array is very large, if a CMOS pixel at a far end of a distance D is addressed, addresses need to be sequentially shifted through the whole shift register chain to be reached. This design has one significant drawback or disadvantage:
1. the addressing is complicated and time-consuming.
Each addressing requires moving the address through the shift register chain, especially longer for reading the far-end CMOS pixel signals.
2. The reliability is poor.
The shift register chain is a whole, wherein any stage fails, and the whole register chain cannot work. In addition, the wafer level chip has large area, the defect probability is improved, and the failure rate of the shift register chain is increased.
Disclosure of Invention
The embodiment of the application provides a CMOS pixel addressing module and a method, which can directly address in blocks, improve the addressing speed and improve the overall yield and reliability.
The embodiment of the application provides a CMOS pixel addressing module which is connected with a CMOS pixel array structure; the CMOS pixel array structure comprises a plurality of CMOS pixel array blocks; (ii) a
The CMOS pixel array structure may include: a plurality of vertically arranged CMOS pixel array blocks; each CMOS pixel array block comprises a plurality of CMOS pixels which are arranged according to a preset rule;
the CMOS pixel addressing module may include: the device comprises an address control module and a plurality of row address decoders connected with the address control module;
the address control module is connected with each CMOS pixel array block;
each CMOS pixel array block corresponds to a row address decoder and is connected with the corresponding row address decoder.
In an exemplary embodiment of the present application, all CMOS pixel array blocks in the CMOS pixel array structure are the same;
addresses of all the CMOS pixels in each row in each CMOS pixel array block are the same, and addresses of the CMOS pixels in each column are sequentially increased.
In an exemplary embodiment of the present application, all row address decoders in the CMOS pixel addressing module are the same;
each row address decoder is connected with the CMOS pixels of each row of the corresponding CMOS pixel array block through a preset block row selection signal line,
the number of the row selection signal lines in the block is the same as that of the rows of the CMOS pixel array block.
In an exemplary embodiment of the present application, each of the row address decoders is connected to the CMOS pixels of each row of the corresponding CMOS pixel array block through a preset intra-block row reset signal line,
the number of the row reset signal lines in the block is the same as the number of the rows of the CMOS pixel array block.
In an exemplary embodiment of the present application, the address control block is connected to each CMOS pixel array block through a preset block selection signal line.
In an exemplary embodiment of the present application, each CMOS pixel array block corresponds to one routing area; the routing types and the routing modes of the routing areas corresponding to all the CMOS pixel array blocks are the same.
The embodiment of the present application further provides a CMOS pixel addressing method, based on the CMOS pixel addressing module, the method may include:
generating, by an address control block of the CMOS pixel addressing module, a block selection signal for selecting a CMOS pixel array block to enable the selected CMOS pixel array block by the block selection signal;
generating a block row selection signal for selecting a row in a CMOS pixel array block by the address control module, and sending the block row selection signal to a row address decoder of the CMOS pixel addressing module;
and decoding the row selection signal in the block by the row address decoder to address the target CMOS pixel.
In an exemplary embodiment of the present application, the row address decoder, which is transmitted to the CMOS pixel addressing module, may include:
and sending the data to all row address decoders of the CMOS pixel addressing module, or sending the data to a row address decoder corresponding to the selected CMOS pixel array block.
In an exemplary embodiment of the present application, the method may further include:
and when the address control module receives a reset instruction, generating an in-block row reset signal for resetting the CMOS pixels of each row in the CMOS pixel array block, and sending the in-block row reset signal to the corresponding row address decoder.
In an exemplary embodiment of the present application, the method may further include:
decoding the block internal row reset signal through the row address decoder, and resetting the target CMOS pixel.
Compared with the related art, the CMOS pixel addressing module of the embodiment of the application is connected with the CMOS pixel array structure; the CMOS pixel array structure comprises a plurality of CMOS pixel array blocks; the CMOS pixel addressing module includes: the device comprises an address control module and a plurality of row address decoders which are connected with the address control module; the address control module is connected with each CMOS pixel array block; each CMOS pixel array block corresponds to a row address decoder and is connected with the corresponding row address decoder. By the scheme of the embodiment, the block direct addressing is realized, the addressing speed is increased, and the overall yield and reliability are improved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.
Drawings
The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
FIG. 1 is a diagram illustrating a conventional shift register chain addressing method in the related art;
FIG. 2 is a block diagram of an embodiment of a CMOS pixel addressing module;
FIG. 3 is a schematic diagram of a CMOS pixel addressing module according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a flat panel detector according to an embodiment of the present application;
fig. 5 is a flow chart of a CMOS pixel addressing method according to an embodiment of the present application.
Detailed Description
The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
The embodiment of the application provides a CMOS pixel addressing module, which is a wafer-level three-side spliced CMOS pixel detector rapid addressing module, as shown in figure 2, a complementary metal oxide semiconductor CMOS pixel addressing module 2 is connected with a CMOS pixel array structure 1; the CMOS pixel array structure 1 includes a plurality of CMOS pixel array blocks 11;
the CMOS pixel array structure 1 includes: a plurality of vertically arranged CMOS pixel array blocks 11; each CMOS pixel array block 11 includes a plurality of CMOS pixels arranged according to a preset rule;
the CMOS pixel addressing module 2 comprises: an address control module 21 and a plurality of row address decoders 22 each connected to the address control module 21;
the address control module 21 is connected with each CMOS pixel array block 11;
each CMOS pixel array block 11 corresponds to one row address decoder 22, and is connected to the corresponding row address decoder 22.
In an exemplary embodiment of the present application, as shown in fig. 3, for example, the CMOS pixel array block arranged longitudinally may include m, m being a positive integer, for example: block 1CMOS Pixel Array, Block 2CMOS Pixel Array, Block 3CMOS Pixel Array, … …, Block m CMOS Pixel Array.
In an exemplary embodiment of the present application, each Block CMOS pixel Array is a CMOS pixel Array Block of the same structural scale.
In an exemplary embodiment of the present application, a plurality of CMOS pixels included in each CMOS pixel array block are arranged in a rectangular or positive direction;
addresses of all the CMOS pixels in each row in each CMOS pixel array block are the same, and addresses of the CMOS pixels in each column are sequentially increased.
In the exemplary embodiment of the present application, when each CMOS pixel array block includes a plurality of columns of CMOS pixels, for example, i columns of CMOS pixels are included, i being a positive integer, and the addresses of the i columns of CMOS pixels in the longitudinal direction in each CMOS pixel array block are sequentially 1 to i.
In the exemplary embodiment of the present application, when more CMOS pixels need to be expanded within the CMOS pixel array structure, more CMOS pixel array blocks may continue to be expanded in the longitudinal direction on the basis of a plurality of CMOS pixel array blocks.
In an exemplary embodiment of the present application, as shown in fig. 2, a CMOS pixel addressing module 2 may be used to address the CMOS pixel array structure 1; the CMOS pixel addressing module may include: the device comprises an Address control module (21), an Address Ctrl and a plurality of Row Address decoders (22) Row decoders, wherein the Row Address decoders are connected with the Address Ctrl of the Address control module (21);
the Address control module (21) Address Ctrl is connected to each CMOS pixel array block in the CMOS pixel array structure 1;
each CMOS pixel array block in the CMOS pixel array structure corresponds to a row address decoder respectively and is connected with the corresponding row address decoder.
In an exemplary embodiment of the present application, the Address control module (21) Address Ctrl may be connected to a plurality of Row Address decoders (22) Row Decoder via a Row Address Bus (Row Address Bus).
In an exemplary embodiment of the present application, each CMOS pixel array block corresponds to the same Row address Decoder (22) Row Decoder.
In an exemplary embodiment of the present application, as shown in fig. 3, each Row address Decoder (22) Row Decoder is connected to the CMOS pixels of each Row of the corresponding CMOS pixel array block, respectively.
In the exemplary embodiment of the present application, each of the Row address decoders Row Decoder is connected to the CMOS pixels of each Row of the corresponding CMOS pixel array block through a preset block Row selection signal line,
the number of the row selection signal lines in the block is the same as that of the rows of the CMOS pixel array block.
In an exemplary embodiment of the present application, each of the row address decoders is connected to the CMOS pixels of each row of the corresponding CMOS pixel array block through a preset intra-block row reset signal line,
the number of the row reset signal lines in the block is the same as the number of the rows of the CMOS pixel array block.
In an exemplary embodiment of the present application, as shown in fig. 3, the Address control block Address Ctrl is connected to each CMOS pixel array block through a preset block selection signal line.
In an exemplary embodiment of the present application, the Address control module Address Ctrl may be configured to generate a block selection signal BlockEn for selecting a CMOS pixel array block, and send the block selection signal BlockEn to the selected CMOS pixel array block; and generating a block Row selection signal RowSel for selecting a Row within the CMOS pixel array block, and transmitting the block Row selection signal RowSel to the corresponding Row address Decoder Row Decoder.
In an exemplary embodiment of the present application, the Block 1CMOS pixel Array, the Block 2CMOS pixel Array, the Block 3CMOS pixel Array, … …, and the Block m CMOS pixel Array may correspond to corresponding Block selection signals Block en [0], Block en [1], Block en [2], … …, Block en [ m-1], respectively.
In an exemplary embodiment of the present application, a selected CMOS pixel array block is directly enabled by a corresponding BlockEn signal of the CMOS pixel array block without going through a shift register chain.
In an exemplary embodiment of the present application, the Row Decoder Row.
In the exemplary embodiment of the present application, only the Row address Decoder Row Decoder corresponding to the selected CMOS pixel array block decodes and addresses the target CMOS pixel in the ROI mode.
In an exemplary embodiment of the present application, each row address (e.g., RowAddr1, RowAddr2, … …, RowAddr n) in each CMOS pixel array block may correspond to a corresponding intra-block row select signal RowSel (e.g., RowSel _1, RowSel _2, … …, RowSel _ n).
In an exemplary embodiment of the present application, the Address control module Address Ctrl may be further configured to generate an intra-block Row reset signal RowRst for resetting each Row of CMOS pixels in the CMOS pixel array block, and send the intra-block Row reset signal RowRst to the corresponding Row Address Decoder Row Decoder.
In an exemplary embodiment of the present application, the Row reset signal RowRst in the block generated by the Address control module Address Ctrl is simultaneously connected to all the Row Address decoders Row Decoder, and the Row reset signal RowRst in the block resets the target CMOS pixels after being decoded by the Row Address decoders Row Decoder.
In the exemplary embodiment of the present application, only the Row address Decoder Row Decoder corresponding to the selected CMOS pixel array block decodes and addresses the target CMOS pixel and resets the target CMOS pixel in the ROI mode.
In an exemplary embodiment of the present application, each row address (e.g., RowAddr1, RowAddr2, … …, RowAddr n) in each CMOS pixel array block may correspond to a corresponding intra-block row reset signal RowRst (e.g., RowRst _1, RowRst _2, … …, RowRst _ n).
In an exemplary embodiment of the present application, as shown in fig. 3, one routing region P (e.g., P1, P2, P3) corresponds to each CMOS pixel array block; all the block selection signal lines are arranged in the routing area P;
in each routing region P, routing modes of other block selection signal lines except for the block selection signal line of the CMOS pixel array block corresponding to the routing region are the same.
In an exemplary embodiment of the present application, the Block 1CMOS pixel Array, the Block 2CMOS pixel Array, the Block 3CMOS pixel Array, … …, and the Block m CMOS pixel Array may respectively correspond to the corresponding routing regions P1, P2, P3, … …, Pm.
In the exemplary embodiment of the present application, in each routing area, the layout routing of BlockEn may adopt a 'Z' routing, and the 'Z' routing layouts of BlockEn in P1, P2, P3, … …, and Pm may be identical.
In the exemplary embodiment of the present application, when the area of the flat panel detector needs to be expanded, and more CMOS pixel array blocks need to be expanded, theoretically, a plurality of blocks as shown in L1, L2, and L3 can be infinitely spliced in the longitudinal direction without re-customizing layout routing and CMOS pixel arrays.
In an exemplary embodiment of the present application, the CMOS pixel addressing module described above may be applied in a flat panel detector 3, as shown in fig. 4.
In an exemplary embodiment of the present application, a Pixel Array is a detector portion of the present application, that is, the CMOS Pixel Array structure 1, and the analog-to-digital converter ADC is responsible for converting signals of CMOS pixels into digital signals and outputting the digital signals through an LVDS Driver (low voltage differential signal Driver) port after sequentially passing through an Algorithm & Timing Control (algorithmic & Timing Control) module and a FIFO (first in first out) module. The Global Timing Control module is connected to the Vertical Scanning Block module, which is the CMOS pixel addressing module 2 and is responsible for addressing and resetting the CMOS pixels, to generate all Timing Control signals. The other end of the Global Timing Control module is connected with an I2C Port (inter-Integrated Circuit bus interface). A temperature Sensor (Temp Sensor) may also be provided in the flat panel detector 3. The flat panel detector 3 may also include a Voltage & Current Generator (Voltage Current Generator) that supplies power to the Pixel Array and ADC.
The embodiment of the present application further provides a CMOS pixel addressing method, based on the CMOS pixel addressing module, as shown in fig. 5, the method may include steps S101 to S103:
s101, generating a block selection signal for selecting a CMOS pixel array block by an address control module of the CMOS pixel addressing module so as to enable the selected CMOS pixel array block through the block selection signal;
s102, generating a block row selection signal for selecting a row in a CMOS pixel array block by the address control module, and sending the block row selection signal to a row address decoder of the CMOS pixel addressing module;
s103, decoding the row selection signal in the block through the row address decoder, and addressing to a target CMOS pixel.
In an exemplary embodiment of the present application, the row address decoder, which is transmitted to the CMOS pixel addressing module, may include:
and sending the data to all row address decoders of the CMOS pixel addressing module, or sending the data to a row address decoder corresponding to the selected CMOS pixel array block.
In an exemplary embodiment of the present application, the method may further include:
and when the address control module receives a reset instruction, generating an in-block row reset signal for resetting the CMOS pixels of each row in the CMOS pixel array block, and sending the in-block row reset signal to the corresponding row address decoder.
In an exemplary embodiment of the present application, the method may further include:
decoding the block internal row reset signal through the row address decoder, and resetting the target CMOS pixel.
In the exemplary embodiment of the present application, any of the foregoing system embodiments is applicable to the method embodiment, and details are not repeated here.
In the exemplary embodiments of the present application, the embodiments of the present application have at least the following advantages:
1. the traditional shift register chain addressing mode is abandoned, and a block direct addressing mode is adopted, so that the target CMOS pixel can be directly and quickly addressed, and the addressing speed is improved.
2. In the aspects of circuit structure and physical design, a block addressing mode is adopted, each CMOS pixel array block is independently addressed, even if a certain decoder fails, the work of other blocks cannot be hindered, and the overall yield and reliability are improved.
3. In the aspect of layout design, block enable signal layouts of each CMOS pixel array are completely consistent, new-type products are designed, and the products can be directly reused when the area of a flat plate is expanded, so that repeated labor is avoided, and the design time is shortened.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (10)
1. A CMOS pixel addressing module is characterized by being connected with a CMOS pixel array structure; the CMOS pixel array structure comprises a plurality of CMOS pixel array blocks;
the CMOS pixel addressing module includes: the device comprises an address control module and a plurality of row address decoders connected with the address control module;
the address control module is connected with each CMOS pixel array block;
each CMOS pixel array block corresponds to a row address decoder and is connected with the corresponding row address decoder.
2. The CMOS pixel addressing module of claim 1, wherein all CMOS pixel array blocks are identical;
addresses of all the CMOS pixels in each row in each CMOS pixel array block are the same, and addresses of the CMOS pixels in each column are sequentially increased.
3. A CMOS pixel addressing module according to claim 1 or 2, wherein all row address decoders in the CMOS pixel addressing module are identical;
each row address decoder is connected with the CMOS pixels of each row of the corresponding CMOS pixel array block through a preset block row selection signal line;
the number of the row selection signal lines in the block is the same as that of the rows of the CMOS pixel array block.
4. The CMOS pixel addressing module of claim 1 or 2, wherein each row address decoder is connected to the CMOS pixels of each row of the corresponding CMOS pixel array block through a preset intra-block row reset signal line,
the number of the row reset signal lines in the block is the same as the number of the rows of the CMOS pixel array block.
5. The CMOS pixel addressing module of claim 1 or 2, wherein the address control module is connected to each CMOS pixel array block via a predetermined block selection signal line.
6. The CMOS pixel addressing module of claim 1 or 2, wherein each CMOS pixel array block corresponds to one routing area; the routing types and the routing modes of the routing areas corresponding to all the CMOS pixel array blocks are the same.
7. A CMOS pixel addressing method, based on the CMOS pixel addressing module of any of claims 1-6, the method comprising:
generating, by an address control block of the CMOS pixel addressing module, a block selection signal for selecting a CMOS pixel array block to enable the selected CMOS pixel array block by the block selection signal;
generating a block row selection signal for selecting a row in a CMOS pixel array block by the address control module, and sending the block row selection signal to a row address decoder of the CMOS pixel addressing module;
and decoding the row selection signal in the block by the row address decoder to address the target CMOS pixel.
8. The CMOS pixel addressing method of claim 7, wherein the row address decoder sent to the CMOS pixel addressing module comprises:
and sending the data to all row address decoders of the CMOS pixel addressing module, or sending the data to a row address decoder corresponding to the selected CMOS pixel array block.
9. The CMOS pixel addressing method of claim 7, further comprising:
and when the address control module receives a reset instruction, generating an in-block row reset signal for resetting the CMOS pixels of each row in the CMOS pixel array block, and sending the in-block row reset signal to the corresponding row address decoder.
10. The CMOS pixel addressing method of claim 9, further comprising:
decoding the block internal row reset signal through the row address decoder, and resetting the target CMOS pixel.
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