CN113964138A - Display substrate, display panel and display device - Google Patents
Display substrate, display panel and display device Download PDFInfo
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- CN113964138A CN113964138A CN202111217471.4A CN202111217471A CN113964138A CN 113964138 A CN113964138 A CN 113964138A CN 202111217471 A CN202111217471 A CN 202111217471A CN 113964138 A CN113964138 A CN 113964138A
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- 239000000758 substrate Substances 0.000 title claims abstract description 74
- 239000002184 metal Substances 0.000 claims abstract description 55
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 239000002245 particle Substances 0.000 abstract description 12
- 239000000428 dust Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 105
- 238000005538 encapsulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
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Abstract
The embodiment of the invention discloses a display substrate, a display panel and a display device, wherein an anode in a third sub-pixel is arranged to be not overlapped with the orthographic projection of a latticed power line on a substrate, so that particles (foreign matters, dust and the like) on the latticed power line cannot penetrate through a flat layer between a first source-drain metal layer and the anode and then directly contact with the anode (the power line is in short circuit with the anode), and the problem of poor bright spots when a screen is lightened at the rear end is avoided.
Description
Technical Field
The invention relates to the technical field of vehicle-mounted display, in particular to a display substrate, a display panel and a display device.
Background
At present, the display technology is widely applied to the vehicle-mounted field, and the requirement of vehicle-mounted display on the product yield of a display screen is high.
Disclosure of Invention
The embodiment of the invention provides a display substrate, a display panel and a display device, which are used for solving the problem that a vehicle-mounted display product has bad bright spots when a screen is lightened and improving the yield of the product.
An embodiment of the present invention provides a display substrate, including: the pixel structure comprises a substrate, a first source drain metal layer and a plurality of sub-pixels, wherein the first source drain metal layer is positioned on one side of the substrate, and the plurality of sub-pixels are positioned on one side, away from the substrate, of the first source drain metal layer;
the plurality of sub-pixels are divided into a first sub-pixel, a second sub-pixel and a third sub-pixel, and the plurality of sub-pixels are divided into a plurality of sub-pixel columns; the plurality of sub-pixel columns include: a first sub-pixel column composed of the first sub-pixels and the second sub-pixels alternately arranged, and a second sub-pixel column composed of the third sub-pixels; the first sub-pixel columns and the second sub-pixel columns are alternately arranged;
the first source-drain metal layer comprises a grid-shaped power line, each sub-pixel comprises an anode, and the anode in the third sub-pixel is not overlapped with the orthographic projection of the power line on the substrate.
Optionally, in the display substrate provided in an embodiment of the present invention, the display substrate further includes: the second source-drain metal layer is positioned between the substrate base plate and the first source-drain metal layer, and the first flat layer is positioned between the first source-drain metal layer and the second source-drain metal layer;
the grid-shaped power line comprises a first grid arranged around the third sub-pixel, and the first grid is formed by sequentially connecting first grid lines arranged along the row direction and second grid lines arranged along the column direction;
the latticed power line further comprises a connecting part which is crossed with the second grid lines and is electrically connected with the second grid lines, the connecting part is located between the adjacent third sub-pixels, the connecting part and the second grid lines are of an integrated structure, and the end part, close to the third sub-pixels, of the connecting part is electrically connected with the second source drain metal layer through a through hole penetrating through the first flat layer.
Optionally, in the display substrate provided in the embodiment of the present invention, a width of the connection portion in the row direction is 2.7 μm to 3.3 μm, and a width of the second grid line in the column direction is 1.8 μm to 2.4 μm.
Optionally, in the display substrate provided in the embodiment of the present invention, the grid-shaped power line further includes a second grid disposed around the first sub-pixel and the second sub-pixel, and the second grid is formed by sequentially connecting a third grid line arranged in a row direction and a fourth grid line arranged in a column direction;
the orthographic projection of the third grid line on the substrate base plate is mutually overlapped with the orthographic projections of the first sub-pixel and the second sub-pixel on the substrate base plate, and the fourth grid line is positioned between the adjacent first sub-pixel and the adjacent second sub-pixel.
Optionally, in the display substrate provided in the embodiment of the present invention, the fourth grid line is electrically connected to a center position of the first grid line, the second grid line is electrically connected to a center position of the third grid line, and the first grid line and the third grid line are an integral structure extending in a column direction and have a common portion.
Optionally, in the display substrate provided in the embodiment of the present invention, a width of the third grid line in the row direction is 2.2 μm to 2.8 μm, and a width of the fourth grid line in the column direction is 1.8 μm to 2.4 μm.
Optionally, in the display substrate provided in an embodiment of the present invention, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.
Optionally, in the display substrate provided in the embodiment of the present invention, a second planarization layer located between the first source-drain metal layer and the anode is further included.
Correspondingly, the embodiment of the invention also provides a display panel which comprises the display substrate.
Correspondingly, the embodiment of the invention also provides a display device which comprises the display panel.
The embodiment of the invention has the following beneficial effects:
according to the display substrate, the display panel and the display device provided by the embodiment of the invention, the anode in the third sub-pixel is arranged to be not overlapped with the orthographic projection of the latticed power line on the substrate, so that particles (foreign matters, dust and the like) on the latticed power line cannot penetrate through the flat layer between the first source-drain metal layer and the anode and then directly contact with the anode (the power line is in short circuit with the anode), and the problem of poor bright spots when a screen is lightened at the rear end is avoided.
Drawings
Fig. 1 is a schematic top view of a display substrate provided in the related art;
FIG. 2 is a schematic cross-sectional view along AA' of FIG. 1;
fig. 3 is a schematic top view of a display substrate according to an embodiment of the invention;
FIG. 4 is a schematic cross-sectional view taken along the direction CC' of FIG. 3;
FIG. 5 is a schematic cross-sectional view taken along direction CC' of FIG. 3;
FIG. 6 is a schematic diagram of a pixel circuit;
fig. 7 is a schematic cross-sectional structure diagram of a sub-pixel.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a display substrate, a display panel and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The thickness, size and shape of the various layers of film in the drawings do not reflect the actual scale of the display substrate and are intended to be illustrative only of the present invention.
The Organic Light-Emitting Diode (OLED) display technology has the advantages of self-luminescence, wide viewing angle, almost infinite contrast, low power consumption, extremely high response speed, and the like, and is known as a new generation display technology. The full-screen OLED product has become a mainstream for development, a power line (VDD) of the OLED product generally adopts a double-layer SD trace, and an SD trace closest to an anode (hereinafter referred to as a first trace) and the anode generally overlap each other. For display products, such as mobile phones, which pursue high PPI (pixel resolution), the Anode (Anode) size of an OLED full-screen product is small and the first routing line is narrow, and the area of the first routing line covered by the Anode is also small. On the other hand, for a full-screen vehicle-mounted OLED product, because the requirement of vehicle-mounted display on pixel resolution is not so high, the anode has a large size and a wide first routing line, as shown in fig. 1 and fig. 2, fig. 1 is a schematic top view of a part of a film layer in the vehicle-mounted display product, fig. 2 is a schematic cross section along the AA' direction in fig. 1, the vehicle-mounted display product includes a first source-drain metal layer 2, a first flat layer 3, a second source-drain layer (the film layer where the first routing line 4 is located), a second flat layer 5 and an anode layer 6, which are sequentially stacked on a substrate 1, the anode layer 6 includes a plurality of anodes (represented by R, G, B) corresponding to different color sub-pixels, because the requirement of vehicle-mounted display on pixel resolution is not so high, R, G, B arrangement generally adopts R, G in the same column, B is in a single column, and R, G is tightly arranged, and B is sparsely arranged, the first trace 4 is in a grid shape, and in the pattern design, the area of the first trace 4 covered by the anode (R, G, B) is correspondingly increased. Since the first trace 4 is wider, particles (such as foreign matters and dust) on the first trace 4 can penetrate through the second flat layer 5 between the first trace 4 and the anode (R, G, B) to directly contact with the anode (R, G or B), i.e. the first trace 4 and the anode (R, G (R, G, B) B) are shorted, which causes poor bright spot when the rear end is bright. The inventor of the present application finds that the vehicle-mounted OLED full-screen product has 5% of bright point failures, wherein 30% of the bright point failures can be traced to the particle on the first trace 4. Therefore, the influence of particles on the first routing wire on the full-screen product of the vehicle-mounted OLED on the anode layer is increased, and the product yield is reduced.
In view of the above, an embodiment of the invention provides a display substrate, as shown in fig. 3 and fig. 4, where fig. 3 is a schematic top view of a portion of a film layer in the display substrate, and fig. 4 is a schematic cross-sectional view along CC' direction in fig. 3, including: the pixel structure comprises a substrate base plate 10, a first source-drain metal layer 20 positioned on one side of the substrate base plate 10, and a plurality of sub-pixels (for example R, G, B) positioned on one side, away from the substrate base plate 10, of the first source-drain metal layer 20;
the plurality of sub-pixels are divided into a first sub-pixel (e.g., red sub-pixel R), a second sub-pixel (e.g., green sub-pixel G), and a third sub-pixel (e.g., blue sub-pixel B), the plurality of sub-pixels (R, G, B) are divided into a plurality of sub-pixel columns; the plurality of sub-pixel columns include: a first sub-pixel column composed of first and second sub-pixels R and G alternately arranged, and a second sub-pixel column composed of third sub-pixels B; the first sub-pixel columns and the second sub-pixel columns are alternately arranged;
the first source-drain metal layer 20 includes a grid-shaped power line VDD, each sub-pixel includes an anode 30, and the anode 30 in the third sub-pixel B does not overlap with the orthographic projection of the power line VDD on the substrate 10.
In the display substrate provided by the embodiment of the invention, the anode 30 in the third sub-pixel B is arranged to be not overlapped with the orthographic projection of the latticed power line VDD on the substrate 10, so that particles (foreign matters, dust and the like) on the latticed power line VDD do not penetrate through the flat layer between the first source-drain metal layer 20 and the anode 30 and then directly contact with the anode 30 (the power line VDD is in short circuit with the anode 30), and the problem of poor bright spots when a screen is lighted at the rear end is avoided.
In a specific implementation, as shown in fig. 3 and 4, the display substrate provided in the embodiment of the present invention further includes: a second source-drain metal layer 40 located between the substrate base plate 10 and the first source-drain metal layer 20, and a first planarization layer 50 located between the first source-drain metal layer 20 and the second source-drain metal layer 40;
the grid-shaped power supply line VDD includes a first grid 201 disposed around the third sub-pixel B, and the first grid 201 is formed by sequentially connecting first grid lines 2011 arranged in the row direction X and second grid lines 2012 arranged in the column direction Y;
the grid-shaped power line VDD further includes a connection portion 2013 crossing the second grid lines 2012 and electrically connected to the second grid lines 2012, the connection portion 2013 is located between the adjacent third sub-pixels B, the connection portion 2013 and the second grid lines 2012 are an integral structure, and an end portion of the connection portion 2013 close to the third sub-pixels B is electrically connected to the second source-drain metal layer 40 through a via penetrating through the first planarization layer 50. The display substrate further comprises a second planarization layer 60 located between the first source drain metal layer 20 and the anode 30. Specifically, when the grid-shaped power line VDD is manufactured in the embodiment of the present invention, the VDD in the shape shown in fig. 1 may be manufactured first, and the overlapped portion of the power line VDD and the B pixel in fig. 1 is etched away, so that the anode 30 is not overlapped with the grid-shaped power line VDD, and a particle on the power line VDD does not pierce through the second flat layer 60, that is, the power line VDD and the anode 30 are not shorted, so that the problem of poor bright point does not occur; and the end part of the connecting part 2013 close to the third sub-pixel B is electrically connected with the second source-drain metal layer 40 through a via penetrating through the first planarization layer 50, so that the problem that the display is poor due to the influence of the point discharge can be prevented.
It should be noted that, as shown in fig. 3, the first planarization layer 50 is a film layer between the first source-drain metal layer 20 and the second source-drain metal layer 40, and in fig. 3, the first planarization layer 50 is illustrated by using an approximately circular pattern, where the circular pattern is actually a via hole on the first planarization layer 50.
In practical implementation, as shown in fig. 1, the width d1 of the traces arranged along the row direction X is generally about 2.7 μm to 3.3 μm, and the width d2 of the traces arranged along the column direction Y is generally about 1.3 μm to 1.9 μm, in the embodiment of the invention shown in fig. 3, because a part of the power line VDD is removed, thus, the resistance value of the power line VDD is relatively large, in order to keep the design of the invention consistent with the resistance value of the original design, in the above display substrate provided by the embodiment of the invention, as shown in fig. 3 and 4, the width w1 of the connecting portion 2013 along the row direction X may be 2.7 μm to 3.3 μm (keeping the original design width), the width w2 of the second grid line 2012 along the column direction Y may be 1.8 μm to 2.4 μm, that is, the width w2 of the second grid line 2012 along the column direction Y is increased compared to the original design fig. 1, so that the resistance value is correspondingly increased to be consistent with the original design resistance value.
In practical implementation, in the display substrate provided in the embodiment of the present invention, as shown in fig. 3, the grid-shaped power line VDD further includes a second grid 202 disposed around the first sub-pixel R and the second sub-pixel G, and the second grid 202 is formed by sequentially connecting a third grid line 2021 arranged along the row direction X and a fourth grid line 2022 arranged along the column direction Y;
the orthographic projection of the third grid line 2021 on the substrate base plate 10 and the orthographic projection of the first sub-pixel R and the second sub-pixel G on the substrate base plate 10 are mutually overlapped, and the fourth grid line 2022 is positioned between the adjacent first sub-pixel R and the second sub-pixel G.
In a specific implementation, as shown in fig. 3, in the display substrate provided in the embodiment of the invention, the fourth grid line 2022 is electrically connected to a central position of the first grid line 2011, the second grid line 2012 is electrically connected to a central position of the third grid line 2021, and the first grid line 2011 and the third grid line 2021 are integrated structures extending in the column direction Y and have a common portion (an oval dashed-line frame portion).
In specific implementation, as shown in fig. 1, since the sub-pixel R, G and the first trace 4 arranged along the row direction X are overlapped with each other, and the width d1 of the first trace 4 is about 2.7 μm to 3.3 μm, a particle on the power line VDD may pierce through the flat layer between the anode and the first trace 4 and be shorted with the anode, so that, as shown in fig. 3, in the display substrate provided in the embodiment of the present invention, the width w3 of the third grid line 2021 along the row direction X may be 2.2 μm to 2.8 μm, that is, the width w3 of the third grid line 2021 along the row direction X is reduced compared with that of the original design fig. 1, thereby reducing the overlapping area of the third grid line 2021 and the anodes of the first sub-pixel R and the second sub-pixel G, and relatively reducing the probability that the particle of the first sub-pixel R and the second sub-pixel G pierces through the second flat layer 60, thereby further avoiding the problem of poor bright spots; since the width w3 of the third grid line 2021 along the row direction X is smaller than that of the original design fig. 1, the resistance of the power line VDD is correspondingly larger, and in order to keep the design of the present invention consistent with the resistance of the original design, the width w4 of the fourth grid line 2022 along the column direction Y may be 1.8 μm to 2.4 μm, that is, the width w4 of the fourth grid line 2022 along the column direction Y is larger than that of the original design fig. 1, so as to correspondingly reduce the resistance to be consistent with the resistance of the original design.
Note that, as shown in fig. 3, the power supply line VDD overlapping the first subpixel R and the second subpixel G is as close as possible to the edge R, G, which reduces the risk of display defects.
In a specific implementation, as shown in fig. 5, the display substrate provided in the embodiment of the present invention further includes: the active layer 70 is located between the substrate 10 and the second source-drain metal layer 40, the insulating layer 80 is located between the second source-drain metal layer 40 and the active layer 70, and the second source-drain metal layer 40 is electrically connected with the active layer 70 through a via hole penetrating through the insulating layer 80.
In specific implementation, each sub-pixel includes a light emitting device and a pixel circuit for driving the light emitting device to emit light, as shown in fig. 6 and 7, fig. 6 is a schematic diagram of the pixel circuit and the light emitting device L in each sub-pixel, and the pixel circuit takes a 7T1C structure as an example, but may have other structures; FIG. 7 is a schematic cross-sectional view of a sub-pixel; specifically, as shown in fig. 6, the pixel circuit includes: a driving transistor T1, a data writing transistor T2, a threshold compensating transistor T3, a reset transistor T4, a first light emission controlling transistor T5, a second light emission controlling transistor T6, an anode reset transistor T7, and a storage capacitor Cst; the first electrode S5 of the first light-emitting control transistor T5 is located in the second source-drain metal layer 40 in the embodiment of the present invention, and the first electrode S5 of the first light-emitting control transistor T5 is electrically connected to the power line VDD.
Specifically, the timing at which the pixel circuit shown in fig. 6 drives the light emitting device to emit light is as follows: in the reset phase, the reset transistor T4 and the anode reset transistor T7 are turned on, the data write transistor T2, the first light emission control transistor T5 and the second light emission control transistor T6 are turned off, the gate of the driving transistor T1 and the anode of the light emitting device L are initialized by the signal of the initialization signal terminal RL, and the gate of the driving transistor T1 is initialized to turn on the driving transistor T1. In the data write compensation stage, the data write transistor T2 and the threshold compensation transistor T3 are turned on, the reset transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the anode reset transistor T7 are turned off, and the data voltage Vdata is applied to the gate of the driving transistor T1 through the data write transistor T2, the driving transistor T1, and the threshold compensation transistor T3. At this time, the voltage applied to the gate of the driving transistor T1 is the compensation voltage Vdata + Vth (threshold voltage), and the compensation voltage applied to the gate of the driving transistor T1 is also applied to the first electrode CE1 of the storage capacitor Cst. In the light emitting phase, the first and second light emission controlling transistors T5 and T6 are turned on, and the data writing transistor T2, the threshold compensating transistor T3, the reset transistor T4, and the anode reset transistor T7 are turned off, so that the first light emission controlling transistor T5 applies the driving voltage VDD to the driving transistor T1, so that the light emitting devices of the respective sub-pixels emit light.
As shown in fig. 7, each sub-pixel includes a buffer layer 90, an active layer 70, a first gate insulating layer 100, a first gate layer 110, a second gate insulating layer 120, a second gate layer 130, an interlayer insulating layer 140, a second source-drain metal layer 40, a passivation layer 150, a first planarization layer 50, a first source-drain metal layer 20, a second planarization layer 60, an anode 30, a pixel defining layer 160, a light emitting layer 1/70, a cathode 180, an inorganic encapsulation layer 190, an organic encapsulation layer 200, and an inorganic encapsulation layer 210, which are sequentially stacked on a substrate 10; of these, fig. 4 and 5 only illustrate a part of the film structure, and the first gate insulating layer 100, the second gate insulating layer 120, and the interlayer insulating layer 140 in fig. 6 constitute the insulating layer 80 in fig. 5.
It should be noted that, in the embodiment of the present invention, the second source-drain metal layer 40 and the first source-drain metal layer 20 are both provided with the power line VDD, that is, a double-layer VDD routing arrangement is adopted to reduce the resistance of the power line, the power line VDD of the first source-drain metal layer 20 is a grid structure, the power line VDD of the second source-drain metal layer 40 may be designed for each column, the projection of the power line VDD of the first source-drain metal layer 20 in each sub-pixel is at least partially overlapped with the power line VDD of the second source-drain metal layer 40, so as to electrically connect the power line VDD of the first source-drain metal layer 20 and the power line VDD of the second source-drain metal layer 40.
Specifically, as shown in fig. 7, the second source-drain metal layer 40 and the first source-drain metal layer 20 are electrically connected through a first via V1 penetrating through the first planarization layer 50 and the passivation layer 150, the anode 30 is electrically connected through a second via V2 penetrating through the second planarization layer 60, and orthographic projections of the first via V1 and the second via V2 on the substrate do not overlap.
In summary, according to the display substrate provided by the embodiment of the invention, by changing the power line VDD pattern and the width design of the first source-drain metal layer 20, the overlapping area between the power line VDD and the anodes of the first sub-pixel R, the second sub-pixel G and the third sub-pixel B is reduced, and the probability that the second planarization layer 60 is punctured by a particle in the first sub-pixel R, the second sub-pixel G and the third sub-pixel B and the anode is shorted is relatively reduced, so that the bright spots related to the particle of the first source-drain metal layer 20 are reduced, and the yield of the vehicle-mounted OLED full-screen product is improved by 1.5%.
In practical implementation, the display substrate provided in the embodiment of the present invention further includes other functional film layers known to those skilled in the art, such as a touch layer, a cover plate, and the like located on a side of the inorganic encapsulation layer facing away from the substrate.
Based on the same inventive concept, the embodiment of the invention further provides a display panel, which comprises the display substrate provided by the embodiment of the invention. The display panel can be implemented in the embodiments of the display substrate, and repeated descriptions are omitted.
Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention. The display device may be a vehicle-mounted display screen, a notebook computer, a television, a tablet computer, a mobile phone, or a medical display device, and the like, which is not limited herein. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.
According to the display substrate, the display panel and the display device provided by the embodiment of the invention, the anode in the third sub-pixel is arranged to be not overlapped with the orthographic projection of the latticed power line on the substrate, so that particles (foreign matters, dust and the like) on the latticed power line cannot penetrate through the flat layer between the first source-drain metal layer and the anode and then directly contact with the anode (the power line is in short circuit with the anode), and the problem of poor bright spots when a screen is lightened at the rear end is avoided.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A display substrate, comprising: the pixel structure comprises a substrate, a first source drain metal layer and a plurality of sub-pixels, wherein the first source drain metal layer is positioned on one side of the substrate, and the plurality of sub-pixels are positioned on one side, away from the substrate, of the first source drain metal layer;
the plurality of sub-pixels are divided into a first sub-pixel, a second sub-pixel and a third sub-pixel, and the plurality of sub-pixels are divided into a plurality of sub-pixel columns; the plurality of sub-pixel columns include: a first sub-pixel column composed of the first sub-pixels and the second sub-pixels alternately arranged, and a second sub-pixel column composed of the third sub-pixels; the first sub-pixel columns and the second sub-pixel columns are alternately arranged;
the first source-drain metal layer comprises a grid-shaped power line, each sub-pixel comprises an anode, and the anode in the third sub-pixel is not overlapped with the orthographic projection of the power line on the substrate.
2. The display substrate of claim 1, further comprising: the second source-drain metal layer is positioned between the substrate base plate and the first source-drain metal layer, and the first flat layer is positioned between the first source-drain metal layer and the second source-drain metal layer;
the grid-shaped power line comprises a first grid arranged around the third sub-pixel, and the first grid is formed by sequentially connecting first grid lines arranged along the row direction and second grid lines arranged along the column direction;
the latticed power line further comprises a connecting part which is crossed with the second grid lines and is electrically connected with the second grid lines, the connecting part is located between the adjacent third sub-pixels, the connecting part and the second grid lines are of an integrated structure, and the end part, close to the third sub-pixels, of the connecting part is electrically connected with the second source drain metal layer through a through hole penetrating through the first flat layer.
3. The display substrate according to claim 2, wherein the width of the connection portion in the row direction is 2.7 μm to 3.3 μm, and the width of the second grid line in the column direction is 1.8 μm to 2.4 μm.
4. The display substrate according to claim 2, wherein the grid-shaped power supply line further comprises a second grid disposed around the first sub-pixel and the second sub-pixel, the second grid being formed by sequentially connecting a third grid line arranged in a row direction and a fourth grid line arranged in a column direction;
the orthographic projection of the third grid line on the substrate base plate is mutually overlapped with the orthographic projections of the first sub-pixel and the second sub-pixel on the substrate base plate, and the fourth grid line is positioned between the adjacent first sub-pixel and the adjacent second sub-pixel.
5. The display substrate according to claim 4, wherein the fourth grid line is electrically connected to a center position of the first grid line, the second grid line is electrically connected to a center position of the third grid line, and the first grid line and the third grid line are integrated structures extending in a column direction and have a common portion.
6. The display substrate of claim 5, wherein the third grid lines have a width in a row direction of 2.2 μm to 2.8 μm, and the fourth grid lines have a width in a column direction of 1.8 μm to 2.4 μm.
7. The display substrate according to any one of claims 1 to 6, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.
8. The display substrate according to any one of claims 1 to 6, further comprising a second planarization layer between the first source-drain metal layer and the anode.
9. A display panel comprising the display substrate according to any one of claims 1 to 8.
10. A display device characterized by comprising the display panel according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111217471.4A CN113964138A (en) | 2021-10-19 | 2021-10-19 | Display substrate, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111217471.4A CN113964138A (en) | 2021-10-19 | 2021-10-19 | Display substrate, display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023236095A1 (en) * | 2022-06-08 | 2023-12-14 | 京东方科技集团股份有限公司 | Display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023236095A1 (en) * | 2022-06-08 | 2023-12-14 | 京东方科技集团股份有限公司 | Display panel and display device |
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