CN113964122A - 集成电路 - Google Patents

集成电路 Download PDF

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Publication number
CN113964122A
CN113964122A CN202110812903.XA CN202110812903A CN113964122A CN 113964122 A CN113964122 A CN 113964122A CN 202110812903 A CN202110812903 A CN 202110812903A CN 113964122 A CN113964122 A CN 113964122A
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China
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layer
source
region
fin
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朱峯庆
李威养
林家彬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

集成电路，包含第二区的堆叠鳍式场效晶体管及第一区的全绕式栅极晶体管。堆叠鳍式场效晶体管包含两个第一源极/漏极部件、第一半导体层和第二半导体层的堆叠物、第一栅极介电层、第一栅极电极层以及横向设置于第二半导体层与两个第一源极/漏极部件之间的第一间隙壁部件，第一半导体层和第二半导体层包含不同材料。全绕式栅极晶体管包含两个第二源极/漏极部件、第三半导体层的堆叠物、环绕第三半导体层的第二栅极介电层、在第二栅极介电层上方的第二栅极电极层以及横向设置于第二栅极介电层与两个第二源极/漏极部件之间的第二间隙壁部件。

Description

集成电路
技术领域
本发明实施例是有关于半导体技术，且特别是有关于集成电路。
背景技术
电子产业对越来越小且更快的电子装置的需求不断增长，这些电子装置同时能够支持越来越多越趋复杂和精密的功能。为了实现这些需求，在集成电路(integratedcircuit，IC)产业中制造低成本、高效能和低功率的集成电路为持续的趋势。至今为止，通过缩小集成电路尺寸(例如将集成电路部件尺寸最小化)已很大程度上实现这些目标，进而改善生产效率并降低相关成本。然而，这些微缩化也已增加了集成电路制造过程的复杂性。因此，要实现集成电路装置及其效能的持续进步，就需要在集成电路制造过程和技术方面取得类似的进步。
近年来，已引入多栅极装置来改善栅极控制。已观察到多栅极装置增加栅极通道耦合，降低关态电流及/或减少短通道效应(short-channel effects，SCEs)。此类多栅极装置之一为全绕式栅极(gate-all-around，GAA)装置，全绕式栅极装置包含环绕通道区的栅极结构，以在多个面上提供到通道区的通道。范例的全绕式栅极装置包含垂直堆叠全绕式栅极(GAA)水平纳米线(nanowire，NW)和纳米片(nanosheet，NS)装置。全绕式栅极装置可实现集成电路技术的积极微缩化，维持栅极控制并减轻短通道效应，同时与传统集成电路制造过程无缝整合。然而，全绕式栅极装置中相邻线通道或片通道之间的垂直空间限制了栅极介电层的厚度。因此，全绕式栅极装置可能不适用于某些期望厚的栅极介电层的应用，例如输入/输出(input/output，I/O)功能。期望在此领域得到改善。
发明内容
在一些实施例中，提供集成电路，集成电路包含基底；堆叠鳍式场效晶体管，位于基底的第二区上，堆叠鳍式场效晶体管具有两个第一源极/漏极部件、交替堆叠且设置于两个第一源极/漏极部件之间的第一半导体层和第二半导体层的堆叠物、设置于第一半导体层和第二半导体层的堆叠物的顶部和侧壁上的第一栅极介电层、设置于第一栅极介电层上方的第一栅极电极层以及横向设置于第二半导体层的每一者与两个第一源极/漏极部件的每一者之间的第一间隙壁部件，其中第一半导体层和第二半导体层包含不同材料，且第一半导体层电性连接两个第一源极/漏极部件；以及全绕式栅极晶体管，位于基底的第一区上，全绕式栅极晶体管具有两个第二源极/漏极部件、电性连接两个第二源极/漏极部件的第三半导体层的堆叠物、环绕第三半导体层的每一者的第二栅极介电层、在第二栅极介电层上方的第二栅极电极层以及横向设置于第二栅极介电层与两个第二源极/漏极部件的每一者之间的第二间隙壁部件。
在一些其他实施例中，提供集成电路的制造方法，此方法提供结构，此结构具有基底、在集成电路的第二区中的基底上方的第一鳍、在集成电路的第一区中的基底上方的第二鳍、分别占据第一鳍和第二鳍的通道区的第一牺牲栅极堆叠物和第二牺牲栅极堆叠物以及分别在第一牺牲栅极堆叠物和第二牺牲栅极堆叠物的侧壁上的第一栅极间隙壁和第二栅极间隙壁，其中第一鳍和第二鳍各包含第一半导体材料的第一层及不同于第一半导体材料的第二半导体材料的第二层，其中第一层和第二层交替堆叠于基底上方；蚀刻相邻于第一栅极间隙壁的第一鳍，以形成第一源极/漏极沟槽；蚀刻相邻于第二栅极间隙壁的第二鳍，以形成第二源极/漏极沟槽；将暴露于第一源极/漏极沟槽和第二源极/漏极沟槽中的第二层部分凹陷，以在第一鳍和第二鳍的第一层的相邻层之间形成间隙；以及在第一鳍和第二鳍的间隙中形成内部间隙壁部件。
在另外一些实施例中，提供集成电路的制造方法，此方法提供结构，此结构具有基底、在集成电路的第二区中的基底上方的第一鳍、在集成电路的第一区中的基底上方的第二鳍、分别在第一鳍和第二鳍上方的第一牺牲栅极堆叠物和第二牺牲栅极堆叠物以及分别在第一牺牲栅极堆叠物和第二牺牲栅极堆叠物的侧壁上的第一栅极间隙壁和第二栅极间隙壁，其中第一鳍和第二鳍各包含第一半导体材料的第一层及不同于第一半导体材料的第二半导体材料的第二层，其中第一层和第二层交替堆叠于基底上方；蚀刻第一鳍和第二鳍，以在相邻于第一栅极间隙壁处形成第一源极/漏极沟槽，并在相邻于第二栅极间隙壁处形成第二源极/漏极沟槽；将暴露于第一源极/漏极沟槽和第二源极/漏极沟槽中的第二层部分凹陷，以在第一鳍和第二鳍的第一层的相邻层之间形成间隙；在第一鳍和第二鳍的间隙中形成内部间隙壁部件；以及在形成内部间隙壁部件之后，在第一源极/漏极沟槽和第二源极/漏极沟槽中分别外延成长第一源极/漏极部件和第二源极/漏极部件。
附图说明
根据以下的详细说明并配合所附图式可以更加理解本发明实施例。应注意的是，根据本产业的标准惯例，图示中的各种部件(feature)并未必按照比例绘制。事实上，可能任意的放大或缩小各种部件的尺寸，以做清楚的说明。
图1A和图1B为依据本发明实施例的各方面，制造多栅极装置的方法的流程图。
图2A为依据本发明实施例的各方面，在图1A和图1B的方法的制造阶段，多栅极装置的一部分的概略透视图。
图2B、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13和图14为依据本发明实施例的各方面，在与图1A和图1B的方法相关联的各个制造阶段，沿图2A的线A-A的多栅极装置的一部分的概略剖面示意图。
图15为依据本发明实施例的各方面，在与图1A和图1B的方法相关联的制造阶段，沿图2A的线B-B的多栅极装置的一部分的概略剖面示意图。
其中，附图标记说明如下：
10：方法
12，14，16，18，20，22，24，26，28，30，32，34，36，38：操作
100：多栅极装置
100A：第一区
100B：第二区
102：基底
103：鳍
103a，103b：半导体层
103c：鳍基部
104：隔离结构
105：源极/漏极沟槽
106：牺牲栅极堆叠物
107：沟槽
108，208：源极/漏极部件
110：间隙
112：内部间隙壁部件
116：接触蚀刻停止层
118：层间介电层
124：栅极间隙壁
125，225：栅极沟槽
126：牺牲栅极介电层
127：牺牲栅极电极层
128：硬遮罩层
131，231：栅极介电层
132，232：功函数金属层
133，233：金属填充层
135，235：高介电常数金属栅极堆叠物
190，192：蚀刻遮罩
T1，T2：厚度
具体实施方式
要了解的是以下的公开内容提供许多不同的实施例或范例，以实施提供的主体的不同部件。以下叙述各个构件及其排列方式的特定范例，以求简化公开内容的说明。当然，这些仅为范例并非用以限定本发明。例如，以下的公开内容叙述了将一第一部件形成于一第二部件之上或上方，即表示其包含了所形成的上述第一部件与上述第二部件是直接接触的实施例，亦包含了尚可将附加的部件形成于上述第一部件与上述第二部件之间，而使上述第一部件与上述第二部件可能未直接接触的实施例。此外，公开内容中不同范例可能使用重复的参考符号及/或用字。这些重复符号或用字是为了简化与清晰的目的，并非用以限定各个实施例及/或所述外观结构之间的关系。
再者，为了方便描述图式中一元件或部件与另一(复数)元件或(复数)部件的关系，可使用空间相关用语，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及类似的用语。除了图式所绘示的方位之外，空间相关用语也涵盖装置在使用或操作中的不同方位。所述装置也可被另外定位(例如，旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。再者，当用“大约”、“近似”及类似术语描述数字或数字范围时，除非另有说明，否则依据本发明所属技术领域中具通常知识者所知，此术语目的在涵盖在所描述的数字的特定变化内(例如+/-10％或其他变化)的数字。举例来说，术语“约5nm”涵盖了尺寸范围从4.5nm至5.5nm、从4.0nm至5.0nm等等。
本发明实施例一般有关于半导体装置及其制造方法，且特别有关于在集成电路(IC)的第一区中形成全绕式栅极(GAA)装置，并在集成电路的第二区中形成堆叠鳍式场效晶体管装置。举例来说，全绕式栅极装置可用于集成电路的第一区中的低功耗电路及/或高速电路，且堆叠鳍式场效晶体管装置可用于集成电路的第二区中的输入输出电路、静电放电(electrostatic discharge，ESD)电路及/或其他电路。在一实施例中，堆叠鳍式场效晶体管装置具有比全绕式栅极装置更厚的栅极介电质。在另一实施例中，堆叠鳍式场效晶体管装置具有比全绕式栅极装置更大的栅极长度。每个全绕式栅极装置包含一对源极/漏极(source/drain，S/D)部件、连接源极/漏极部件的多个垂直堆叠水平定向的通道以及环绕每个通道的高介电常数金属栅极。每个堆叠鳍式场效晶体管装置包含一对源极/漏极(S/D)部件、堆叠物鳍结构以及设置于堆叠物鳍结构的顶表面和侧壁表面上的高介电常数金属栅极。堆叠物鳍结构包含多个交替堆叠的第一半导体层和多个第二半导体层。每个全绕式栅极装置更包含水平设置于高介电常数金属栅极与一对源极/漏极部件之间的内部间隙壁部件。每个堆叠鳍式场效晶体管装置更包含水平设置于第二半导体层与一对源极/漏极部件之间的内部间隙壁部件。全绕式栅极装置和堆叠鳍式场效晶体管装置中的内部间隙壁部件可通过相同制程形成，且可具有相同材料，以简化制造流程。
图1A和图1B为依据本发明实施例的各方面，制造多栅极装置100的方法10的流程图。在一些实施例中，多栅极装置100包含集成电路的第一区100A中的全绕式栅极晶体管(全绕式栅极装置)以及集成电路的第二区100B中的鳍式场效晶体管(或鳍式场效晶体管装置)。举例来说，第一区100A(例如集成电路的核心区域)包含进行逻辑功能的晶体管、用于存储的晶体管(例如静态随机存取存储器(static random access memory，SRAM))等等；而第二区100B(例如集成电路)的输入输出区)包含输入/输出晶体管、静电放电(ESD)晶体管、高压晶体管等等。图2A为依据本发明实施例的各方面，在图1A和图1B的方法10的制造阶段，多栅极装置100的一部分的概略透视图。图2B、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13和图14为依据本发明实施例的各方面，在与图1A和图1B的方法10相关联的各个制造阶段，沿图2A的线A-A的多栅极装置100的一部分的概略剖面示意图。图15为依据本发明实施例的各方面，在与图1A和图1B的方法10相关联的制造阶段，沿图2A的线B-B的多栅极装置100的一部分的概略剖面示意图。方法10包含操作12到操作38。本发明实施例考虑了额外的加工。可在方法10之前、期间及之后提供额外的步骤，且对于方法10的额外实施例，可移动、取代或消除操作12到操作38的其中一些。
多栅极装置100可被包含在微处理器、存储器及/或其他集成电路装置中。在一些实施例中，多栅极装置100为集成电路芯片的一部分、系统单芯片(system on chip，SoC)或前述的一部分，其包含各种被动和主动微电子装置，例如电阻、电容、电感、二极管、p型场效晶体管(p-type FETs，PFETs)、n型场效晶体管(n-type FETs，NFETs)、金属氧化物半导体场效晶体管(metal-oxide-semiconductor FETs，MOSFETs)、鳍式场效晶体管、纳米片场效晶体管、纳米线场效晶体管、其他类型的多栅极场效晶体管、互补式金属氧化物半导体(complementary metal-oxide semiconductor，CMOS)晶体管、双极性接面晶体管(bipolarjunction transistors，BJTs)、横向扩散金属氧化物半导体(laterally diffused MOS，LDMOS)晶体管、高压晶体管、高频晶体管、其他合适的组件或前述的组合。在一些实施例中，多栅极装置100被包含在存储器装置中，例如静态随机存取存储器(SRAM)、非易失性随机存取存储器(non-volatile random-access memory，NVRAM)、快闪存储器、可电气抹除可编程只读存储器(electrically erasable programmable read only memory，EEPROM)、电性可编程只读存储器(electrically programmable read-only memory，EPROM)、其他合适的存储器类型或前述的组合。为了清楚起见，已将图2A-图15简化，以更好地理解本发明实施例的发明概念。可在多栅极装置100中添加额外的部件，且在多栅极装置100的其他实施例中，可取代、修改或消除以下所描述的一些部件。以下结合方法10的实施例描述多栅极装置100的制造。
在操作12，方法10(图1A)提供多栅极装置100的初始结构。请参照图2A-2B，多栅极装置100包含基底102。在第一区100A和第二区100B中，多栅极装置100包含从基底102延伸的鳍103、在基底102上方并将鳍103的下部隔开的隔离结构104、在鳍103和隔离结构104上方的牺牲栅极堆叠物106以及在牺牲栅极堆叠物106的侧壁上以及在鳍103的顶表面和侧壁表面上的栅极间隙壁124。每个牺牲栅极堆叠物106包含牺牲栅极介电层126、牺牲栅极电极层127和一个或多个硬遮罩层128。每个鳍103包含在在鳍基部103c上方的半导体层103a和103b的堆叠物。半导体层103a和103b的堆叠物在隔离结构104之上。鳍103的源极/漏极区暴露于牺牲栅极堆叠物106之间的沟槽107中。在一些实施例中，第一区100A中的鳍103和牺牲栅极堆叠物106可具有与第二区100B中的鳍103和牺牲栅极堆叠物106不同的尺寸。举例来说，在一些实施例中，在第二区100B中鳍103沿y方向的宽度可大于在第一区100A中鳍103沿y方向的宽度。举例来说，在一些实施例中，在第二区100B中牺牲栅极堆叠物106沿x方向的宽度可大于在第一区100A中牺牲栅极堆叠物106沿x方向的宽度。举例来说，在一些实施例中，在第二区100B中鳍103的间距及/或牺牲栅极堆叠物106的间距可大于在第一区100A中鳍103的间距及/或牺牲栅极堆叠物106的间距。以下进一步讨论多栅极装置100的各种组件。
在本实施例中，基底102包含硅。举例来说，基底102为硅晶圆。替代地或额外地，基底102包含其他元素半导体(例如锗)、化合物半导体(包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟)、合金半导体(例如硅锗(SiGe)、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP)或前述的组合。或者，基底102为绝缘层上覆半导体基底，例如绝缘层上覆硅(silicon-on-insulator，SOI)基底、绝缘层上覆硅锗(silicon germanium-on-insulator，SGOI)基底或绝缘层上覆锗(germanium-on-insulator，GOI)基底。缘层上覆半导体基底可通过使用植氧分离(separation by implantation of oxygen，SIMOX)、晶圆接合及/或其他合适的方法制造。取决于多栅极装置100的设计需求，基底102可包含各种掺杂区。举例来说，基底102可包含配置给n型全绕式栅极晶体管和n型堆叠物鳍式场效晶体管的p型掺杂区以及配置给p型全绕式栅极晶体管和p型堆叠物鳍式场效晶体管的n型掺杂区。p型掺杂区掺杂p型掺杂物，例如硼、铟、其他p型掺杂物或前述的组合。n型掺杂区掺杂n型掺杂物，例如磷、砷、其他n型掺杂物或前述的组合。在一些实施例中，基底102包含由p型掺杂物和n型掺杂物的组合形成的掺杂区。各种掺杂区可直接形成于基底102上及/或基底102中，例如提供p型井结构、n型井结构、双井结构、凸起结构或前述的组合。可进行离子布植制程、扩散制程及/或其他合适的掺杂制程，以形成各种掺杂区。
在本实施例中，每个鳍103包含鳍基部103c以及从鳍基部103c以交错或交替的配置垂直排列(例如沿z方向)的半导体层103a和半导体层103b的堆叠物。在一实施例中，鳍基部103c包含与基底102相同的半导体材料，且半导体层103a和103b以交错或交替的配置逐层从鳍基部103c外延成长，直到到达所期望数量的半导体层。在所示的实施例中，每个鳍103包含三个半导体层103a和三个半导体层103b。然而，例如取决于多栅极装置100的所期望通道数量，本公开考虑了每个鳍103包含更多或更少的半导体层的实施例。举例来说，在一些实施例中，每个鳍103可包含两个至十个半导体层103a以及两个至十个半导体层103b。
半导体层103a的组成不同于半导体层103b的组成，以实现在后续加工期间的蚀刻选择性及/或不同的氧化速率。举例来说，半导体层103a和103b可包含不同的材料、不同的组成原子百分比、不同的组成重量百分比、及/或不同的特性，以在蚀刻制程期间实现所期望的蚀刻选择性，例如使用蚀刻制程，以在多栅极装置100的通道区中形成悬置的通道层。在本实施例中，半导体层103a包含硅，且半导体层103b包含硅锗，硅锗具有与硅不同的蚀刻选择性。在一些实施例中，半导体层103a和103b可包含相同材料，但是具有不同的组成原子百分比，以实现蚀刻选择性及/或不同的氧化速率。举例来说，半导体层103a和103b可包含硅锗，其中半导体层103a具有第一硅原子百分比及/或第一锗原子百分比，且半导体层103b具有不同的第二硅原子百分比及/或不同的第二锗原子百分比。本发明实施例考虑了半导体层103a和103b包含可提供所期望的蚀刻选择性、所期望的氧化速率差异及/或所期望的效能特性(例如最大化电流的材料)的半导体材料的任何组合，包含本文所公开的任何半导体材料。
在一些实施例中，每个半导体层103a的厚度为约1nm至约10nm，每个半导体层103b的厚度为约1nm至约10nm，且两者的厚度可相同或不同。在一实施例中，在第一区100A和第二区100B中在相同堆叠物水平高度的半导体层103a(例如从鳍基部103c的表面算起的第n个半导体层103a)通过相同制程形成，且具有相同厚度和相同材料，且在第一区100A和第二区100B中在相同堆叠物水平高度的半导体层103b(例如从鳍基部103c的表面算起的第n个半导体层103b)通过相同制程形成，且具有相同厚度和相同材料。
鳍103可通过合适的方法从半导体层103a和103b的堆叠物和基底102图案化。举例来说，鳍103可通过合适的制程(包含双重图案化或多重图案化制程)来图案化。一般来说，双重图案化或多重图案化制程结合了光微影和自对准制程，以创造具有较小间距的图案，举例来说，此图案具有比使用单一直接光微影制程可获得的间距更小的图案。举例来说，在一实施例中，牺牲层形成于基底上方并通过使用光微影制程图案化。间隔物通过使用自对准制程形成于图案化牺牲层旁边。接着，移除牺牲层，且可接着使用剩下的间隔物或心轴作为用以将鳍103图案化的遮罩元件。举例来说，遮罩元件可用于将基底102上方或基底102中的半导体层蚀刻凹口，在基底102上保留鳍103。蚀刻制程可包含干蚀刻、湿蚀刻、反应性离子蚀刻(reactive ion etching，RIE)及/或其他合适的制程。举例来说，干蚀刻制程可使用含氧气体、含氟气体(例如CF4、SF6、CH2F2、CHF3及/或C2H6)、含氯气体(例如Cl2、CHCl3、CCl4及/或BCl3)、含溴气体(例如HBr及/或CHBr3)、含碘气体、其他合适的气体及/或等离子体及/或前述的组合。举例来说，湿蚀刻制程可包括在稀释氢氟酸(diluted hydrofluoric acid，DHF)、氢氧化钾(potassium hydroxide，KOH)溶液、含氢氟酸(hydrofluoric acid，HF)、硝酸(HNO3)及/或醋酸(CH3COOH)的溶液或其他合适的湿蚀刻剂中蚀刻。
隔离结构104可包含氧化硅(SiO2)、氮化硅(Si3N4-)、氮氧化硅(SiON)、氟掺杂硅酸盐玻璃(fluorine-doped silicate glass，FSG)、低介电常数介电材料及/或其他合适的绝缘材料。在一实施例中，通过在基底102中或基底102上方蚀刻沟槽(例如作为形成鳍103的制程的一部分)，以绝缘材料填充沟槽，对绝缘材料进行化学机械平坦化(chemicalmechanical planarization，CMP)制程及/或回蚀刻制程，保留剩下的绝缘材料作为隔离结构104。其他类型的隔离结构也可为合适的，例如场氧化物和硅局部氧化(LOCal Oxidationof Silicon，LOCOS)。隔离结构104可包含多层结构，例如在基底102和鳍103的表面上具有一个或多个衬垫层(例如氮化硅)以及在一个或多个衬垫层上方的主要隔离层(例如二氧化硅)。
牺牲栅极介电层126可包含介电材料，例如氧化硅(例如(SiO2)或氮氧化硅(SiON)，且可通过化学氧化、热氧化、原子层沉积(atomic layer deposition，ALD)、化学气相沉积(chemical vapor deposition，CVD)及/或其他合适的方法形成。牺牲栅极电极层127可包含多晶硅(poly-crystalline silicon，poly-Si)或其他材料，且可通过合适的沉积制程形成，例如低压化学气相沉积(low-pressure CVD，LPCVD)和等离子体辅助化学气相沉积(plasma enhanced CVD，PECVD)。硬遮罩层128可包含氮化硅、氧化硅及/或其他合适的介电材料，且可通过化学气相沉积或其他合适的方法形成。牺牲栅极介电层126、牺牲栅极电极层127和硬遮罩层128可通过光微影和蚀刻制程来图案化。栅极间隙壁124可包括介电材料，例如氧化硅、氮化硅、氮氧化硅、碳化硅、其他介电材料或前述的组合，且可包括一层或多层材料。栅极间隙壁124可通过在隔离结构104、鳍103和牺牲栅极堆叠物106上方沉积间隙壁材料作为保护层来形成。接着，通过非等向性蚀刻制程蚀刻间隙壁材料，以暴露隔离结构104、硬遮罩层128和鳍103的顶表面。间隙壁材料在牺牲栅极堆叠物106的侧壁上的部分变成栅极间隙壁124。相邻的栅极间隙壁124提供开口107，开口107暴露鳍103在多栅极装置100的源极/漏极区中的部分。
在操作14，方法10(图1A)蚀刻鳍103，以在第一区100A和第二区100B中形成源极/漏极沟槽105(图3)。操作14可包含一个或多个光微影制程和蚀刻制程。举例来说，光微影制程可形成遮罩元件，此遮罩元件覆盖多栅极装置100将不被蚀刻的区域。遮罩元件提供开口，通过这些开口蚀刻鳍103。举例来说，操作14可通过使用遮罩元件分别在第一区100A和第二区100B中蚀刻源极/漏极沟槽105。举另一例来说，操作14可通过使用遮罩元件分别在第一区100A中的p型金属氧化物半导体(p-type MOS，PMOS)区和n型金属氧化物半导体(n-type MOS，NMOS)区中蚀刻源极/漏极沟槽105，并通过使用遮罩元件分别在第二区100B中的p型金属氧化物半导体区和n型金属氧化物半导体区中蚀刻源极/漏极沟槽105。在一实施例中，操作14同时在第一区100A和第二区100B中的p型金属氧化物半导体区中蚀刻源极/漏极沟槽105，而遮蔽第一区100A和第二区100B中的n型金属氧化物半导体区，并同时在第一区100A和第二区100B中的n型金属氧化物半导体区中蚀刻源极/漏极沟槽105，而遮蔽第一区100A和第二区100B中的p型金属氧化物半导体区。在一实施例中，操作14同时在第一区100A和第二区100B中的p型金属氧化物半导体区和n型金属氧化物半导体区中蚀刻源极/漏极沟槽105，而遮蔽多栅极装置100的其他区域。在一实施例中，如之前所讨论的，蚀刻制程可包含干蚀刻、湿蚀刻、反应性离子蚀刻(RIE)及/或其他合适的制程。再者，调整蚀刻制程为对鳍103的材料有选择性，而不蚀刻(或最小化蚀刻)栅极间隙壁124、硬遮罩层128和隔离结构104。由于蚀刻制程的缘故，半导体层103a和103b的各个表面暴露于每个源极/漏极沟槽105中。在一些实施例中，源极/漏极沟槽105可延伸至鳍基部103c中。
在操作16，方法10(图1A)将第一区100A和第二区100B中的源极/漏极沟槽105中的半导体层103b凹陷，进而在每两个相邻的半导体层103a之间以及在最底部半导体层103a与鳍基部103c之间形成间隙110，如图4所示。在各种实施例中，可蚀刻间隙110为矩形、圆形、梯形、漏斗形或其他形状。在各种实施例中，操作16应用调整为对半导体层103b的材料有选择性的蚀刻制程，而最小化蚀刻(至不蚀刻)栅极间隙壁124、硬遮罩层128、隔离结构和半导体层103a。可调整各种蚀刻参数，以实现半导体层103b的选择性蚀刻，例如蚀刻剂组成、蚀刻温度、蚀刻溶液浓度、蚀刻时间、蚀刻压力、电源功率、射频偏压电压、射频偏压功率、蚀刻剂流量、其他合适的蚀刻参数或前述的组合。在一实施例中，操作16使用含氟气体(例如HF、F2、NF3、CF4、SF6、CH2F2、CHF3及/或C2F6)对半导体层103b进行等向性干蚀刻制程(例如表面气体/自由基反应制程)，以选择性蚀刻包含硅锗的半导体层103b。在一些实施例中，可调整含氟气体对含氧气体(例如O2)的比值、蚀刻温度及/或射频功率，以选择性蚀刻硅锗或硅。在一些实施例中，在完成蚀刻制程之后，操作16可更对暴露于源极/漏极沟槽105的表面应用清洁制程。清洁制程可包含对各个表面应用稀释氢氟酸(dHF)。
在操作18，方法10(图1A)在第一区100A和第二区100B中形成内部间隙壁部件112，如图5所示。这可涉及多个沉积和蚀刻制程。在一实施例中，操作18沿多栅极装置100由于操作16而暴露的各个表面(例如牺牲栅极堆叠物106的顶表面、栅极间隙壁124的侧壁以及半导体层103a和103b暴露于源极/漏极沟槽105中的表面)沉积介电层，并接着回蚀刻介电层，以保留介电层在间隙110中的部分作为内部间隙壁部件112。在各种实施例中，介电层可包含不同于半导体层103b和栅极间隙壁124的材料，以在后续蚀刻制程期间实现所期望的蚀刻选择性。在一些实施例中，介电层包含介电材料，介电材料包含硅、氧、碳、氮、其他合适的材料或前述的组合(例如氧化硅、氮化硅、氮氧化硅、碳化硅或氮碳氧化硅)。在一些实施例中，介电层包含低介电常数介电材料及/或空气间隙。范例的低介电常数介电材料包含氟掺杂硅酸盐玻璃、碳掺杂氧化硅、干凝胶、气凝胶、非晶氟化碳、聚对二甲苯、二苯并环丁烯(bis-benzocyclobutenes，BCB)、聚酰亚胺、其他低介电常数介电材料或前述的组合。介电层可通过使用原子层沉积、化学气相沉积或其他合适的方法沉积。在各种实施例中，回蚀刻制程可应用调整为对介电层的材料有选择性的干蚀刻、湿蚀刻、反应性离子蚀刻，而最小化蚀刻(至不蚀刻)半导体层103a、牺牲栅极堆叠物106和栅极间隙壁124。举例来说，回蚀刻制程可应用等向性湿蚀刻制程。
在操作20，方法10(图1A)在第一区100A中外延成长源极/漏极(S/D)部件108，并在第二区100B中外延成长源极/漏极部件208，如图6所示。源极/漏极部件108和208从半导体层103a和鳍基部103c(或基底102，在一些实施例中)暴露于源极/漏极沟槽105中的表面成长。内部间隙壁部件112将源极/漏极部件108和208与半导体层103b隔开。在一实施例中，操作20可遮蔽第一区100A和第二区100B中的p型金属氧化物半导体区，而在第一区100A和第二区100B中的n型金属氧化物半导体区外延成长源极/漏极部件108和208。再者，操作20可遮蔽第一区100A和第二区100B中的n型金属氧化物半导体区，而在第一区100A和第二区100B中的p型金属氧化物半导体区外延成长源极/漏极部件108和208。在此实施例中，操作20使用两个遮罩，一个用于p型金属氧化物半导体区，另一个用于n型金属氧化物半导体区。在另一实施例中，操作20使用四个遮罩，使得第一区100A中的p型源极/漏极部件108、第一区100A中的n型源极/漏极部件108、第二区100B中的p型源极/漏极部件208和第二区100B中的n型源极/漏极部件208个别成长。在这些实施例中，可个别调整源极/漏极部件108和208的性质用于核心功能(例如逻辑、记忆等)或输入输出功能(例如输入/输出、静电放电、高电压等)。
外延制程可使用化学气相沉积(CVD)技术(例如气相外延及/或超高真空化学气相沉积)、分子束外延、其他合适的外延成长制程或前述的组合。外延制程可使用气体及/或液体前驱物，这些前驱物与半导体层103a、鳍基部103c和基底102的组成反应。方法10也可将源极/漏极部件108和208掺杂n型掺杂物及/或p型掺杂物。在一些实施例中，对于n型晶体管，源极/漏极部件108和208包含硅，且可掺杂碳、磷、砷、其他n型掺杂物或前述的组合(举例来说，形成Si:C外延源极/漏极部件、Si:P外延源极/漏极部件或Si:C:P外延源极/漏极部件)。在一些实施例中，对于p型晶体管，源极/漏极部件108和208包含硅锗或锗，且可掺杂硼、其他p型掺杂物或前述的组合(举例来说，形成Si:Ge:B外延源极/漏极部件)。在一些实施例中，源极/漏极部件108和208可包含多个外延半导体层，其中多个外延半导体层具有不同水平的掺杂物密度。再者，掺杂可为原位(即在沉积期间通过将杂质加入外延制程的源材料来掺杂)或非原位(例如在沉积制程之后通过离子布植制程来掺杂)。在一些实施例中，进行退火制程(例如快速热退火(rapid thermal anneal，RTA)及/或激光退火)，以活化源极/漏极部件108和208中的掺杂物。
在操作22，方法10(图1A)在多栅极装置100上方形成接触蚀刻停止层(contactetch stop layer，CESL)116和层间介电(inter-level dielectric，ILD)层118，例如图7所示。在本实施例中，在此制造阶段，已形成第一区100A和第二区100B中用于p型金属氧化物半导体区和n型金属氧化物半导体区的源极/漏极部件108和208。如图7所示，接触蚀刻停止层116形成于源极/漏极部件108和208、牺牲栅极堆叠物106和栅极间隙壁124的侧壁上方。层间介电层118沉积于接触蚀刻停止层116上方。接触蚀刻停止层116可包括氮化硅、氮氧化硅、有着氧(O)或碳(C)元素的氮化硅及/或其他材料，且可通过化学气相沉积、物理气相沉积、原子层沉积或其他合适方法形成。在一实施例中，接触蚀刻停止层116沿上述的各个表面沉积大致一致的厚度。层间介电层118可包括四乙氧基硅烷(tetraethylorthosilicate，TEOS)形成的氧化物、未掺杂硅酸盐玻璃或掺杂氧化硅，例如硼磷硅酸盐玻璃(borophosphosilicate glass，BPSG)、氟掺杂硅酸盐玻璃(FSG)、磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼掺杂硅玻璃(boron doped silicon glass，BSG)及/或其他合适的介电材料。层间介电层118可通过等离子体辅助化学气相沉积(PECVD)、可流动化学气相沉积(flowable CVD，FCVD)或其他合适的方法形成。层间介电层118填充在牺牲栅极堆叠物106之间以及对应的源极/漏极部件108和208之间的各个沟槽。在一实施例中，在沉积层间介电层118之后，操作22可对多栅极装置100进行化学机械平坦化，以暴露牺牲栅极堆叠物106的顶表面。
在操作24，方法10(图1B)形成蚀刻遮罩190，蚀刻遮罩190覆盖第二区100B，并暴露第一区100A，例如图8所示。蚀刻遮罩190包含不同于牺牲栅极堆叠物106的材料，以在后续移除牺牲栅极堆叠物106的期间实现蚀刻选择性。举例来说，蚀刻遮罩190可包含光阻材料(且因此可被作为图案化阻剂层或图案化光阻层)。在一些实施例中，蚀刻遮罩190具有多层结构，例如设置于抗反射涂布(anti-reflective coating，ARC)层及/或硬遮罩层上方的光阻层。本发明实施例考虑了用于蚀刻遮罩190的其他材料，只要能够在移除牺牲栅极堆叠物106的期间实现蚀刻选择性。在一些实施例中，操作24包含微影制程，微影制程包含在多栅极装置100上方形成光阻层(例如通过旋涂)、进行曝光前烘烤制程、使用光罩进行曝光制程、进行曝光后烘烤制程以及在显影溶液中将曝光的光阻层显影。在显影之后，图案化光阻层(例如图案化的蚀刻遮罩190)包含对应光罩的光阻图案，其中图案化光阻层覆盖第二区100B并暴露第一区100A。或者，可通过其他方法进行或取代曝光制程，例如无遮罩微影、电子束写入、离子束写入或前述的组合。
在操作26，方法10(图1B)从第一区100A移除牺牲栅极堆叠物106，进而在第一区100A中形成栅极沟槽125，例如图9所示。在一实施例中，操作26进行一个或多个蚀刻制程，以移除包含硬遮罩层128、牺牲栅极电极层127和牺牲栅极介电层126的牺牲栅极堆叠物106。蚀刻制程可包含干蚀刻、湿蚀刻、反应性离子蚀刻、前述的组合或其他合适的蚀刻制程。将蚀刻制程调整为对牺牲栅极堆叠物106的材料有选择性，而不蚀刻(或最小化蚀刻)层间介电层118、接触蚀刻停止层116、栅极间隙壁124和鳍103(包含半导体层103a和103b)。如图9所示，蚀刻制程使得在两侧的栅极间隙壁124之间形成栅极沟槽125。栅极沟槽125暴露鳍103的通道区。
在操作28，方法10(图1B)选择性移除第一区100A中栅极沟槽125中的半导体层103b，例如图10所示。在一些实施例中，此制程也被称为通道释放制程。在图10所示的实施例中，蚀刻制程选择性蚀刻半导体层103b，而最小化蚀刻(至不蚀刻)半导体层103a，且在一些实施例中，最小化蚀刻(至不蚀刻)栅极间隙壁124及/或内部间隙壁部件112。可调整各种蚀刻参数，以实现半导体层103b的选择性蚀刻，例如蚀刻剂组成、蚀刻温度、蚀刻溶液浓度、蚀刻时间、蚀刻压力、电源功率、射频偏压电压、射频偏压功率、蚀刻剂流量、其他合适的蚀刻参数或前述的组合。蚀刻制程可为干蚀刻制程、湿蚀刻制程、其他合适的蚀刻制程或前述的组合。在一些实施例中，干蚀刻制程(例如表面气体/自由基反应制程)使用含氟气体(例如HF、F2、NF3、CF4、SF6、CH2F2、CHF3及/或C2F6)，以选择性蚀刻包含硅锗的半导体层103b。在一些实施例中，可调整含氟气体对含氧气体(例如O2)的比值、蚀刻温度及/或射频功率，以选择性蚀刻硅锗或硅。在一些实施例中，湿蚀刻制程使用包含氢氧化铵(NH4OH)和水(H2O)的蚀刻溶液，以选择性蚀刻半导体层103b。在一些实施例中，化学气相蚀刻制程使用氢氯酸(HCl)选择性蚀刻半导体层103b。由于蚀刻选择性的缘故，内部间隙壁部件112保护源极/漏极部件108免受蚀刻制程影响。
由于操作28的缘故，半导体层103a悬置于鳍基部103c和基底102上方，并连接每个栅极沟槽125两侧上的源极/漏极部件108。在一些实施例中，在移除半导体层103b之后，可选择性进行蚀刻制程，以修改半导体层103a的轮廓，以实现所期望的尺寸及/或所期望的形状(例如圆柱形(例如纳米线)、矩形(逆如纳米棒)、片状(例如纳米片)等)。取决于多栅极装置100的设计需求，本公开更考虑了半导体层103a具有次纳米的尺寸。在一实施例中，由于通道释放制程的缘故(以及选择性进一步的蚀刻制程)，在相同堆叠物水平高度处，第一区100A中的半导体层103a的厚度T2变得小于第二区100B中的半导体层103a的厚度T1。
在操作30，方法10(图1B)在栅极沟槽125中形成高介电常数金属栅极堆叠物(high-k metal gate stacks，HKMG)135围绕每个半导体层103a，例如图11所示。图15的左图进一步显示高介电常数金属栅极堆叠物135围绕每个半导体层103a。在一实施例中，高介电常数金属栅极堆叠物135包含栅极介电层131、在栅极介电层131上方的功函数金属层132以及在功函数金属层132上方的金属填充层133。栅极介电层131可包含高介电常数介电材料，例如氧化铪、氧化锆、氧化镧、氧化钛、氧化钇和钛酸锶。栅极介电层131可通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)及/或其他合适的方法形成。在一些实施例中，高介电常数金属栅极堆叠物135更包含在栅极介电层131与半导体层103a之间的界面层。界面层可包含氧化硅、氮氧化硅或其他合适的材料。在一些实施例中，取决于全绕式栅极晶体管的类型，功函数金属层132包含n型或p型功函数层。举例来说，n型功函数层可包括足够小的有效功函数的金属，例如钛、铝、碳化钽、氮碳化钽、氮化钽硅或前述的组合。举例来说，p型功函数层可包括足够大的有效功函数的金属，例如氮化钛、氮化钽、钌、钼、钨、铂或前述的组合。功函数金属层132可通过化学气相沉积、物理气相沉积、原子层沉积及/或其他合适的制程形成。在一些实施例中，金属填充层133可包含铝、钨、钴、铜及/或其他合适的材料，且可通过化学气相沉积、物理气相沉积、电镀及/或其他合适的制程形成。高介电常数金属栅极堆叠物135通过栅极间隙壁124和内部间隙壁部件112与源极/漏极部件108隔开。在一些实施例中，在栅极介电层131与功函数金属层132之间可具有额外层，及/或功函数金属层132围绕额外层。在高介电常数金属栅极堆叠物135包含上述的界面层的实施例中，界面层设置于栅极介电层131与内部间隙壁部件112之间，即界面层直接接触内部间隙壁部件112以及半导体层103a的两相邻层。在高介电常数金属栅极堆叠物135不包含界面层的一实施例中，栅极介电层131设置为直接接触内部间隙壁部件112。
在操作32，方法10(图1B)从第二区100B移除蚀刻遮罩190，并形成蚀刻遮罩192，蚀刻遮罩192覆盖第一区100A，并暴露第二区100B，例如图12所示。蚀刻遮罩192可包含相同或相似于蚀刻遮罩190的材料，且可通过相同或相似于形成蚀刻遮罩190的方法来形成。
在操作34，方法10(图1B)从第二区100B移除牺牲栅极堆叠物106，进而在第二区100B中形成栅极沟槽225，例如图13所示。操作34的各方面相同或大致相似于操作26的各方面，为了简单起见，不赘述于此。
在操作36，方法10(图1B)在栅极沟槽225中形成高介电常数金属栅极堆叠物(HKMG)235，例如图14所示。图15的右图进一步显示高介电常数金属栅极堆叠物235设置于鳍103的顶部和侧壁表面上，每个鳍103包含半导体层130a和103b。由于半导体层103b通过内部间隙壁部件112与源极/漏极部件208隔开，因此第二区100B的装置中的主要传导通道为半导体层103a。在一些实施例中，相较于第二区100B不包含内部间隙壁部件112的配置，此配置提供更一致的装置效能(例如临界电压、饱和电流等)。在一些实施例中，第二区100B中的装置可被视为多个彼此堆叠且通过高介电常数金属栅极堆叠物235控制的鳍式场效晶体管。由于第二区100B中的装置不像第一区100A中的装置经过通道释放制程，因此当在相同堆叠物水平处测量对应的半导体层的中心时，第二区100B中的半导体层103a的厚度T1(保持)大于第一区100A中的半导体层103a的厚度T2。
在一实施例中，高介电常数金属栅极堆叠物235包含栅极介电层231、在栅极介电层231上方的功函数金属层232以及在功函数金属层232上方的金属填充层233。栅极介电层231可包含高介电常数介电材料，例如氧化铪、氧化锆、氧化镧、氧化钛、氧化钇和钛酸锶。栅极介电层231可通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)及/或其他合适的方法形成。在一实施例中，栅极介电层231形成比栅极介电层131更厚。举例来说，较厚的栅极介电层231允许第二区100B中的晶体管在比第一区100A中的晶体管更高的电压下操作。在一些实施例中，高介电常数金属栅极堆叠物235包含在栅极介电层231与半导体层103a之间的界面层。界面层可包含氧化硅、氮氧化硅或其他合适的材料。在一些实施例中，取决于堆叠鳍式场效晶体管的类型，功函数金属层232包含n型或p型功函数层。举例来说，n型功函数层可包括足够小的有效功函数的金属，例如钛、铝、碳化钽、氮碳化钽、氮化钽硅或前述的组合。举例来说，p型功函数层可包括足够大的有效功函数的金属，例如氮化钛、氮化钽、钌、钼、钨、铂或前述的组合。功函数金属层232可通过化学气相沉积、物理气相沉积、原子层沉积及/或其他合适的制程形成。在一些实施例中，金属填充层233可包含铝、钨、钴、铜及/或其他合适的材料，且可通过化学气相沉积、物理气相沉积、电镀及/或其他合适的制程形成。高介电常数金属栅极堆叠物235通过栅极间隙壁124与源极/漏极部件208隔开。在一些实施例中，在栅极介电层231与功函数金属层232之间可具有额外层，及/或功函数金属层232围绕额外层。在高介电常数金属栅极堆叠物235包含上述的界面层的实施例中，界面层设置于栅极介电层231与鳍103的表面之间。在高介电常数金属栅极堆叠物235不包含界面层的一实施例中，栅极介电层231设置为直接接触鳍103的表面。
在一些实施例中，方法10可以不同于图8-图14显示的顺序进行操作24到36。举例来说，方法10可进行操作32、34和36来形成高介电常数金属栅极堆叠物235，接着进行操作24、26、28、30来形成高介电常数金属栅极堆叠物135。
在操作38，方法10(图1B)对多栅极装置100进行进一步制造步骤。举例来说，方法10可蚀刻多栅极装置100的源极/漏极区中的层间介电层118和接触蚀刻停止层116，以形成暴露源极/漏极部件108和208的接触孔，在源极/漏极部件108和208上形成硅化物部件，在硅化物部件上方形成源极/漏极接点，形成连接至高介电常数金属栅极堆叠物135和235的栅极接点，并形成互连层。
虽然未意图限制，但是本发明实施例提供一个或多个以下的优点。首先，本发明实施例提供集成电路的不同区域(例如核心区和输入输出区)中的内部间隙壁部件。相较于在一个区域中提供内部间隙壁部件而在另一个区域中不提供内部间隙壁部件的方法，这改善了晶体管的一致性，并简化了制造过程。第二，本发明实施例提供集成电路的核心区中的全绕式栅极晶体管以及集成电路的输入输出区中的堆叠鳍式场效晶体管，以实现两个区域中晶体管的不同效能目标。举例来说，全绕式栅极晶体管可提供高操作速度及/或低功耗，而堆叠鳍式场效晶体管提供高操作电压及高驱动能力。第三，本发明实施例可容易地整合至现有的半导体制造过程中。
在一例示性方面，本发明实施例针对集成电路(IC)。集成电路包含基底、位于基底的第二区上的堆叠鳍式场效晶体管以及位于基底的第一区上的全绕式栅极(GAA)晶体管。堆叠鳍式场效晶体管包含两个第一源极/漏极部件、交替堆叠且设置于两个第一源极/漏极部件之间的第一半导体层和第二半导体层的堆叠物、设置于第一半导体层和第二半导体层的堆叠物的顶部和侧壁上的第一栅极介电层、设置于第一栅极介电层上方的第一栅极电极层以及横向设置于第二半导体层的每一者与两个第一源极/漏极部件的每一者之间的第一间隙壁部件，其中第一半导体层和第二半导体层包含不同材料，且第一半导体层电性连接两个第一源极/漏极部件。全绕式栅极晶体管包含两个第二源极/漏极部件、电性连接两个第二源极/漏极部件的第三半导体层的堆叠物、环绕第三半导体层的每一者的第二栅极介电层、在第二栅极介电层上方的第二栅极电极层以及横向设置于第二栅极介电层与两个第二源极/漏极部件的每一者之间的第二间隙壁部件。
在集成电路的一些实施例中，第一半导体层和第三半导体层包含相同的半导体材料。在另一些实施例中，第一半导体层的其中一者与第三半导体层的其中一者在相同堆叠物水平高度处，且第一半导体层的其中一者的中间部分比第三半导体层的其中一者的中间部分更厚。
在集成电路的一些实施例中，第一半导体层和第三半导体层包含硅，且第二半导体层包含硅锗。在一些实施例中，第一间隙壁部件和第二间隙壁部件包含相同的介电材料。在另一实施例中，第一间隙壁部件和第二间隙壁部件包含低介电常数介电材料、氧化硅、氮化硅、氮氧化硅、碳化硅或碳氧化硅或氮碳氧化硅。
在一实施例中，集成电路更包含设置于第一栅极电极层的侧壁上方以及第一半导体层和第二半导体层的堆叠物的顶表面和侧壁表面上方的第一栅极间隙壁，以及设置于第二栅极电极层的侧壁上方以及第三半导体层的堆叠物的最顶层上方的第二栅极间隙壁。在集成电路的一些实施例中，第一栅极介电层比第二栅极介电层更厚。
在另一例示性方面，本发明实施例针对集成电路(IC)的制造方法，此方法包含提供结构，此结构具有基底、在集成电路的第二区中的基底上方的第一鳍、在集成电路的第一区中的基底上方的第二鳍、分别占据第一鳍和第二鳍的通道区的第一牺牲栅极堆叠物和第二牺牲栅极堆叠物以及分别在第一牺牲栅极堆叠物和第二牺牲栅极堆叠物的侧壁上的第一栅极间隙壁和第二栅极间隙壁。第一鳍和第二鳍各包含第一半导体材料的第一层及不同于第一半导体材料的第二半导体材料的第二层。第一层和第二层交替堆叠于基底上方。此方法更包含蚀刻相邻于第一栅极间隙壁的第一鳍，以形成第一源极/漏极沟槽；蚀刻相邻于第二栅极间隙壁的第二鳍，以形成第二源极/漏极沟槽；将暴露于第一源极/漏极沟槽和第二源极/漏极沟槽中的第二层部分凹陷，以在第一鳍和第二鳍的第一层的相邻层之间形成间隙；以及在第一鳍和第二鳍的间隙中形成内部间隙壁部件。
在此方法的一实施例中，蚀刻第一鳍和蚀刻第二鳍通过相同制程进行。在一实施例中，此方法更包含在第一源极/漏极沟槽中外延成长第一源极/漏极部件，并在第二源极/漏极沟槽中外延成长第二源极/漏极部件。在另一实施例中，此方法包含在第一源极/漏极部件和第二源极/漏极部件上方以及在第一牺牲栅极堆叠物和第二牺牲栅极堆叠物上方形成层间介电层。在另一实施例中，此方法包含形成第一蚀刻遮罩，第一蚀刻遮罩覆盖第一区，并暴露第二区；通过第一蚀刻遮罩移除第一牺牲栅极堆叠物，以形成第一栅极沟槽；以及在第一栅极沟槽中以及具有第一层和第二层的第一鳍的顶部和侧壁上方形成第一栅极介电层。在另一实施例中，此方法包含形成第二蚀刻遮罩，第二蚀刻遮罩覆盖第二区，并暴露第一区；通过第二蚀刻遮罩移除第二牺牲栅极堆叠物，以形成第二栅极沟槽；从第二栅极沟槽移除第二鳍的第二层，保留第二鳍的第一层悬置于基底上方；以及形成第二栅极介电层环绕第二鳍的第一层的每一者。在另一实施例中，此方法包含在第一栅极介电层上方形成第一栅极电极层，并在第二栅极介电层上方形成第二栅极电极层。
在另一例示性方面，本发明实施例针对集成电路(IC)的制造方法，此方法包含提供结构，此结构具有基底、在集成电路的第二区中的基底上方的第一鳍、在集成电路的第一区中的基底上方的第二鳍、分别在第一鳍和第二鳍上方的第一牺牲栅极堆叠物和第二牺牲栅极堆叠物以及分别在第一牺牲栅极堆叠物和第二牺牲栅极堆叠物的侧壁上的第一栅极间隙壁和第二栅极间隙壁。第一鳍和第二鳍各包含第一半导体材料的第一层及不同于第一半导体材料的第二半导体材料的第二层。第一层和第二层交替堆叠于基底上方。此方法更包含蚀刻第一鳍和第二鳍，以在相邻于第一栅极间隙壁处形成第一源极/漏极沟槽，并在相邻于第二栅极间隙壁处形成第二源极/漏极沟槽；将暴露于第一源极/漏极沟槽和第二源极/漏极沟槽中的第二层部分凹陷，以在第一鳍和第二鳍的第一层的相邻层之间形成间隙；在第一鳍和第二鳍的间隙中形成内部间隙壁部件；以及在形成内部间隙壁部件之后，在第一源极/漏极沟槽和第二源极/漏极沟槽中分别外延成长第一源极/漏极部件和第二源极/漏极部件。
在一实施例中，此方法更包含形成第一蚀刻遮罩，第一蚀刻遮罩覆盖第一区，并暴露第二区；通过第一蚀刻遮罩移除第一牺牲栅极堆叠物，以形成第一栅极沟槽，第一栅极沟槽暴露具有第一层和第二层的第一鳍的顶部和侧壁；在具有第一层和第二层的第一鳍的顶部和侧壁上方形成第一栅极介电层；以及在第一栅极介电层上方形成第一栅极电极层。
在另一实施例中，此方法更包含形成第二蚀刻遮罩，第二蚀刻遮罩覆盖第二区，并暴露第一区；通过第二蚀刻遮罩移除第二牺牲栅极堆叠物，以形成第二栅极沟槽；从第二栅极沟槽移除第二鳍的第二层，保留第二鳍的第一层悬置于基底上方；形成第二栅极介电层环绕第二鳍的第一层的每一者；以及在第二栅极介电层上方形成第二栅极电极层。
在此方法的一实施例中，内部间隙壁包含低介电常数介电材料、氧化硅、氮化硅、氮氧化硅、碳化硅或碳氧化硅或氮碳氧化硅。在另一实施例中，第一半导体材料包含外延成长硅，且第二半导体材料包含外延成长硅锗。
前述内文概述了许多实施例的特征，使本技术领域中具有通常知识者可以从各个方面更加了解本发明实施例。本技术领域中具有通常知识者应可理解，且可轻易地以本发明实施例为基础来设计或修饰其他制程及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中具有通常知识者也应了解这些相等的结构并未背离本发明的发明精神与范围。在不背离本发明的发明精神与范围的前提下，可对本发明实施例进行各种改变、置换或修改。

Claims (1)

1.一种集成电路，包括:
一基底；
一堆叠鳍式场效晶体管，位于该基底的一第二区上，该堆叠鳍式场效晶体管具有两个第一源极/漏极部件、交替堆叠且设置于该两个第一源极/漏极部件之间的多个第一半导体层和多个第二半导体层的一堆叠物、设置于该多个第一半导体层和该多个第二半导体层的该堆叠物的顶部和侧壁上的一第一栅极介电层、设置于该第一栅极介电层上方的一第一栅极电极层以及横向设置于该多个第二半导体层的每一者与该两个第一源极/漏极部件的每一者之间的一第一间隙壁部件，其中该多个第一半导体层和该多个第二半导体层包含不同材料，且该多个第一半导体层电性连接该两个第一源极/漏极部件；以及
一全绕式栅极晶体管，位于该基底的一第一区上，该全绕式栅极晶体管具有两个第二源极/漏极部件、电性连接该两个第二源极/漏极部件的多个第三半导体层的一堆叠物、环绕该多个第三半导体层的每一者的一第二栅极介电层、在该第二栅极介电层上方的一第二栅极电极层以及横向设置于该第二栅极介电层与该两个第二源极/漏极部件的每一者之间的一第二间隙壁部件。
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