CN113964039B - Novel self-aligned power Trench MOSFET manufacturing method and structure thereof - Google Patents
Novel self-aligned power Trench MOSFET manufacturing method and structure thereof Download PDFInfo
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- CN113964039B CN113964039B CN202111201596.8A CN202111201596A CN113964039B CN 113964039 B CN113964039 B CN 113964039B CN 202111201596 A CN202111201596 A CN 202111201596A CN 113964039 B CN113964039 B CN 113964039B
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- 238000004519 manufacturing process Methods 0.000 title claims description 9
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- 229920005591 polysilicon Polymers 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 8
- -1 boron ions Chemical class 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
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- 238000009413 insulation Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000010276 construction Methods 0.000 description 1
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- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention provides a novel self-aligned power Trench MOSFET, wherein a Trench groove and a contact hole (contact groove) are determined by a mask plate, so that the spacing between Trench Pitch (namely the spacing between adjacent Trench grooves) can be greatly reduced.
Description
Technical Field
The invention relates to the technical field of power devices, in particular to a novel self-aligned power Trench MOSFET manufacturing method and a structure thereof.
Background
In the development of power devices, power MOSFETs have played a very important role. In market share, taking 2006 as an example, power MOSFETs account for almost 26% of the entire power device market, and power MOSFETs are so rapidly developed for the following reasons:
(1) The frequency is high: the field effect transistor is used as a multi-sub device, and compared with a bipolar power device, the frequency of the field effect transistor is greatly improved, so that the field effect transistor has an expansion in high-frequency application and plays a key role in reducing the whole volume.
(2) The driving is convenient: compared with a bipolar power device, the field effect transistor is controlled by changing current control into voltage control, and can be controlled by directly using a plurality of special high-voltage integrated circuits as driving.
(3) The on-state resistance is small: the on-state resistance of the field effect transistor of the new generation is better than that of the PN junction, and even better than that of the Schottky diode which has the lowest forward resistance in the past. Thus, a MOSFET is not only a fast switching device, but also an optimal rectifying element under certain conditions. These advantages have led to MOSFETs entering almost every field of power conversion.
(4) Supplement of novel MOSFET device: MOSFET-based new devices, such as IGBTs, are emerging that further expand the MOS-type devices.
The development process of the power MOSFET is basically a process of striving to increase the power (i.e. increase the operating voltage and current of the device) on the basis of preserving and exerting the characteristics of the MOS device itself. However, since there is no conductance modulation effect like bipolar device minority carrier injection, as the breakdown voltage of the device increases (greater than 200V), the on-resistance increases dramatically, which greatly limits the increase in power MOS breakdown voltage and also limits its use in high voltage systems.
The power MOSFET development is successively subjected to the structural evolution processes of LDMOS (transverse plane double diffusion), VVMOS (V-shaped groove), UVMOS (U-shaped groove) and plane VDMOS (longitudinal plane double expansion groove) to Trench gate and the like. The LDMOS has a simple structure and a simpler manufacturing process, but has the main defects that the utilization rate of the chip area is not high, and because the diffusion area and the channel area are formed on the surface of the wafer, serious waste is caused to the area of the wafer, so that the VVMOS appears next, the drain electrode can be arranged on the back surface of the wafer, and the diffusion area and the channel area are in the vertical direction, so that the chip integration level is obviously improved. However, the V-shaped spike of the VVMOS is easy to cause the concentration of the electric field lines to reduce the breakdown voltage, in order to overcome the defect, the UVMOS has a U-shaped gate to prevent the concentration of the electric field, but the UVMOS is difficult to realize in the corrosion process due to the crystal orientation, and then the V-shaped spike of the VVMOS is brittle to make the gate flat, so that the VDMOS is a major revolution in the structure of the power MOS, and plays a critical role in promoting the development of the power MOSFET.
The VDMOSFET adopts a self-aligned double diffusion process, takes a polysilicon gate as a mask, and forms a conductive channel by utilizing the transverse diffusion difference of two diffusions, so that the pressure-resistant level, the reliability and the manufacturing process of the device are advanced by one step.
The on-state resistance R of the drain and the source of the device is the total resistance between the drain and the source when the unit area of the device is on, and is an important parameter for determining the maximum rated current and the power loss of the device DSON. Because of many advantages of VDMOS, the early low-voltage MOSFET is mostly a planar VDMOS process, but because of the limitation of JFET parasitic resistance in the planar process MOSFET itself, the area of a single cell cannot be reduced very little, so that it becomes difficult to increase the cell density, and the development of the planar process MOSFET toward the direction of further reducing R is limited. In this case, in order to further increase the cell density and increase the total width of the chip channel DSON per unit area, d.ueda in 1984 used the Trench technique for the first time for manufacturing UMOS devices. Because the Trench gate (UMOS) changes the channel from horizontal to straight, the influence of the parasitic JFET resistance of the material plane structure is thoroughly eliminated, the cell size is greatly reduced, and the reduction of the cell size can bring the advantages of increasing the channel width-to-length ratio on a unit silicon wafer of the device, increasing the current, reducing the on-resistance and the like. The Trench gate structure almost completely eliminates the defects of the planar VDMOS, and is widely applied to the field of manufacturing low-voltage MOSFETs. Various Trench MOSFET structures have also begun to develop.
The traditional power Trench MOSFET needs two masks for photoetching to form the Trench and the contact hole, and because a certain overlay interval is needed between the two masks and the contact hole is influenced by the minimum interval of photoetching, the Trench Pitch (the distance between adjacent Trench) cannot be minimized.
In the prior art, the patent CN101663760A has the following process flow:
as in fig. 1, a dielectric is deposited on the epitaxial region and the Gate electrode is lithographically located; etching the Gate groove; removing the medium on the epitaxial region; gate oxidation and polysilicon deposition; removing the polysilicon of the dielectric layer, and forming a concave grid electrode region in the Gate groove only; depositing a second layer of medium; etching the second layer of medium to make the medium embedded only on the surface of the concave part of the grid region; etching the surface of the silicon wafer by taking a second layer of medium on the polysilicon as Hardmask, and forming a Source region and a contact hole of the device by a self-alignment process;
in this patent, the upper surface of the second layer of medium on the polysilicon in the trench is substantially parallel to the wafer surface, see FIG. 2A; etching the surface of the silicon wafer by using a second dielectric layer on the surface of the polysilicon as Hardmask, and etching the surface of the silicon wafer in the Source region to make the surface of the silicon wafer lower than the surface of the second dielectric layer on the polysilicon; see fig. 2B.
Disclosure of Invention
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
The invention provides a novel self-aligned power Trench MOSFET, wherein a Trench groove and a contact hole (contact groove) are defined by a mask plate, so that the spacing between Trench Pitch (namely the spacing between adjacent Trench grooves) can be greatly reduced. For this reason, the present application provides a method for preparing a novel self-aligned power Trench MOSFET, including the following steps:
step1: forming an epitaxial region on the upper surface of the substrate in an epitaxial manner;
step2: boron ions are implanted into the right upper surface of the epitaxial region to form a main body region;
step3: depositing a first dielectric layer on the main body region;
step4: etching the first dielectric layer to form a groove, wherein the groove penetrates through the main body region to the epitaxial region;
step5: oxidizing the groove and filling polycrystalline silicon to form a grid electrode, wherein the polycrystalline silicon covers the first dielectric layer;
step6: etching the polysilicon on the first dielectric layer, wherein the surface of the polysilicon in the groove is lower than the surface of the first dielectric layer, and the surface of the polysilicon can be parallel to the surface of the epitaxial layer, lower than the surface of the epitaxial layer or higher than the surface of the epitaxial layer;
step7: depositing a second dielectric layer to cover the first dielectric layer and the polysilicon in the groove;
step8: etching the second dielectric layer on the first dielectric layer, and only reserving the second dielectric layer on the groove polysilicon;
step9: completely removing the first dielectric layer;
step10: doping ions on the body region to form a source region;
step11: depositing a third dielectric layer, wherein the third dielectric layer covers the source electrode region and the second dielectric layer;
step12, etching the third dielectric layer in a maskless mode and forming a side wall on the side wall of the second dielectric layer and the side wall of the polysilicon;
step13, etching the source region to form a contact groove, wherein the contact groove passes through the source region to the main body region;
step14, implanting boron ions into the contact groove to form a contact area of the main body area;
and Step15, performing metal sputtering or evaporation on the front surface of the wafer structure formed in Step14 to form a metallization layer, wherein the metallization layer covers the contact area, the side wall and the second dielectric layer.
As a preferred embodiment, the substrate is heavily doped N-type semiconductor silicon, and the epitaxial region is lightly doped N-type semiconductor silicon.
As a preferred embodiment, the source region is heavily doped N-type semiconductor silicon.
In a preferred embodiment, the body region is formed by doping an epitaxial region with boron ions.
As a preferred embodiment, the first dielectric layer and the second dielectric layer are selected from silicon dioxide or silicon nitride; the first dielectric layer and the second dielectric layer are set to be of different material types.
In a preferred embodiment, the third dielectric layer is selected from silicon dioxide or silicon nitride.
In a preferred embodiment, in step6, the upper surface of the polysilicon is above, below or flush with the upper surface of the body region (epitaxial layer) after etching.
In a preferred embodiment, in step8, the surface of the second dielectric layer is flush with or lower than the surface of the first dielectric layer after etching.
In a preferred embodiment, the depth of the contact trench is greater than the depth of the source region in step15 until the body region below the source region is reached, but not beyond the body region.
It is another object of the present invention to provide a novel self-aligned power Trench MOSFET with Trench and contact holes (contact trenches) defined by a single reticle, which can greatly reduce the Pitch of the Trench Pitch (i.e., the Pitch between adjacent Trench trenches).
Drawings
Fig. 1 is a cross-sectional view of a prior art structure.
Fig. 2A is a structural diagram of one step in the prior art.
Fig. 2B is a structural diagram of another step in the prior art.
FIG. 3 shows the structure formed in Step1 of the present invention.
FIG. 4 shows the structure formed in Step2 of the present invention.
FIG. 5 shows the structure formed in Step3 of the present invention.
FIG. 6 shows the structure formed in Step4 of the present invention.
FIG. 7 shows the structure formed in Step5 of the present invention.
FIG. 8 shows the structure formed in Step6 of the present invention.
FIG. 9 shows the structure formed in Step7 of the present invention.
FIG. 10 shows the structure formed in Step8 of the present invention.
FIG. 11 shows the structure formed in Step9 of the present invention.
Fig. 12 shows the structure formed in Step10 of the present invention.
Fig. 13 shows the structure formed in Step11 of the present invention.
Fig. 14 shows the structure formed in Step12 of the present invention.
FIG. 15 shows the structure formed in Step13 of the present invention.
Fig. 16 shows the structure formed in Step14 of the present invention.
FIG. 17 shows the structure formed in Step15 of the present invention.
Detailed Description
The following description is presented to enable one skilled in the art to make and use the invention and to incorporate it into the context of a particular application. Various modifications, as well as various uses in different applications will be readily apparent to persons skilled in the art, and the generic principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without limitation to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
The reader is directed to all documents and documents filed concurrently with this specification and open to public inspection with this specification, and the contents of all such documents and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic set of equivalent or similar features.
Note that where used, the designations left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for convenience only and do not imply any particular orientation of securement. In fact, they are used to reflect the relative position and/or orientation between the various parts of the object. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Note that, where used, further, preferably, further and more preferably, the brief description of another embodiment is made on the basis of the foregoing embodiment, and further, preferably, further or more preferably, the combination of the contents of the rear band with the foregoing embodiment is made as a complete construction of another embodiment. A further embodiment is composed of several further, preferably, still further or preferably arrangements of the strips after the same embodiment, which may be combined arbitrarily.
The invention is described in detail below with reference to the drawings and the specific embodiments. It is noted that the aspects described below in connection with the drawings and the specific embodiments are merely exemplary and should not be construed as limiting the scope of the invention in any way.
In the following text description, P+ and N+ represent heavy doping, and the doping concentration is high; p-, N-means lightly doped, low doping concentration.
Referring to fig. 3, in step1, an epitaxial region 112 is epitaxially formed on a wafer substrate or substrate 111, and the wafer substrate or substrate 111 is heavily doped N-type semiconductor (the doped ion is phosphorus, i.e., n+), so the wafer substrate or substrate 111 is expressed as an n+ substrate 111. The lightly doped N-EPI region 112, abbreviated as N-EPI, is used for the EPI region 112.
Referring to fig. 4, in step2, a boron ion implantation is performed on the surface of the N-epi region 112 to form a body region 114, i.e., a P body region.
Referring to fig. 5, in step3, a first dielectric layer 118 is deposited on the surface of the body region 114, and the first dielectric layer 118 is silicon dioxide or silicon nitride, and the thickness thereof is adapted to be 1-10 um.
Referring to fig. 6, in step4, the trench 12 is etched in the first dielectric layer 118 by photoresist-exposure-development-etching, and the trench 12 is etched through the body region 114 to the epitaxial region 112, i.e., the depth of the trench 12 needs to exceed the depth of the body region 114, and is inserted into the epitaxial region 112, but does not exceed the depth of the epitaxial region 112. This is the only one process requiring a photolithography process.
Referring to fig. 7, in step5, the Trench (i.e., trench 12) is subjected to gate oxidation and doped polysilicon 121 is deposited and filled to form a gate, such that polysilicon 121 fills the Trench and polysilicon 121 is covered with first dielectric layer 118. Specifically, a gate insulating region 122 is formed between the polysilicon 121 and the Trench, and the gate insulating region 122 covers the bottom and the peripheral walls of the Trench.
Referring to fig. 8, in step6, polysilicon 121 is removed from first dielectric layer 118 by a maskless Etch (Etch Back), but to ensure that polysilicon 121 is fully embedded in trench 12. The upper surface of the polysilicon 121 after etching is above, below, or flush with the upper surface of the body region 114.
Referring to fig. 9, in step7, a second dielectric layer 119 is deposited to cover the first dielectric layer 118 and the trench 12. The first dielectric layer 118 and the second dielectric layer 119 are selected from silicon dioxide or silicon nitride; the first dielectric layer 118 and the second dielectric layer 119 are set to be different materials.
Referring to fig. 10, in step8, the second dielectric layer 119 on the first dielectric layer 118 is etched away by a maskless etching (Etch Back) method, and only the second dielectric layer 119 on the trench 12 remains. The surface of the second dielectric layer 119 after etching is flush with or lower than the surface of the first dielectric layer 118.
Referring to fig. 11, in step9, the first dielectric layer 118 is completely removed, and the surface of the body region 114 is completely exposed.
Referring to fig. 12, in step10, source regions 117, i.e., source regions, are formed by doping ions into body regions 114. Further, there is a heavy n+ type doping, i.e., referred to as an n+ Source region. The source region 117 is heavily doped N-type semiconductor silicon.
Referring to fig. 13, in step11, a third dielectric 113 is deposited, the third dielectric 113 covering the n+ Source region and the second dielectric layer 119.
Referring to fig. 14, in step12, the third dielectric 113 is etched and a sidewall 1131, i.e., spacer, is formed on the sidewall of the second dielectric layer 119. The Spacer etching does not need a mask, the third dielectric layer on the surface of the wafer is etched, the Spacer is formed on the side face of the second dielectric layer, and the third dielectric 113 on the surface of the silicon of the wafer is completely etched.
Further, the third medium 113 is silicon dioxide or silicon nitride.
Referring to fig. 15, in step13, a contact trench is formed by dry etching down to the n+source region, the depth of the contact trench being greater than the depth of the n+source region until reaching the P body region below the n+source region, but not exceeding the P body region, because the purpose is to achieve ohmic contact with the P body region, the contact trench passing through the n+source region to the body region 114, and providing a precondition for ohmic contact with the body region 114.
Referring to fig. 16, in step14, boron ions are implanted into the contact trench to a degree of heavy implantation to form an ohmic contact region 115 of the P body region.
Referring to fig. 17, in step15, metallization is performed on the wafer structure formed in step14 to form a metallization layer 116, such that all n+ regions are connected, and the metallization layer 116 forms a contact layer/contact, i.e., a source contact.
The present invention has been described in detail with reference to the embodiments of the drawings, and those skilled in the art can make various modifications to the invention based on the above description. Accordingly, certain details of the illustrated embodiments are not to be taken as limiting the invention, which is defined by the appended claims.
Claims (10)
1. The novel self-aligned power Trench MOSFET manufacturing method is characterized by comprising the following steps of: step1: forming an epitaxial region on the upper surface of the substrate in an epitaxial manner;
step2: boron ions are implanted into the right upper surface of the epitaxial region to form a main body region;
step3: depositing a first dielectric layer on the main body region;
step4: etching the first dielectric layer to form a groove, wherein the groove penetrates through the main body region to the epitaxial region;
step5: oxidizing the groove, filling polycrystalline silicon to form a grid electrode, and forming a grid electrode insulation region between the polycrystalline silicon and the groove, wherein the polycrystalline silicon covers the first dielectric layer;
step6: etching the polysilicon on the first dielectric layer, wherein the surface of the polysilicon in the groove is lower than the surface of the first dielectric layer, and the surface of the polysilicon can be parallel to the surface of the epitaxial layer, lower than the surface of the epitaxial layer or higher than the surface of the epitaxial layer;
step7: depositing a second dielectric layer to cover the first dielectric layer and the polysilicon in the groove;
step8: etching the second dielectric layer on the first dielectric layer, and only reserving the second dielectric layer on the groove polysilicon;
step9: completely removing the first dielectric layer;
step10: doping ions on the body region to form a source region;
step11: depositing a third dielectric layer, wherein the third dielectric layer covers the source electrode region and the second dielectric layer;
step12, etching the third dielectric layer in a maskless mode and forming a side wall on the side wall of the second dielectric layer and the side wall of the polysilicon;
step13, etching the source region to form a contact groove, wherein the contact groove passes through the source region to the main body region;
step14, implanting boron ions into the contact groove to form a contact area of the main body area;
and Step15, performing metal sputtering or evaporation on the front surface of the wafer structure formed in Step14 to form a metallization layer, wherein the metallization layer covers the contact area, the side wall and the second dielectric layer.
2. The method of claim 1, wherein the substrate is heavily doped N-type semiconductor silicon and the epitaxial region is lightly doped N-type semiconductor silicon.
3. The method of claim 1, wherein the source region is heavily doped N-type semiconductor silicon.
4. The method of claim 1, wherein the body region is formed by doping an epitaxial region with boron ions.
5. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are selected from silicon dioxide or silicon nitride; the first dielectric layer and the second dielectric layer are set to be of different material types.
6. The method of claim 1, wherein the third dielectric layer is selected from silicon dioxide or silicon nitride.
7. The method of claim 1, wherein in step6, the upper surface of the polysilicon is above, below, or level with the upper surface of the body region (epitaxial layer) after etching.
8. The method of claim 1, wherein in step8, the surface of the second dielectric layer is flush with or lower than the surface of the first dielectric layer after etching.
9. The method of claim 1 wherein in step15 the depth of the contact trench is greater than the depth of the source region until the body region below the source region is reached but not exceeded.
10. A novel self-aligned power Trench MOSFET made by the method of making as claimed in claims 1-9.
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| CN111370463A (en) * | 2018-12-26 | 2020-07-03 | 深圳尚阳通科技有限公司 | Trench gate power device and manufacturing method thereof |
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| CN111370463A (en) * | 2018-12-26 | 2020-07-03 | 深圳尚阳通科技有限公司 | Trench gate power device and manufacturing method thereof |
| CN110416211A (en) * | 2019-07-24 | 2019-11-05 | 上海朕芯微电子科技有限公司 | A kind of super-self-aligned power Trench MOSFET production method and structure |
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| IGBT全自对准栅挖槽工艺研究;袁寿财,汪李明,祝咏晨;微电子学(02);全文 * |
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