CN113964039A - Novel self-aligned power Trench MOSFET manufacturing method and structure thereof - Google Patents
Novel self-aligned power Trench MOSFET manufacturing method and structure thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention provides a novel power Trench MOSFET with a self-aligned structure, wherein Trench grooves and contact holes (contact grooves) of the power Trench MOSFET are determined by a mask, and the spacing of Trench Pitch (namely the spacing between adjacent Trench grooves) can be greatly reduced.
Description
Technical Field
The invention relates to the technical field of power devices, in particular to a manufacturing method and a structure of a novel self-aligned power Trench MOSFET.
Background
In the development of power devices, power MOSFETs have been playing a very important role as ground. From a market share, taking 2006 as an example, power MOSFETs account for almost 26% of the entire power device market, and power MOSFETs are so rapidly developed for the following reasons:
(1) the frequency is high: as a multi-sub device, compared with a bipolar power device, the frequency of the field effect transistor is greatly improved, so that the field effect transistor is expanded in high-frequency application and plays a key role in reducing the volume of the whole device.
(2) The driving is convenient: compared with a bipolar power device, the field effect transistor has the advantages that the control method is changed from current control to voltage control, and some special high-voltage integrated circuits can be directly used as drives for control.
(3) The on-state resistance is small: the on-resistance of the field effect transistor of the new generation is better than not only the forward resistance of the PN junction but also that of what was thought to have the lowest forward resistance in the past, known as a schottky diode. Therefore, a MOSFET is not only a fast switching device, but also an optimal rectifying element under certain conditions. These advantages have brought MOSFETs into almost every area of power conversion.
(4) Supplement of the novel MOSFET device: new devices based on MOSFETs, such as IGBTs, have further expanded the emergence of MOS-type devices.
The development of power MOSFETs is essentially a process of trying to increase power (i.e., increase the operating voltage and current of the device) while retaining and exploiting the characteristics of MOS devices themselves. However, as the breakdown voltage of the device increases (more than 200V), the on-resistance thereof also increases sharply due to the conductance modulation effect generated by minority carrier injection without the bipolar-like device, which greatly limits the increase of the breakdown voltage of the power MOS and also limits the use thereof in a high-voltage system.
The power MOSFET is developed through the structural evolution processes of LDMOS (lateral planar double diffusion), VVMOS (V-shaped groove), UVMOS (U-shaped groove) and planar VDMOS (longitudinal planar double diffusion groove) to Trench gate (groove gate) and the like. The LDMOS is simple in structure and simple in manufacturing process, but the main defect is that the utilization rate of the area of a chip is low, and the diffusion region and the channel region are formed on the surface of a wafer, so that the area of the wafer is seriously wasted, and then the VVMOS is appeared, the drain electrode of the VVMOS can be arranged on the back surface of the wafer, so that the diffusion region and the channel region are in the vertical direction, and the integration level of the chip is remarkably improved. However, the V-shaped spikes of the VVMOS easily cause the concentration of electric field lines to reduce the breakdown voltage, and in order to overcome this defect, the UVMOS is generated, and people make the gate into a U-shape to prevent the concentration of the electric field, but because of the crystal orientation, the UVMOS is difficult to realize in the corrosion process, and then people make the gate flat, and then the VDMOS appears, which is a great revolution on the structure of the power MOS and plays a critical role in promoting the development of the power MOSFET.
The VDMOSFET adopts a self-aligned double diffusion process, takes a polysilicon gate as a mask, and forms a conductive channel by utilizing the transverse diffusion difference of two times of diffusion, so that the voltage resistance level, the reliability and the manufacturing process of the device are greatly improved.
The drain-source on-state resistance R of the device is the total resistance between the drain and the source when the device is in an on state in unit area, and is an important parameter for determining the maximum rated current and power loss of the DSON of the device. Due to the advantages of the VDMOS, most of the early low-voltage MOSFETs use the planar VDMOS process, but due to the limitation of the JFET parasitic resistance in the planar MOSFET itself, the area of a single cell cannot be reduced, which makes it difficult to increase the cell density, and limits the development of the planar MOSFET toward further reduction of R. In this case, in order to further increase the cell density and increase the total width of the chip channel DSON per unit area, d.ueda first used the Trench technology for fabricating UMOS devices in 1984. Because the Trench gate (UMOS) changes the horizontal channel into straight channel, the influence of the parasitic JFET resistance of the material plane structure is thoroughly eliminated, the size of the unit cell is greatly reduced, and the reduction of the size of the unit cell can increase the width-to-length ratio of the channel on the unit silicon wafer of the device, thereby increasing the current, reducing the on-resistance and the like. The Trench gate structure almost completely eliminates the defects of a planar VDMOS, and is widely applied to the field of manufacturing low-voltage MOSFETs. Various Trench MOSFET structures are also beginning to emerge.
In the traditional power Trench MOSFET, Trench and a contact hole of the power Trench MOSFET need two mask plates to be formed by photoetching, and because a certain alignment distance is needed between the two mask plates and is influenced by the minimum distance of photoetching, Trench (the distance between adjacent Trench) cannot be minimized.
In the prior art, patent CN101663760A has the following process flow:
depositing a medium on the epitaxial region and determining the position of a Gate electrode by photoetching as shown in FIG. 1; etching a Gate groove; removing the medium on the epitaxial region; oxidizing gate and depositing polysilicon; removing the polysilicon of the dielectric layer, and forming a recessed Gate region only in the Gate trench; depositing a second layer of medium; etching the second layer of medium to enable the medium to be embedded on the surface of the concave part of the gate region; taking a second layer of medium on the polycrystalline silicon as Hardmask, etching the surface of the silicon wafer, and forming a Source area and a contact hole of the device by a self-alignment process;
in this patent, the upper surface of the second layer of dielectric on the polysilicon in the trench is substantially parallel to the surface of the silicon wafer, as shown in FIG. 2A; using a second dielectric layer on the surface of the polycrystalline silicon as Hardmask, etching the surface of the silicon wafer by Etchback, and enabling the surface of the silicon wafer in the Source area to be lower than the surface of the second dielectric layer on the polycrystalline silicon; see figure 2B.
Disclosure of Invention
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
The invention provides a novel power Trench MOSFET with a self-aligned structure, wherein Trench grooves and contact holes (contact grooves) are determined by a mask, and the spacing of Trench Pitch (namely the spacing between adjacent Trench grooves) can be greatly reduced. Therefore, the application provides a preparation method of a novel self-aligned power Trench MOSFET, which comprises the following steps:
a novel manufacturing method of a self-aligned power Trench MOSFET is characterized by comprising the following steps:
step 1: forming an epitaxial region on the positive upper surface of the substrate in an epitaxial manner;
step 2: implanting boron ions into the positive upper surface of the epitaxial region to form a body region;
step 3: depositing a first dielectric layer on the main body region;
step 4: etching the first dielectric layer to form a groove, wherein the groove penetrates through the main body region to the epitaxial region;
step 5: oxidizing the groove and filling polycrystalline silicon to form a grid, wherein the polycrystalline silicon covers the first dielectric layer;
step 6: etching the polycrystalline silicon on the first dielectric layer, wherein the surface of the polycrystalline silicon in the groove is required to be lower than the surface of the first dielectric layer, and the surface of the polycrystalline silicon can be parallel to the surface of the epitaxial layer, or lower than the surface of the epitaxial layer, or higher than the surface of the epitaxial layer;
step 7: depositing a second dielectric layer to cover the first dielectric layer and the polycrystalline silicon in the groove;
step 8: etching the second dielectric layer on the first dielectric layer, and only keeping the second dielectric layer on the groove polysilicon;
step 9: completely removing the first dielectric layer;
step 10: doping ions on the body region to form a source region;
step 11: depositing a third dielectric layer, wherein the third dielectric layer covers the source region and the second dielectric layer;
step12, etching the third dielectric layer without mask and forming a side wall on the second dielectric layer and the side wall of the polysilicon;
step13, etching the source region to form a contact groove, wherein the contact groove penetrates through the source region to the body region;
step14, implanting boron ions into the contact groove to form a contact area of the body region;
and Step15, performing metal sputtering or evaporation on the front surface of the wafer structure formed in the Step14 to form a metallization layer, wherein the metallization layer covers the contact region, the side wall and the second medium layer.
In a preferred embodiment, the substrate is heavily doped N-type semiconductor silicon, and the epitaxial region is lightly doped N-type semiconductor silicon.
As a preferred embodiment, the source region is heavily doped N-type semiconductor silicon.
In a preferred embodiment, the body region is formed by doping and implanting boron ions into the epitaxial region.
In a preferred embodiment, the first dielectric layer and the second dielectric layer are selected from silicon dioxide or silicon nitride; the first dielectric layer and the second dielectric layer are set to be of different material types.
In a preferred embodiment, the third dielectric layer is selected from silicon dioxide or silicon nitride.
As a preferred embodiment, in step6, the upper surface of the polysilicon after etching is higher than, lower than or even with the upper surface of the body region (epitaxial layer).
In step8, the surface of the second dielectric layer after etching is flush with or lower than the surface of the first dielectric layer.
As a preferred embodiment, in step15, the depth of the contact trench is greater than the depth of the source region until the body region under the source region is reached, but not beyond.
Another object of the present invention is to provide a novel self-aligned power Trench MOSFET, in which the Trench and the contact hole (contact Trench) are defined by a single mask, which can greatly reduce the Pitch of the Trench Pitch (i.e., the Pitch between adjacent Trench).
Drawings
FIG. 1 is a cross-sectional view of a prior art structure.
Fig. 2A is a structural diagram of a step in the prior art.
Fig. 2B is a structural diagram of another step in the prior art.
FIG. 3 shows the structure formed in Step1 of the present invention.
FIG. 4 shows the structure formed in Step2 of the present invention.
FIG. 5 shows the structure formed in Step3 of the present invention.
FIG. 6 shows the structure formed in Step4 of the present invention.
FIG. 7 shows the structure formed in Step5 of the present invention.
FIG. 8 shows the structure formed in Step6 of the present invention.
FIG. 9 shows the structure formed in Step7 of the present invention.
FIG. 10 shows the structure formed in Step8 of the present invention.
FIG. 11 shows the structure formed in Step9 of the present invention.
FIG. 12 shows the structure formed in Step10 according to the present invention.
FIG. 13 shows the structure formed in Step11 according to the present invention.
FIG. 14 shows the structure formed in Step12 according to the present invention.
FIG. 15 shows the structure formed in Step13 according to the present invention.
FIG. 16 shows the structure formed in Step14 according to the present invention.
FIG. 17 shows the structure formed in Step15 according to the present invention.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the invention and is incorporated in the context of a particular application. Various modifications, as well as various uses in different applications will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the practice of the invention may not necessarily be limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
Note that where used, the designations left, right, front, back, top, bottom, positive, negative, clockwise, and counterclockwise are used for convenience only and do not imply any particular fixed orientation. In fact, they are used to reflect the relative position and/or orientation between the various parts of the object. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be connected internally or indirectly between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those of ordinary skill in the art.
It is noted that, where used, further, preferably, still further and more preferably is a brief introduction to the exposition of the alternative embodiment on the basis of the preceding embodiment, the contents of the further, preferably, still further or more preferably back band being combined with the preceding embodiment as a complete constituent of the alternative embodiment. Several further, preferred, still further or more preferred arrangements of the belt after the same embodiment may be combined in any combination to form a further embodiment.
The invention is described in detail below with reference to the figures and specific embodiments. It is noted that the aspects described below in connection with the figures and the specific embodiments are only exemplary and should not be construed as imposing any limitation on the scope of the present invention.
In the following text description, the + of P + and N + represents heavy doping and high doping concentration; p-, N-represents light doping, and the doping concentration is low.
Referring to fig. 3, in step1, an epitaxial region 112 is epitaxially formed on a wafer substrate or substrate 111, and the wafer substrate or substrate 111 is made of a heavily doped N-type semiconductor (doped ions are phosphorus, i.e., N +), so that the wafer substrate or substrate 111 is expressed as an N + substrate 111. The epitaxial region 112 is a lightly doped N-EPI region 112, referred to as N-EPI for short.
Referring to fig. 4, in step2, a body region 114, i.e., Pbody region, is formed by boron ion implantation into the surface of the N-epi region 112.
Referring to fig. 5, in step3, a first dielectric layer 118 is deposited on the surface of the body region 114, wherein the first dielectric layer 118 is silicon dioxide or silicon nitride, and the thickness thereof is suitably determined, and the thickness thereof is typically 1 to 10 um.
Referring to fig. 6, in step4, a trench 12 is etched in the first dielectric layer 118 through photoresist-exposure-development-etching, the trench 12 penetrating through the body region 114 to the epitaxial region 112, i.e., the depth of the trench 12 needs to exceed the depth of the body region 114, and to penetrate into the epitaxial region 112, but not to exceed the depth of the epitaxial region 112. This is the only process step that requires a photolithographic process.
Referring to fig. 7, in step5, the Trench (i.e., Trench 12) is subjected to gate oxidation and doped polysilicon 121 deposition filling to form a gate, such that polysilicon 121 fills the Trench and polysilicon 121 covers first dielectric layer 118. Specifically, a gate insulating region 122 is formed between the polysilicon 121 and the Trench, and the gate insulating region 122 covers the bottom and the four peripheral walls of the Trench.
Referring to fig. 8, in step6, polysilicon 121 is removed from over first dielectric layer 118 by a maskless Etch (Etch Back), but to ensure that polysilicon 121 is fully embedded in trench 12. The upper surface of the polysilicon 121 is higher, lower or even with the upper surface of the body region 114 after etching.
Referring to fig. 9, in step7, a second dielectric layer 119 is deposited overlying first dielectric layer 118 and trench 12. The first dielectric layer 118 and the second dielectric layer 119 are selected from silicon dioxide or silicon nitride; the first dielectric layer 118 and the second dielectric layer 119 are set to different material types.
Referring to fig. 10, in step8, the second dielectric layer 119 is etched away from the first dielectric layer 118 by a maskless Etch (Etch Back) method, and only the second dielectric layer 119 is remained on the trench 12. After etching, the surface of the second dielectric layer 119 is flush with or lower than the surface of the first dielectric layer 118.
Referring to fig. 11, in step9, first dielectric layer 118 is completely removed, leaving the surface of body region 114 completely exposed.
Referring to fig. 12, in step10, Source regions 117, i.e., Source regions, are formed by doping ions in the body regions 114. Further, the doping is heavy N + type doping, namely, the doping is called an N + Source area. The source region 117 is heavily doped N-type semiconductor silicon.
Referring to fig. 13, in step11, a third dielectric 113 is deposited, the third dielectric 113 covering the N + Source region and the second dielectric layer 119.
Referring to fig. 14, in step12, the third dielectric 113 is etched and spacers 1131, i.e., spacers, are formed on the sidewalls of the second dielectric layer 119. The Spacer etching does not need a mask, the third dielectric layer on the surface of the wafer is etched, the Spacer is formed on the side face of the second dielectric layer, and the third dielectric 113 on the silicon surface of the wafer is completely etched.
Further, the third dielectric 113 is silicon dioxide or silicon nitride.
Referring to fig. 15, in step13, a contact trench is formed by dry etching in the N + Source region down to a depth greater than that of the N + Source region, and up to the Pbody region under the N + Source region, but not beyond the Pbody region, since the purpose is to achieve ohmic contact with the Pbody region, the contact trench passing through the N + Source region to the body region 114, providing a provision for ohmic contact with the body region 114.
Referring to fig. 16, in step14, boron ions are implanted into the contact trench with a doping profile that is heavily implanted to form the ohmic contact region 115 of the Pbody region.
Referring to fig. 17, in step15, metallization layer 116 is formed on the wafer structure formed in step14, thus connecting all N + regions, and metallization layer 116 forms a contact layer/contact, i.e., source contact.
While the present invention has been described in detail and with reference to the embodiments thereof as illustrated in the accompanying drawings, it will be apparent to one skilled in the art that various changes and modifications can be made therein. Therefore, certain details of the embodiments are not to be interpreted as limiting, and the scope of the invention is to be determined by the appended claims.
Claims (10)
1. A novel manufacturing method of a self-aligned power Trench MOSFET is characterized by comprising the following steps:
step 1: forming an epitaxial region on the positive upper surface of the substrate in an epitaxial manner;
step 2: implanting boron ions into the positive upper surface of the epitaxial region to form a body region;
step 3: depositing a first dielectric layer on the main body region;
step 4: etching the first dielectric layer to form a groove, wherein the groove penetrates through the main body region to the epitaxial region;
step 5: oxidizing the groove and filling polycrystalline silicon to form a grid, wherein the polycrystalline silicon covers the first dielectric layer;
step 6: etching the polycrystalline silicon on the first dielectric layer, wherein the surface of the polycrystalline silicon in the groove is required to be lower than the surface of the first dielectric layer, and the surface of the polycrystalline silicon can be parallel to the surface of the epitaxial layer, or lower than the surface of the epitaxial layer, or higher than the surface of the epitaxial layer;
step 7: depositing a second dielectric layer to cover the first dielectric layer and the polycrystalline silicon in the groove;
step 8: etching the second dielectric layer on the first dielectric layer, and only keeping the second dielectric layer on the groove polysilicon;
step 9: completely removing the first dielectric layer;
step 10: doping ions on the body region to form a source region;
step 11: depositing a third dielectric layer, wherein the third dielectric layer covers the source region and the second dielectric layer;
step12, etching the third dielectric layer without mask and forming a side wall on the second dielectric layer and the side wall of the polysilicon;
step13, etching the source region to form a contact groove, wherein the contact groove penetrates through the source region to the body region;
step14, implanting boron ions into the contact groove to form a contact area of the body region;
and Step15, performing metal sputtering or evaporation on the front surface of the wafer structure formed in the Step14 to form a metallization layer, wherein the metallization layer covers the contact region, the side wall and the second dielectric layer.
2. The method of claim 1, wherein the substrate is heavily doped N-type semiconductor silicon and the epitaxial region is lightly doped N-type semiconductor silicon.
3. The method of claim 1, wherein the source region is heavily doped N-type semiconductor silicon.
4. The method of claim 1, wherein the body region is formed by doping and implanting boron ions into the epitaxial region.
5. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are selected from silicon dioxide or silicon nitride; the first dielectric layer and the second dielectric layer are set to be different material types.
6. The method of claim 1, wherein the third dielectric layer is selected from silicon dioxide or silicon nitride.
7. The method of claim 1 wherein said polysilicon has an upper surface higher than, lower than or even with an upper surface of said body region (epitaxial layer) after etching in step 6.
8. The method of claim 1 wherein in step8, the surface of the second dielectric layer after etching is at or below the surface of the first dielectric layer.
9. The method of claim 1 wherein in step15, the contact trench has a depth greater than the depth of the source region until reaching the body region below the source region but not exceeding the body region.
10. A novel self-aligned power Trench MOSFET prepared by the preparation method as claimed in claims 1-9.
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| CN111370463A (en) * | 2018-12-26 | 2020-07-03 | 深圳尚阳通科技有限公司 | Trench gate power device and manufacturing method thereof |
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| CN111370463A (en) * | 2018-12-26 | 2020-07-03 | 深圳尚阳通科技有限公司 | Trench gate power device and manufacturing method thereof |
| CN110416211A (en) * | 2019-07-24 | 2019-11-05 | 上海朕芯微电子科技有限公司 | A kind of super-self-aligned power Trench MOSFET production method and structure |
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| 袁寿财,汪李明,祝咏晨: "IGBT全自对准栅挖槽工艺研究", 微电子学, no. 02 * |
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