CN113962373A - Method for realizing neuromorphic device with synapse and neuron functions - Google Patents

Method for realizing neuromorphic device with synapse and neuron functions Download PDF

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CN113962373A
CN113962373A CN202111385646.2A CN202111385646A CN113962373A CN 113962373 A CN113962373 A CN 113962373A CN 202111385646 A CN202111385646 A CN 202111385646A CN 113962373 A CN113962373 A CN 113962373A
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黄如
罗金
黄芊芊
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Abstract

The invention provides a method for realizing a neuromorphic device with synapse and neuron functions, and belongs to the technical field of neuromorphic devices in neuromorphic calculation. The invention connects the bottom electrode of the metal layer-ferroelectric layer-metal layer with the grid end of the N-type MOSFET in series to form a ferroelectric neuromorphic device, adjusts the area of the ferroelectric layer to be larger than the area of the NMOS grid, increases the depolarization field to obtain the polarization back-turning short-time relaxation characteristic, and ensures the long-time relaxation characteristic of the device by the wide ferroelectric domain distributed in the coercive field, thereby realizing the neuromorphic device with the functions of synapse and neuron. The invention can obviously reduce the hardware overhead, has CMOS process compatibility and is beneficial to the hardware realization of the large-scale highly interconnected impulse neural network.

Description

Method for realizing neuromorphic device with synapse and neuron functions
Technical Field
The invention relates to a physical implementation mode of a neuromorphic device in neuromorphic computing, in particular to a method for implementing the neuromorphic device with synapse and neuron functions.
Background
With the explosive development of information technology, human society has stepped into the era of "data explosion", and the exponentially increasing data volume each year has brought unprecedented pressure on data processing and calculation. Due to the architectural characteristics of the traditional von neumann computing architecture, due to the architecture characteristics of the memory separation, the transmission of data between the memory unit and the computing unit causes a great deal of power consumption and energy consumption waste, and the problem becomes more and more serious under the background that the information society and even the intelligent society are accompanied by huge data volume nowadays.
Researchers are inspired by a brain operation mode, a Neural Network (Neural Network) computing architecture is provided, a storage-computation-integrated and highly parallel distributed computing Network is constructed on the basis of a neuron-synapse-neuron connection mode, the processing efficiency of complex data is improved, and meanwhile the problems of power consumption and energy consumption caused by a memory wall in the traditional von Neumann computing architecture can be solved. In a classical Artificial Neural Network (Artificial Neural Network), the function of synapses and neurons is abstracted as numerical calculations: and performing dot multiplication on the input vector and the synaptic weight matrix, and obtaining an output activation value through an activation function. At present, the artificial neural network has shown the computational efficiency superior to the traditional general computing unit in the applications of image recognition, natural language processing, automatic driving and the like, but compared with the human brain, the artificial neural network still has the problems of long learning training period, high computing hardware cost and the like. The Neural morphology Computing (Neural Computing) further simulates the human brain on the basis of a Neural Network Computing architecture, information is expressed and transmitted in a pulse form, and the constructed pulse Neural Network (Spiking Neural Network) has asynchronous and event-driven characteristics, can further reduce the difference between machine intelligence and human brain intelligence, and has the advantages of high energy efficiency, high learning speed, strong generalization capability and the like.
Unlike synapses and neuronal functions in artificial neural networks. Synapses in the spiking neural network have Short-term plasticity (STP) and Long-term plasticity (LTP), which is beneficial for the biological neural network to complete continuous learning and Long-term memory functions. The neuron in the impulse neural network is responsible for integrating the input impulse signal and outputting a new impulse signal to transmit information, the working form of the neuron simulates biological neurons, the processing process of the signal is embodied on the change of membrane potential, the basic function of the impulse neurons can be abstracted to leakage-carrying accumulation and Fire (LIF), and the neuron is also the most widely applied bionic impulse neuron model in the neuromorphic calculation.
The neuromorphic calculation can completely get rid of the limitation of the bottleneck of the memory wall only by realizing the hardware of the whole network. At present, many research institutions and enterprises have developed various neuromorphic chips for hardware implementation of neuromorphic computation, however, in the existing neuromorphic computation hardware scheme, hardware synapses and neurons, which are basic units of a network, are still built mainly based on a conventional CMOS circuit, and simulation of functions of the neuromorphic computation often depends on a circuit module composed of a plurality of MOSFET devices and capacitors, so that the problems of high hardware overhead, high circuit energy consumption and the like exist, high-density and large-scale integration is not facilitated, and the original power consumption and energy consumption advantages brought by the framework level of the network may be lost. Many researches propose that STP and LTP functions of bionic synapses and LIF functions of neurons are realized by using a phase-change memory device, a silver ion diffusion type memristor and an ion gate device, but extra complex reset circuits are often needed, the problem of compatibility with a CMOS (complementary metal oxide semiconductor) process is faced, and the large-scale integration is not facilitated.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a method for realizing a neuromorphic device with synapse and neuron functions, and the ferroelectric neuromorphic device provided by the invention can obviously reduce hardware overhead and has process compatibility on the premise of realizing Short-term plasticity (STP), Long-term plasticity (LTP) and leakage cumulative distribution (LIF) of synapses.
In order to realize the purpose of the invention, the technical scheme of the invention is as follows:
a method for realizing the functions of synapse and neuron of a neuromorphic device is characterized in that a bottom electrode of a metal layer-ferroelectric layer-metal layer (MFM) is connected in series with a gate end of an N-type MOSFET (NMOS) to form the MFMFMFET, wherein a top electrode of the MFM is used as an input end of the MFMFET and receives an input voltage excitation signal VGS(ii) a N-type MOSFET channel conductance profileThe state is used as MFMFET output, the source end of the N-type MOSFET is connected to GND, and the drain end of the N-type MOSFET is applied with voltage VDAcquiring channel current as an output state; ferroelectric layer depolarization field strength of mfmfmfet:
Figure BDA0003367027780000021
in formula (1): edep(t) -the depolarization field strength of the ferroelectric layer; p (t) -ferroelectric polarization magnitude; in the depolarization process, the ferroelectric polarization amount and the depolarization field strength change along with time, wherein t represents variable time; epsilon0-vacuum dielectric constant; epsilonFe-the relative dielectric constant of the ferroelectric layer; cIS-the capacitance size of the N-type MOSFET; cFeAnd adjusting the area of the MFM ferroelectric layer to be larger than the area of the N-type MOSFET gate to obtain a high ratio of the capacitance of the MFM ferroelectric layer to the capacitance of the N-type MOSFET dielectric layer, and realizing the functions of synapse and neuron of the neuromorphic device by utilizing a short-term back-turn relaxation process and a long-term retention characteristic in the time-dependent dynamic depolarization field and the change process of the ferroelectric polarization quantity.
The ferroelectric layer can adopt HfO2 doped with Zr (HZO) and HfO2Doped with Al (HfAlO), HfO2Doping Si, HfO2Doping HfO such as Y2A doped ferroelectric material.
The MFM ferroelectric layer area (A)FE) And N type MOSFET gate area (A)MOS) The ratio of (A) to (B): a. theFE/AMOSGreater than 1 to obtain an enhanced depolarization field; and A isFE/AMOSLess than 18, avoiding the need for excessively high operating voltages to flip the ferroelectric.
The MFM ferroelectric layer has an area larger than 1 μm2The obtained ferroelectric layer has a large number of ferroelectric domains and a wide distribution of multi-domain coercive fields.
The invention connects the bottom electrode of metal layer-ferroelectric layer-metal layer (MFM) in series with the grid end of N-type MOSFET (NMOS), the grid capacitance of NMOS transistor is used as the load of MFM ferroelectric layer, after applying excitation to make the polarization of ferroelectric layer turn over, in the short time after removing excitation, under the action of depolarization,the amount of iron polarization is gradually reduced, and the intensity of depolarization field is reduced at the same time until the intensity of depolarization field can not make the ferroelectric layer polarization reverse, and the polarization is maintained for a long time; by increasing the ratio of ferroelectric layer area to dielectric layer area, the Depolarization field is enhanced, short-term and long-term characteristics are simultaneously realized on one device, and the Depolarization field (E) is utilizeddep) Under the action of a Back-switching relaxation mechanism (Back-switching) of ferroelectric polarization in a short time, the STP function of synapse, the leakage characteristic (Leaky viewer) of neurons and a reset function are realized at the same time; the long-time retention characteristic of ferroelectric spontaneous polarization is utilized to realize the LTP function of synapse; the accumulation and turnover characteristics of ferroelectric polarization under continuous pulse excitation are utilized to realize the membrane potential accumulation characteristics of the neuron; the pulse-emitting function of the neuron is realized by utilizing the threshold switching characteristic of the transistor.
The invention has the following technical effects:
when low-voltage pulse excitation is applied, the ferroelectric domain with lower coercive field can be turned over in the period of high voltage level, after the pulse action, under the action of depolarization field, the ferroelectric domain with lower coercive field can be turned over in depolarization field EdepGradually turning back under the action of the force to simulate the short-time relaxation property of the organism; when voltage pulse with higher amplitude is applied for excitation, the ferroelectric domain with higher coercive field can be reversed at high level of pulse, and after pulse action, the depolarization field E lower than the coercive field can be obtaineddepThe back of the body cannot be turned over, the polarization state can be maintained on a long-time scale, and the long-time relaxation characteristic of a living being is simulated; in the neuromorphic device, the ferroelectric polarization adjusts the threshold voltage (V) of the deviceTH) I.e., to adjust the channel conductance state. Compared with the traditional CMOS circuit-based implementation mode, the ferroelectric neuromorphic device with the synapse and the neuron functions has the advantages that the holding characteristic of spontaneous polarization of a ferroelectric domain with a higher coercive field and the modulation effect on the conductance of a device channel are realized, the hardware cost is obviously reduced, and the long-term plasticity of the synapse is realized without a large-area SRAM circuit. The ferroelectric neuromorphic device with synapse and neuron functions can utilize ferroelectric polarization accumulation in an MFM and NMOS series structure under the action of continuous pulsesThe method is particularly novel, realizes the accumulation characteristic of the membrane potential of the biological neuron on an excitation signal, and realizes the leakage characteristic and the reset function of the neuron by utilizing a polarization back flip mechanism under the action of a depolarization field without the voltage action. Compared with the traditional CMOS realization mode, the STP and LTP functions of synapses and the LIF functions of neurons are realized on the MFM and NMOS series structure, the hardware cost is obviously reduced, an extra circuit based on large-area dielectric capacitance is not needed to simulate the short-time relaxation characteristics of biological synapses and neurons, and a complex storage unit is not needed to realize the long-time relaxation characteristics of synapses; compared with a phase change memory device, a silver ion diffusion memristor and an ion gate device, the method has the advantage of being compatible with a CMOS (complementary metal oxide semiconductor) process, and is beneficial to large-scale integration.
Drawings
FIG. 1 is a diagram of a neuromorphic device with both synaptic and neuronal functions according to the present invention.
Detailed Description
The invention will be further elucidated by means of specific embodiments in the following with reference to the drawing.
This example uses Hf with 5nm thickness0.5Zr0.5O2Ferroelectric materials are used to implement the ferroelectric layer in the MFM.
As shown in fig. 1, the present example is a ferroelectric neuromorphic device with both synapse and neuron functions, and its structure includes back-end-process compatible metal layer-ferroelectric layer-metal layer (MFM) and NMOS; wherein the MFM bottom electrode is connected with the gate terminal of the NMOS; the ferroelectric layer has a large area, namely the ratio of the area of the ferroelectric layer to the area of the NMOS gate is larger than 1, so that a depolarization field is increased to obtain back flip characteristics, and a ferroelectric domain with wide coercive field distribution is obtained to ensure the long-time relaxation characteristics of the device; the gate terminal of the series structure of MFM and NMOS receives the excitation signal, the source terminal is connected to GND, and the drain terminal is connected to the working voltage VDChannel current as output I of ferroelectric neuromorphic deviceout. The MFM and NMOS series device structure mimics the short-term plasticity, long-term plasticity of biological synapses, and the leakage, accumulation, firing and resetting functions of biological neurons.
The present embodiment illustrates the beneficial effects of the present invention:
1. under a synapse operation mode, outputting an initial channel current by a ferroelectric neuromorphic device in an MFM and NMOS series structure in an initial state; applying a programming voltage pulse with low amplitude at the gate end, switching the ferroelectric domain with lower coercive field, and after the pulse is removed, gradually reducing the output current of the device along with the time due to the ferroelectric polarization back-switching relaxation process brought by the depolarization field, recovering the initial output current intensity, and simulating the short-time plasticity (STP) of biological synapse; the amplitude of a programming voltage pulse acting on a gate end is increased, so that a ferroelectric domain with a higher coercive field can be subjected to polarization reversal in a pulse high-level period, after the pulse is removed, a part of the ferroelectric domain with a lower coercive field is gradually reversed back under the action of a depolarization field, the intensity of the depolarization field is gradually reduced along with the reduction of polarization, the polarization state is finally converged, the polarization state of the ferroelectric domain with the higher coercive field is maintained, the state of the device is changed and maintained, and the long-term plasticity (LTP) of biological synapse is simulated. In summary, the ferroelectric neuromorphic device with the MFM and NMOS series structure can achieve STP and LTP characteristics of biological synapses.
2. In the neuron operation mode, initially, in the MFM and NMOS series structure, only part of polarization is reversed in the positive direction and is at the threshold voltage (V)TH) A higher resting state; under the action of continuous voltage pulses with lower amplitude, the ferroelectric domain with lower coercive field is gradually overturned and accumulated, and the accumulation effect of the membrane potential of the biological neuron on excitation is simulated; at pulse intervals, due to the action of a depolarization field, the polarization part subjected to accumulative inversion is subjected to back inversion to simulate the potential leakage characteristic of the biological neuron membrane; sufficient continuous pulsing to cause device VTHWhen the amplitude is low enough, the next low-amplitude pulse makes the channel of the device completely conducted to generate current pulse output; after the pulse is sent, in a period without input action, accumulated polarization inversion gradually turns back due to depolarization, so that iron polarization in the MFM and NMOS series structure returns to an initial state, the reset function of neuron is simulated, and the complete LIF function is realized. In summary, the proposed ferroelectric neuromorphic device with MFM and NMOS series structure can realize STP and LTP of synapses and LIF function of neurons, compared with the traditional CMOS-based synapse circuitAnd a neuron circuit, which greatly reduces the hardware cost and realizes the function of integrating synapses and neurons on a single device; compared with a phase change memory device, a memristor and an ion gate device, the phase change memory device has the advantage of being compatible with a CMOS (complementary metal oxide semiconductor) process, and has the potential of large-scale integration.
Finally, it is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.

Claims (5)

1. A method for realizing a neuromorphic device with synapse and neuron functions is characterized in that a bottom electrode of a metal layer-ferroelectric layer-metal layer MFM is connected in series with a grid end of an N-type MOSFET to form a ferroelectric neuromorphic device MFMFMFMFET, wherein a top electrode of the MFM serves as an input end of the MFMFMFMFET and receives an input voltage excitation signal VGS(ii) a The conduction state of the N-type MOSFET channel is output as MFMFMFET, the source end of the N-type MOSFET is connected to GND, and the drain end of the N-type MOSFET is applied with a voltage VDAcquiring channel current as an output state; ferroelectric layer depolarization field strength for MFMFET
Figure FDA0003367027770000011
In the formula: edep(t) -the depolarization field strength of the ferroelectric layer; p (t) -ferroelectric polarization magnitude; in the depolarization process, the ferroelectric polarization amount and the depolarization field strength change along with time, wherein t represents variable time; epsilon0-vacuum dielectric constant; epsilonFe-the relative dielectric constant of the ferroelectric layer; cIS-the capacitance size of the N-type MOSFET; cFeThe capacitance of the MFM ferroelectric layer is adjusted to be larger than the gate area of the N-type MOSFET so as to obtain a high ratio of the capacitance of the MFM ferroelectric layer to the capacitance of the dielectric layer of the N-type MOSFET, and a short-term back-flip relaxation process and a long-term back-flip relaxation process in the time-dependent dynamic depolarization field and the change process of the amount of iron polarization are utilizedKeeping the characteristics and realizing the functions of synapse and neuron of the nerve morphological device.
2. The method of claim 1, wherein the ferroelectric layer of the MFM is selected from HfO2 zr (hzo), HfO, and wherein the mgo of the MFM is doped with HfO22Doped with Al (HfAlO), HfO2Doping Si, HfO2Doping HfO such as Y2A doped ferroelectric material.
3. The method of claim 1, wherein the metal layer of the MFM is a TaN material or a TiN electrode material.
4. The method of implementing a neuromorphic device with both synaptic and neuronal functionality as in claim 1, wherein the MFM ferroelectric layer has an area (a)FE) And N type MOSFET gate area (A)MOS) The ratio of (A) to (B): a. theFE/AMOSGreater than 1 to obtain an enhanced depolarization field; and A isFE/AMOSLess than 18, avoiding the need for excessively high operating voltages to flip the ferroelectric.
5. The method of claim 1, wherein the MFM ferroelectric layer has an area greater than 1 μ ι η2The obtained ferroelectric layer has a large number of ferroelectric domains and a wide distribution of multi-domain coercive fields.
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