CN112381217B - Method for realizing excitation and inhibition functions of synapse - Google Patents
Method for realizing excitation and inhibition functions of synapse Download PDFInfo
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- CN112381217B CN112381217B CN202011228618.5A CN202011228618A CN112381217B CN 112381217 B CN112381217 B CN 112381217B CN 202011228618 A CN202011228618 A CN 202011228618A CN 112381217 B CN112381217 B CN 112381217B
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Abstract
The invention provides a method for realizing excitation and inhibition functions of synapses, belonging to the technical field of synapse hardware in neuromorphic computation. The method adopts a ferroelectric transistor FeFET and a PMOS to form a synapse circuit; the FeFET realizes plasticity and memory characteristics of synapses, a gate terminal of the FeFET serves as a programming (or erasing) port, a source terminal is biased to be inhibition voltage, and a drain terminal is connected to a drain terminal of the PMOS and serves as a synapse voltage output terminal; the source end of the PMOS is used as the pulse input end of a preceding stage neuron, and the grid end of the PMOS is biased at a fixed power supply voltage; when the neuron in the front stage delivers voltage output, the PMOS and FeFET channel resistance voltage division generates synaptic excitatory or inhibitory voltage output. Compared with the traditional MOSFET-based implementation mode, the invention can obviously reduce the hardware overhead, has stronger driving capability and is beneficial to the hardware implementation of large-scale highly interconnected neural networks.
Description
Technical Field
The invention belongs to the technical field of synapses in neuromorphic computing, and particularly relates to a method for realizing synapses with excitation and inhibition functions based on ferroelectric transistors.
Background
With the vigorous development of information technology, the human society has stepped into the era of "data explosion", and the exponentially growing data volume each year puts unprecedented pressure on the processing and calculation of data. Due to the architectural characteristics of the traditional von neumann computing architecture, due to the architecture characteristics of the memory separation, the transmission of data between the memory unit and the computing unit causes a great deal of power consumption and energy consumption waste, and the problem becomes more and more serious under the background that the information society and even the intelligent society are accompanied by huge data volume nowadays.
Researchers are inspired by a brain operation mode, a neural network computing architecture is provided, a storage-computation-integrated and highly parallel distributed computing network is constructed on the basis of a neuron-synapse-neuron connection mode, the processing efficiency of complex data is improved, and meanwhile the problems of power consumption and energy consumption caused by a memory wall in the traditional von Neumann computing architecture can be solved. The core of the neural network computation which is operated in parallel by a processing mode integrating storage and computation is high-density synaptic connection among neurons, a storage mechanism of various states and the storage capacity of data, so that the neural network computation circuit based on synapses has the potential of achieving artificial intelligence in the true sense.
In an artificial neuromorphic computing system, synapses realize connection relationships with memory characteristics between neurons in a network, and are responsible for transmitting and modulating information interaction between the neurons. The basic function of synapse can be abstracted as weight of excitation and inhibition to express the action relationship of preceding stage neuron to excitation or inhibition of following stage neuron. The neuromorphic calculation can completely get rid of the limitation of the bottleneck of the memory wall only by realizing the hardware of the whole network. At present, many research institutions and enterprises have developed various neuromorphic chips for hardware implementation of neuromorphic computation, however, synapses, which are basic units of a network, are still built mainly based on a traditional CMOS circuit, and the problems of high hardware overhead, high circuit energy consumption and the like exist, which are not favorable for high-density and large-scale integration.
And superposing the ferroelectric material on the gate oxide layer of the MOSFET to obtain the ferroelectric transistor FeFET. At this point, the non-volatile spontaneous polarization of the ferroelectric material will induce additional charge on the gate oxide of the MOSFET, resulting in a change in the device channel conductance. The electric charge induced on the MOSFET gate oxide layer by the ferroelectric polarization electric charge can also be equivalent to an additional gate voltage, and the change of the threshold voltage of the device can be reflected on the whole FeFET. The FeFET has the advantages that the polarization intensity can continuously adjust the characteristic and the nonvolatile characteristic, the function of synapses can be intuitively simulated, and the possibility is provided for physical realization of the synapses.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a method for realizing synapses with excitation and inhibition functions based on a ferroelectric transistor; compared with the traditional MOSFET-based implementation mode, the method provided by the invention has the advantages that the hardware overhead is obviously reduced on the premise of realizing the plastic excitation and synapse inhibition functions, and the large-scale highly interconnected neural network is facilitated.
The technical scheme provided by the invention is as follows;
a method for realizing excitation and inhibition functions of synapses adopts a ferroelectric transistor FeFET and a P-type MOSFET (PMOS) to form a synapse circuit; the FeFET realizes the plasticity and the memory characteristic of synapse, the grid end of the FeFET is used as a programming (or erasing) port, the source end of the FeFET is biased at fixed inhibition voltage intensity, and the drain end of the FeFET is connected with the drain end of the PMOS; the source end of the PMOS is used as the positive voltage pulse input end of the preceding stage neuron, and the grid end is biased at a fixed power supply voltage; when the neuron in the front stage delivers voltage output, the PMOS and FeFET channel resistance voltage division generates excitatory or inhibitory synaptic voltage output.
The ferroelectric transistor FeFET used in the synapse circuit with excitation and inhibition functions based on the ferroelectric transistor has the following characteristics: the ferroelectric polarization switching effect is obvious when gate voltage pulse is applied, namely, the channel conductance of the FeFET device can be adjusted by applying voltage excitation on the gate, so that the plastic characteristic is embodied; the ferroelectric polarization strength is maintained when no gate voltage exists, and the nonvolatile characteristic is embodied; the FeFET used in the synapse circuit with excitation and inhibition functions based on the ferroelectric transistor can adopt perovskite ferroelectric (PZT, BFO, SBT), ferroelectric polymer (P (VDF-TrFE)) and the likeFerroelectric materials or HfO2Zr (HZO) and HfO doped2Doped with Al (HfAlO), HfO2Doping Si, HfO2Doping HfO such as Y2The doped ferroelectric material can be any FeFET device based on MFMIS, MFIS, MFS and other structures and having the above typical characteristics.
The synapse circuit based on the ferroelectric transistor and having excitation and inhibition functions has the advantages and corresponding principles that:
1. the synaptic circuit with excitation and inhibition functions based on the ferroelectric transistor realizes plasticity and retention characteristics of synaptic weights by utilizing the characteristics that the ferroelectric polarization of the FeFET is gradually reversed under the action of gate programming (or erasing) voltage and the ferroelectric polarization strength is retained after the excitation is removed.
2. The synaptic circuit with excitation and inhibition functions based on the ferroelectric transistor realizes the on-line regulation of synaptic weight by utilizing the three-terminal characteristic of the FeFET, namely, the output strength of synapse can be regulated and controlled in real time through a FeFET gate in the network operation process.
3. The synapse circuit with excitation and inhibition functions based on the ferroelectric transistor utilizes the characteristic that FeFET channel conductance is modulated by polarization intensity to be connected with PMOS in series to form a voltage division circuit, when a preceding level neuron inputs a voltage pulse, synapse output voltage between excitation type voltage and inhibition type voltage amplitude is generated at an output end, and synapse connection with excitation and inhibition functions can be realized only by two transistors. Compared with the traditional CMOS-based implementation mode, the hardware overhead is obviously reduced.
Drawings
FIG. 1 is a schematic diagram of a synapse circuit with excitatory and inhibitory functions based on ferroelectric transistors according to the present invention.
Detailed Description
The invention will be further elucidated by means of specific embodiments in the following with reference to the drawing.
The present example uses Hf0.5Zr0.5O2A ferroelectric transistor FeFET of ferroelectric material, wherein the spontaneous polarization of the ferroelectric material induces additional charge on the gate oxide of the PMOS, resulting in a change in the device channel conductance. The ferroelectric polarization charges induce charges on the PMOS gate oxide layer to be equivalent to an additional gate voltage, which is reflected on the entire FeFET to be reflected as a change in the device channel conductance.
As shown in FIG. 1, the synapse circuit with excitation and inhibition functions based on ferroelectric transistors of the present embodiment includes ferroelectric transistors FeFET and PMOS; wherein, the FeFET is used for realizing the plasticity and the keeping characteristic of synapse, and a programming (or erasing) pulse acts on a FeFET gate; the FeFET is placed in a high threshold voltage state by a programming pulse of a negative voltage, the channel conductance is reduced, and the FeFET is placed in a low threshold voltage state by an erasing pulse of a positive voltage, the channel conductance is increased; the source terminal of the FeFET is connected to a fixed suppression voltage VinhibitionThe source end of the PMOS is connected with the source end of the PMOS to form a series structure; the gate terminal of PMOS is connected to positive fixed voltage to make the conductance of the device between high and low conductance states of FeFET, and the source terminal receives positive voltage pulse signal V transmitted from the preceding neuronin(ii) a The voltage division of the channel conductance of PMOS and FeFET generates synaptic voltage output Vout，VoutThe voltage amplitude is between the excitation type positive voltage and the inhibition type negative voltage; is characterized in that when synapses are in excitatory type, positive voltage pulse signals transmitted by preceding neurons are transmitted to synapse output terminals V through PMOS with relatively low resistanceoutRealizing the transmission of excitation; when synapses are placed in inhibitory form, V of synapsesoutIs pulled down to an inhibiting voltage VinhibitionAnd inhibitory connections between neurons are realized.
The present embodiment illustrates the beneficial effects of the present invention:
1. ferroelectric polarization of the FeFET is reversed in relation to both electric field and time, gradually reversed by adjusting the number of negative voltage programming (or positive voltage erase) pulses of the FeFET, the polarization being able to be maintained after the pulses are removed; the ferroelectric polarization can continuously modulate the channel conductance of the FeFET, thereby regulating the voltage division relation between the FeFET and the PMOS and continuously regulating the output voltage V of synapseoutThe amplitude value.
2. Since the FeFET is a three-terminal device, in the network operation process, the connection weight value can be adjusted in real time by applying programming (or erasing) pulse to the gate terminal of the FeFET, so that the online learning of the neural network is realized.
3. When the high level of the voltage pulse transmitted by the front-stage neuron acts on synapse, the grid end is biased to be opened by PMOS with a fixed voltage value; applying a programming pulse with a sufficient negative voltage to make the ferroelectric polarization direction upward (from channel to gate), placing the FeFET in a low-conductance state, and making the synapse output VoutIs an excitatory potential consistent with a pulsed high-level potential delivered by a preceding neuron, and the state of synapses can be maintained; on the basis, a positive voltage erasing pulse is applied to gradually turn the ferroelectric polarization downwards, and the gradually changed ferroelectric polarization state can still be maintained when the gate voltage is removed in the process, so that the channel conductance of the FeFET can be continuously changed, and the FeFET is gradually switched from the state that the conductance is far lower than the starting conductance of the PMOS to the state that the conductance is far higher than the starting conductance of the PMOS; synaptic output V when the preceding neuron delivers a high level of the pulseoutGradually switching from excitatory to inhibitory potentials. When synapses are made suppressive, the synapses output a suppressive voltage VinhibitionTo express inhibitory interactions between pre-and post-neurons. Compared with the traditional CMOS realization mode based on SRAM or large-area capacitor, the hardware cost of synapse with excitation and inhibition functions is greatly reduced.
Finally, it is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.
Claims (4)
1. A method for realizing excitation and inhibition functions of synapses is characterized in that a synapse circuit is formed by ferroelectric transistors FeFET and P-type MOSFETs; wherein, the ferroelectric transistor FeFET realizes the plasticity and memory property of synapse; the grid end of the ferroelectric transistor FeFET is used as a programming or erasing end, the source end of the ferroelectric transistor FeFET is biased to be fixed inhibition type voltage, and the drain end of the ferroelectric transistor FeFET is connected to the drain end of the P-type MOSFET and used as a synaptic voltage output end; the source end of the P-type MOSFET is used as the pulse input end of the preceding stage neuron, and the grid end of the P-type MOSFET is biased at a fixed power supply voltage; when the neuron in the front stage delivers voltage output, the channel resistance voltage division of the P-type MOSFET and the ferroelectric transistor FeFET generates synaptic output with excitation and inhibition functions.
2. The method of claim 1, wherein the P-type MOSFET load is implemented by resistive devices, including resistors, memristors, NMOS devices.
3. The method of claim 1, wherein the ferroelectric transistor FeFET device is based on an MFMIS, MFIS, or MFS structure.
4. The method of claim 1, wherein the FeFET device is made of perovskite ferroelectric, ferroelectric polymer or HfO2 doped with Zr, HfO2 doped with Al, HfO2 doped with Si, HfO2 doped with Y ferroelectric material.
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