CN113960435B - Fault arc signal processing circuit and single-phase fault arc detector adopting same - Google Patents
Fault arc signal processing circuit and single-phase fault arc detector adopting same Download PDFInfo
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- CN113960435B CN113960435B CN202111180639.9A CN202111180639A CN113960435B CN 113960435 B CN113960435 B CN 113960435B CN 202111180639 A CN202111180639 A CN 202111180639A CN 113960435 B CN113960435 B CN 113960435B
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Abstract
The invention discloses a fault arc signal processing circuit and a single-phase fault arc detector adopting the same, wherein the fault arc signal processing circuit converts voltage sampling signals into voltage sine wave signals and voltage square wave signals respectively through a voltage signal processing circuit and outputs the voltage sine wave signals and the voltage square wave signals to a processor, the processor can accurately identify the voltage characteristics of a fault arc based on the voltage sine wave signals and the voltage square wave signals, meanwhile, current sampling signals are converted into current sine wave signals, current square wave signals, current flat shoulder pulse signals and current high-frequency pulse signals respectively through a current signal processing circuit and then output the current characteristics of the fault arc, particularly the relevant characteristics of the flat shoulder of the fault arc current, and the single-phase fault arc can be detected accurately.
Description
Technical Field
The invention relates to the technical field of fault arc detection, in particular to a fault arc signal processing circuit, and in addition, the invention also particularly relates to a single-phase fault arc detector adopting the fault arc signal processing circuit.
Background
Fault arcs are common potential safety hazards in electric appliance lines, generally occur at the positions of poor insulation or poor contact of the lines, and also can occur at loose wire connection positions and aged or damaged lines, so that the accurate detection of fault arcs existing in power utilization lines is very important for power utilization safety.
As shown in fig. 1 and 2, fig. 1 is a normal current waveform, and fig. 2 is a fault arc current waveform, and as can be seen from comparing the current waveforms of fig. 1 and 2, the fault arc current generally has the following characteristics: 1. the zero break phenomenon exists in each half cycle of the fault arc current, namely, the waveform of the fault arc current has a flat shoulder; 2. the rate of rise of the fault arc current is generally higher than the normal current, and the current has abrupt changes every half cycle, the abrupt changes are random, and so on. In addition, when a fault arc occurs, the line voltage is suddenly dropped, and the voltage waveform is close to a rectangle. The national standard "GB14287.4-2014" clearly describes the standards for detecting fault arcs, in which a fault arc of at most 9 or less half cycles or a fault arc of at least 14 half cycles per second is generated during the detection process, and a micro arc having an arc duration of not more than 0.42ms or a current value of not more than 5% of a rated current value is not counted as an arc. Therefore, accurately extracting the fault arc signal is critical for fault arc detection based on the current and voltage characteristics of the fault arc.
Disclosure of Invention
The invention provides a fault arc signal processing circuit and a single-phase fault arc detector adopting the same, which can accurately extract a fault arc signal and ensure the accuracy of fault arc detection.
According to an aspect of the present invention, there is provided a fault arc signal processing circuit comprising:
the voltage signal processing circuit is used for respectively converting the voltage sampling signals into voltage sine wave signals and voltage square wave signals and then outputting the voltage sine wave signals and the voltage square wave signals to the processor;
and the current signal processing circuit is used for respectively converting the current sampling signals into current sine wave signals, current square wave signals, current flat shoulder pulse signals and current high-frequency pulse signals and then outputting the current sine wave signals, the current square wave signals, the current flat shoulder pulse signals and the current high-frequency pulse signals to the processor.
Further, the voltage signal processing circuit comprises a voltage differential amplifying circuit and a voltage shaping circuit, the voltage differential amplifying circuit is used for performing primary amplification processing on the voltage sampling signal and then outputting the voltage sampling signal, and the voltage shaping circuit is used for sequentially performing secondary amplification processing and shaping processing on the voltage sine wave signal subjected to the primary amplification processing, converting the voltage sine wave signal into a 3.3V voltage square wave signal and then outputting the voltage square wave signal.
Further, the voltage differential amplifying circuit includes a resistor R14, a resistor R16, a resistor R13, a capacitor C20, a resistor R22, a differential amplifier U1D, a resistor R19, a resistor R20, and a capacitor C19, where first ends of the resistor R14 and the resistor R16 are used for accessing a voltage sampling signal, a first end of the capacitor C20 is used for accessing a 5V power supply voltage, a second end of the resistor R14 is connected to a first end of the resistor R13 and an inverting input end of the differential amplifier U1D, a second end of the capacitor C20 is connected to a first end of the resistor R22, a second end of the resistor R16 is connected to a second end of the resistor R22 and a non-inverting input end of the differential amplifier U1D, an output end of the differential amplifier U1D is connected to a second end of the resistor R13, a first end of the capacitor C19, and a voltage shaping circuit, a second end of the capacitor C19 is connected to a second end of the resistor R19, a first end of the resistor R20, a processor, a first end of the resistor R19 is grounded, and a second end of the resistor R20 is used for accessing a 3.3V power supply voltage.
Further, the voltage shaping circuit includes a resistor R18, a differential amplifier U1C, a resistor R17, a capacitor C18, a nand gate U3A, and a resistor R12, a first end of the resistor R18 is connected to an output end of the voltage differential amplifier circuit, a second end of the resistor R18 is connected to a non-inverting input end of the differential amplifier U1C, an inverting input end of the differential amplifier U1C is grounded, an output end of the differential amplifier U1C is connected to a first end of the resistor R17, a second end of the resistor R17 is connected to a first end of the capacitor C18 and two input ends of the nand gate U3A, respectively, a second end of the capacitor C18 is grounded, an output end of the nand gate U3A is connected to a first end of the resistor R12 and the processor, and a second end of the resistor R12 is used for receiving a 3.3V power supply voltage, the voltage sine wave signal after primary amplification is secondarily amplified by the differential amplifier U1C, and then the voltage sine wave signal after secondary amplification is shaped by the nand gate U3A, and converted into a 3V voltage signal, so as to be recognized by the processor.
Furthermore, the current signal processing circuit comprises a flat shoulder pulse signal extraction circuit and a high-frequency pulse signal extraction circuit, the flat shoulder pulse signal extraction circuit is used for converting the current sampling signal into a current sine wave signal, a current square wave signal and a current flat shoulder pulse signal respectively and then outputting the current sine wave signal, the current square wave signal and the current flat shoulder pulse signal to the processor, and the high-frequency pulse signal extraction circuit is used for converting the current sine wave signal output by the flat shoulder pulse signal extraction circuit into a current high-frequency pulse signal and then outputting the current high-frequency pulse signal to the processor.
The shoulder pulse signal extraction circuit comprises a current differential amplification circuit, an automatic gain amplification circuit, a current positive square wave generation circuit, a current negative square wave generation circuit, a shoulder pulse generation circuit and a first current shaping circuit, wherein the current differential amplification circuit is used for carrying out primary amplification processing on a current sampling signal and outputting an amplified current sine wave signal to the processor and the automatic gain amplification circuit respectively, the automatic gain amplification circuit is used for carrying out secondary amplification processing on the current sine wave signal subjected to the primary amplification processing under the control of the processor and outputting the amplified current sine wave signal, the current positive square wave generation circuit is used for converting the current sine wave signal subjected to the secondary amplification processing into a 5.5V current positive square wave signal, the current negative square wave generation circuit is used for converting the current sine wave signal subjected to the secondary amplification processing into a current negative square wave signal, the shoulder pulse generation circuit is used for superposing the current positive square wave signal and the current negative square wave signal, extracting the current square wave signal, outputting the current negative square wave signal to the processor, and the first current shaping circuit is used for outputting a 5.5V positive square wave signal to the current positive square wave signal and outputting a 3.3V current signal.
Further, the current forward square wave generating circuit comprises a capacitor C25, a resistor R48, a resistor R59, a forward square wave generator U2B, a resistor R55, and a resistor R56, wherein the first end of the capacitor C25 and the forward input end of the forward square wave generator U2B are both connected to the automatic gain amplifying circuit, the second end of the resistor R48 is used for accessing a 5.5V power supply voltage, the first end of the resistor R48 is respectively connected to the first end of the resistor R59 and the reverse input end of the forward square wave generator U2B, the output end of the forward square wave generator U2B is respectively connected to the first end of the resistor R55, the first end of the resistor R56 and the first current shaping circuit, the second end of the resistor R59, the second end of the capacitor C25 and the second end of the resistor R55 are all grounded, and the second end of the resistor R56 is connected to the shoulder pulse generating circuit.
Further, the current negative square wave generating circuit includes a resistor R49, a resistor R60, a negative square wave generator U2C, a capacitor C23, a capacitor C27, and a resistor R58, an inverting input terminal of the negative square wave generator U2C is connected to the automatic gain amplifying circuit, a positive input terminal is connected to the first terminal of the resistor R49 and the first terminal of the resistor R60, the second terminal of the resistor R49, the first terminal of the capacitor C23, and the No. 4 pin of the negative square wave generator U2C are used for accessing +5.5V power supply voltage, the No. 11 pin of the negative square wave generator U2C and the first terminal of the capacitor C27 are used for accessing-5.5V power supply voltage, an output terminal of the negative square wave generator U2C is connected to the first terminal of the resistor R58 and the first current shaping circuit, and the second terminal of the resistor R58, the second terminal of the capacitor C23, the second terminal of the capacitor C27, and the second terminal of the resistor R60 are all grounded.
Further, the shoulder pulse generating circuit includes a resistor R53, a capacitor C24, an nand gate U3D, a capacitor C26, and a resistor R50, a first end of the resistor R53 is connected to the output end of the current negative square wave generating circuit, a second end of the resistor R53 is connected to the first end of the capacitor C24 and the first input end of the nand gate U3D, a second input end of the nand gate U3D is connected to the output end of the current positive square wave generating circuit and the first end of the capacitor C26, an output end of the nand gate U3D is connected to the processor and the second end of the resistor R50, the first end of the resistor R50 is used for accessing a 3.3V power voltage, and the second end of the capacitor C24 and the second end of the capacitor C26 are both grounded.
In addition, the invention also provides a single-phase fault arc detector which adopts the fault arc signal processing circuit.
The invention has the following effects:
according to the fault arc signal processing circuit, the voltage sampling signals are respectively converted into the voltage sine wave signals and the voltage square wave signals through the voltage signal processing circuit and then output to the processor, the processor can accurately identify the voltage characteristics of a fault arc based on the voltage sine wave signals and the voltage square wave signals, meanwhile, the current sampling signals are respectively converted into the current sine wave signals, the current square wave signals, the current flat shoulder pulse signals and the current high-frequency pulse signals through the current signal processing circuit and then output to the processor, the processor can accurately identify the current characteristics of the fault arc, particularly the relevant characteristics of the flat shoulder of the fault arc current, and the single-phase fault arc can be accurately detected.
In addition, the single-phase fault arc detector of the invention also has the advantages.
In addition to the objects, features and advantages described above, other objects, features and advantages of the present invention are also provided. The present invention will be described in further detail below with reference to the drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic diagram of a normal current waveform.
FIG. 2 is a schematic diagram of a fault arc current waveform.
Fig. 3 is a schematic block diagram of a single-phase fault arc detector in accordance with a preferred embodiment of the present invention.
Fig. 4 is a schematic diagram of a specific circuit structure of the power conversion circuit in fig. 1.
Fig. 5 is a specific circuit structure schematic diagram of the fault arc signal processing circuit in fig. 1.
Fig. 6 is a waveform schematic diagram of a fault arc current positive square wave signal generated by a current positive square wave generating circuit according to a preferred embodiment of the present invention.
Fig. 7 is a waveform schematic diagram of a fault arc current negative-going square wave signal generated by a current negative-going square wave generating circuit in accordance with a preferred embodiment of the present invention.
Fig. 8 is a schematic diagram of a flat-shoulder pulse generating circuit in accordance with a preferred embodiment of the present invention superimposing a fault arc current positive square wave signal and a fault arc current negative square wave signal.
Fig. 9 is a waveform diagram of the flat-shoulder pulse inversion signal synthesized by the flat-shoulder pulse generating circuit according to the preferred embodiment of the present invention.
Fig. 10 is a pin layout diagram of the processor of fig. 1.
Fig. 11 is a specific circuit configuration diagram of the sound alarm circuit in fig. 1.
Fig. 12 is a schematic diagram of a specific circuit structure of the crystal debugging interface circuit in fig. 1.
Fig. 13 is a schematic diagram of a specific circuit structure of the communication networking circuit in fig. 1.
Fig. 14 is a schematic circuit diagram of a specific circuit structure of the key indication circuit in fig. 1.
Fig. 15 is a specific circuit configuration diagram of the alarm trip circuit in fig. 1.
Fig. 16 is a schematic circuit diagram of a specific circuit structure of the communication interface circuit in fig. 1.
Fig. 17 is a specific circuit configuration diagram of the current signal input circuit in fig. 1.
Description of the reference numerals
10. A power conversion circuit; 11. a processor; 12. a fault arc signal processing circuit; 13. a current signal input circuit; 14. a crystal oscillator debugging interface circuit; 15. a communication networking circuit; 16. a sound alarm circuit; 17. a key indication circuit; 18. an alarm trip circuit; 19. a communication interface circuit; 101. a voltage sampling circuit; 102. a first voltage conversion circuit; 103. a second voltage conversion circuit; 104. a third voltage conversion circuit; 105. a fourth voltage conversion circuit; 121. a voltage signal processing circuit; 122. a current signal processing circuit; 123. a flat shoulder pulse signal extraction circuit; 124. a high-frequency pulse signal extraction circuit; 1231. a current differential amplifying circuit; 1232. an automatic gain amplification circuit; 1233. a current forward square wave generating circuit; 1234. a current negative square wave generating circuit; 1235. a flat shoulder pulse generating circuit; 1236. a first current shaping circuit; 1211. a voltage differential amplifying circuit; 1212. a voltage shaping circuit; 1241. a high-pass filter circuit; 1242. a low-pass filter circuit; 1243. a second current shaping circuit.
Detailed Description
The embodiments of the invention will be described in detail below with reference to the accompanying drawings, but the invention can be embodied in many different forms, which are defined and covered by the following description.
As shown in fig. 3, a preferred embodiment of the present invention provides a single-phase fault arc detector for detecting a single-phase fault arc, including:
the power supply conversion circuit 10 is connected with a live wire and a zero line of commercial power and is used for providing various power supply voltages and voltage sampling signals;
the current signal input circuit 13 is connected with the current transformer and is used for providing a current sampling signal;
the fault arc signal processing circuit 12 is respectively connected with the power conversion circuit 10 and the current signal input circuit 13, and is configured to output a voltage square wave signal, a voltage sine wave signal, a current square wave signal, a current flat shoulder pulse signal and a current high-frequency pulse signal after processing the voltage sampling signal and the current sampling signal;
and the processor 11 is connected with the power conversion circuit 10 and the fault arc signal processing circuit 12 respectively, and is configured to determine whether a single-phase fault arc exists based on the plurality of current signals and voltage signals output by the fault arc signal processing circuit 12 and in combination with a preset operation rule.
It can be understood that, in the single-phase fault arc detector of this embodiment, the fault arc signal processing circuit 12 processes the voltage sampling signal and the current sampling signal to obtain a voltage square wave signal, a voltage sine wave signal, a current square wave signal, a current flat shoulder pulse signal, and a current high-frequency pulse signal, and the processor 11 may accurately determine whether a single-phase fault arc exists in the power line based on the obtained multiple current signals and voltage signals and by combining a preset operation rule. The current shoulder pulse signal corresponds to a shoulder in a fault arc current waveform, relevant characteristics of the shoulder can be accurately identified by accurately extracting the current shoulder pulse signal from the current sampling signal, and further characteristics such as the number, duration and current value of the shoulder contained in the fault arc current waveform are comprehensively identified based on the current shoulder pulse signal and the current high-frequency pulse signal, when the number of the identified shoulders exceeds 14, the duration of each shoulder exceeds 420us, and the current value exceeds 5% of a rated current value, a single-phase fault arc is determined to exist in the power line, otherwise, the single-phase fault arc does not exist in the power line. The voltage square wave signal, the current square wave signal, the voltage sine wave signal and the current sine wave signal are more used as trigger signals, when the processor 11 identifies that the signals are abnormal, the fault arc detection function is started, namely, the current flat shoulder pulse signal and the current high-frequency pulse signal are sampled, so that the sensitivity of the detector is ensured, the accuracy of the detector is improved, and the false alarm rate is reduced. It can be understood that the specific judgment rule is pre-loaded in the processor through a program, and the processor can automatically judge whether the single-phase fault arc exists only by acquiring the current signal and the voltage signal.
It can be understood that, as shown in fig. 4, the power conversion circuit 10 includes a fuse F1, a voltage sampling circuit 101, a first voltage conversion circuit 102, a second voltage conversion circuit 103, a third voltage conversion circuit 104 and a fourth voltage conversion circuit 105, where the voltage sampling circuit 101 and the first voltage conversion circuit 102 are both connected to the live wire and the zero wire of the commercial power respectively, the fuse F1 is located between the first voltage conversion circuit 102 and the live wire of the commercial power and is used for performing an overload protection function, the voltage sampling circuit 101 is used for sampling a voltage signal of the commercial power, the first voltage conversion circuit 102 is used for converting a 220V ac voltage of the commercial power into a +12V dc voltage, the second voltage conversion circuit 103 is connected to an output end of the first voltage conversion circuit 102 and is used for converting the +12V dc voltage into a +5V dc voltage, and the third voltage conversion circuit 104 is connected to an output end of the second voltage conversion circuit 103 and is used for converting the +5V dc voltage into a ± 5.5V dc voltage, and the fourth voltage conversion circuit 105 is connected to the second voltage conversion circuit 103 and is used for converting the + 3.5V dc voltage into a + 3.3V. It can be understood that the power conversion circuit 10 may further include more voltage conversion circuits as needed to provide different power voltages.
Specifically, the voltage sampling circuit 101 includes a resistor R1, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, and a resistor R9, a first end of the resistor R1 is connected to a live wire of a commercial power through a fuse F1, a second end of the resistor R1 is connected to a first end of the resistor R4, a second end of the resistor R4 is connected to a first end of the resistor R5, a first end of the resistor R3 is connected to a zero line of the commercial power, a second end of the resistor R3 is connected to a first end of the resistor R6, a second end of the resistor R6 is connected to a first end of the resistor R7, a second end of the resistor R7 is connected to the first end of the resistor R8 and the fault arc signal processing circuit 12, a second end of the resistor R8 and a first end of the resistor R9 are grounded, and second ends of the resistor R9 and the fault arc signal processing circuit 12 are connected to the fault arc signal processing circuit 12. The voltage sampling circuit 101 may provide a voltage sampling signal for the fault arc signal processing circuit 12 by adopting a resistance voltage division sampling manner, so as to perform subsequent voltage signal analysis.
The first voltage conversion circuit 102 comprises a capacitor C3, a first voltage conversion module DY2, a filter inductor T1, a capacitor C7, a capacitor C12 and a capacitor C16, wherein a first end of the capacitor C3 is connected with a live wire of a mains supply through a fuse F1, a second end of the capacitor C3 is connected with a zero line of the mains supply, two input ends of the first voltage conversion module DY2 are respectively connected with the live wire and the zero line of the mains supply, two output ends of the first voltage conversion module DY2 are respectively connected with the input end of the filter inductor T1, a first output end of the filter inductor T1 is respectively connected with a first end of the capacitor C7 and the second voltage conversion circuit 103, a second output end of the capacitor C12 is grounded, a second end of the capacitor C12 is connected with a second end of the resistor R5, a first end of the capacitor C7, a first end of the capacitor C16 and a first end of the capacitor C12 are grounded, and a second end of the capacitor C16 is connected with a second end of the resistor R7. The first voltage conversion module DY2 is an alternating current-to-direct current EMC power conversion module, and 220V alternating current power voltage of mains supply is converted into 12V direct current power voltage through the first voltage conversion module DY 2.
The second voltage conversion circuit 103 comprises a polar capacitor C8, a second voltage conversion module TM1, a capacitor C4 and a polar capacitor C5, wherein the positive terminal of the polar capacitor C8 and the input terminal of the second voltage conversion module TM1 are connected with the first output terminal of the filter inductor T1, the output terminal of the second voltage conversion module TM1 is connected with the first terminal of the capacitor C4, the positive terminal of the polar capacitor C5, the fault arc signal processing circuit 12 and the third voltage conversion circuit 104, and the second terminal of the capacitor C4, the negative terminal of the polar capacitor C5 and the negative terminal of the polar capacitor C8 are all grounded. The 12V dc voltage may be converted into a 5V dc voltage by the second voltage conversion module TM 1.
The third voltage conversion circuit 104 includes a third voltage conversion module DY1, a capacitor C10, a polar capacitor C2, and a polar capacitor C9, where a pin 1 of the third voltage conversion module DY1 is connected to an output terminal of the second voltage conversion module TM1, a pin 2 is grounded, a pin 5 is used as an output terminal of a voltage of-5.5V, a pin 6 is grounded, a pin 7 is connected to a first end of the capacitor C1 and a positive terminal of the polar capacitor C2, respectively, and is used as an output terminal of a voltage of +5.5V, a second end of the capacitor C1, a negative terminal of the polar capacitor C2, a first end of the capacitor C10, and a positive terminal of the polar capacitor C9 are grounded, and a second end of the capacitor C10 and a negative terminal of the polar capacitor C9 are connected to a pin 5 of the third voltage conversion module DY 1.
The fourth voltage conversion circuit 105 comprises a capacitor C13, a polarity capacitor C17, a fourth voltage conversion module U1, a capacitor C14 and a polarity capacitor C15, wherein the first end of the capacitor C13, the positive end of the polarity capacitor C17 and the input end of the fourth voltage conversion module U1 are connected with the output end of the second voltage conversion module TM1, the output end of the fourth voltage conversion module U1 is connected with the first end of the capacitor C14 and the positive end of the polarity capacitor C15, and the second end of the capacitor C13, the negative end of the polarity capacitor C17, the second end of the capacitor C14 and the negative end of the polarity capacitor C15 are all grounded. The fourth voltage conversion module U1 can convert 5V dc voltage into 3.3V, which can supply power to the processor 11.
It can be understood that, with reference to fig. 3 and 5, the fault arc signal processing circuit 12 includes a voltage signal processing circuit 121 and a current signal processing circuit 122, where the voltage signal processing circuit 121 is respectively connected to the power conversion circuit 10 and the processor 11, and is configured to respectively convert the voltage sampling signal into a voltage sine wave signal and a voltage square wave signal, and output the voltage sine wave signal and the voltage square wave signal to the processor 11, and the current signal processing circuit 122 is respectively connected to the current signal input circuit 13 and the processor 11, and is configured to respectively convert the current sampling signal into a current sine wave signal, a current square wave signal, a current flat-shoulder pulse signal, and a current high-frequency pulse signal, and output the current sine wave signal, the current square wave signal, the current flat-shoulder pulse signal, and the current high-frequency pulse signal to the processor 11.
Specifically, the voltage signal processing circuit 121 includes a voltage differential amplifying circuit 1211 and a voltage shaping circuit 1212, the voltage differential amplifying circuit 1211 is respectively connected to the power conversion circuit 10, the voltage shaping circuit 1212 and the processor 11, and is configured to perform a primary amplification process on the voltage sampling signal, and output the amplified voltage sine wave signal to the voltage shaping circuit 1212 and the processor 11, and the voltage shaping circuit 1212 is respectively connected to the voltage differential amplifying circuit 1211 and the processor 11, and is configured to sequentially perform a secondary amplification process and a shaping process on the voltage sine wave signal after the primary amplification process, convert the voltage sine wave signal into a 3.3V voltage square wave signal, and output the voltage square wave signal to the processor 11. The processor 11 can identify relevant characteristics of the fault arc voltage signal according to the voltage sine wave signal and the voltage square wave signal, for example, when a single-phase fault arc occurs, the line voltage is suddenly dropped, and the waveform is close to a rectangle, so that the processor 11 can preliminarily determine whether the single-phase fault arc exists in the power line through the voltage sine wave signal and the voltage square wave signal.
Specifically, the voltage differential amplifying circuit 1211 includes a resistor R14, a resistor R16, a resistor R13, a capacitor C20, a resistor R22, a differential amplifier U1D, a resistor R19, a resistor R20, and a capacitor C19, first ends of the resistor R14 and the resistor R16 are connected to the power conversion circuit 10 to receive a voltage sampling signal, that is, to an output end of the voltage sampling circuit 101, a first end of the capacitor C20 is connected to the power conversion circuit 10 to receive a 5V power voltage, second ends of the resistor R14 are connected to a first end of the resistor R13 and an inverting input end of the differential amplifier U1D, a second end of the capacitor C20 is connected to a first end of the resistor R22, a second end of the resistor R16 is connected to a second end of the resistor R22 and a non-inverting input end of the differential amplifier U1D, output ends of the differential amplifier U1D are connected to a second end of the resistor R13, a first end of the capacitor C19 and a voltage shaping circuit 1212, and second ends of the resistor R19, the second end of the resistor R19, the power conversion circuit 10, and the second end of the resistor R3.3.
The voltage shaping circuit 1212 includes a resistor R18, a differential amplifier U1C, a resistor R17, a capacitor C18, an nand gate U3A, and a resistor R12, wherein a first end of the resistor R18 is connected to an output end of the voltage differential amplifier 1211, that is, to an output end of the differential amplifier U1D, a second end of the resistor R18 is connected to a non-inverting input end of the differential amplifier U1C, an inverting input end of the differential amplifier U1C is grounded, an output end of the differential amplifier U1C is connected to a first end of the resistor R17, a second end of the resistor R17 is connected to a first end of the capacitor C18 and two input ends of the nand gate U3A, respectively, a second end of the capacitor C18 is grounded, an output end of the nand gate U3A is connected to a first end of the resistor R12 and the processor 11, and a second end of the resistor R12 is connected to the power conversion circuit 10. The voltage sine wave signal after the primary amplification processing is secondarily amplified through the differential amplifier U1C, then the voltage sine wave signal after the secondary amplification is shaped by the nand gate U3A, and the voltage sine wave signal is converted into a 3.3V voltage square wave signal, so that the processor 11 can conveniently perform identification processing.
The current signal processing circuit 122 includes a flat shoulder pulse signal extraction circuit 123 and a high frequency pulse signal extraction circuit 124, the flat shoulder pulse signal extraction circuit 123 is respectively connected with the current signal input circuit 13 and the processor 11, and is configured to output the current sampling signal to the processor 11 after being respectively converted into a current sine wave signal, a current square wave signal and a current flat shoulder pulse signal, and the high frequency pulse signal extraction circuit 124 is respectively connected with the flat shoulder pulse signal extraction circuit 123 and the processor 11, and is configured to output the current sine wave signal to the processor 11 after being converted into a current high frequency pulse signal.
Specifically, the shoulder pulse signal extraction circuit 123 includes a current differential amplification circuit 1231, an automatic gain amplification circuit 1232, a current positive square wave generation circuit 1233, a current negative square wave generation circuit 1234, a shoulder pulse generation circuit 1235, and a first current shaping circuit 1236, the current differential amplifier circuit 1231 is connected to the current signal input circuit 13, the processor 11, and the automatic gain amplifier circuit 1232, is used for carrying out primary amplification processing on the current sampling signal, respectively outputting the current sine wave signal after the amplification processing to the processor 11 and the automatic gain amplification circuit 1232, the automatic gain amplifying circuit 1232 is respectively connected to the processor 11, the current positive square wave generating circuit 1233, and the current negative square wave generating circuit 1234, is used for carrying out secondary amplification processing on the current sine wave signal after primary amplification processing under the control of the processor 11 and then outputting the current sine wave signal, the current forward square wave generating circuit 1233 is configured to convert the current sine wave signal after the second amplification process into a current forward square wave signal of 5.5V, the current negative square wave generating circuit 1234 is configured to convert the current sine wave signal after the second amplification process into a current negative square wave signal, the flat shoulder pulse generating circuit 1235 is respectively connected to the current positive square wave generating circuit 1233, the current negative square wave generating circuit 1234 and the processor 11, is used for superposing the current positive square wave signal and the current negative square wave signal, extracting a current flat shoulder pulse signal and outputting the current flat shoulder pulse signal to the processor 11, the first current shaping circuit 1236 is connected to the current positive square wave generating circuit 1233, the current forward square wave generating circuit 1233 is configured to convert the 5.5V current forward square wave signal output by the current forward square wave generating circuit into a 3.3V current forward square wave signal, and output the signal to the processor 11.
The current differential amplifying circuit 1231 includes a resistor 30, a resistor R41, a resistor R42, a differential amplifier U1D, a resistor R31, a resistor R36, a resistor R37, a capacitor C22, and a resistor R44, where a first end of the resistor R41 and a first end of the resistor R30 are both connected to the current signal input circuit 13, a second end of the resistor R30 is connected to a first end of the resistor R31 and an inverting input terminal of the differential amplifier U1D, a second end of the resistor R41 and a second end of the resistor R42 are both connected to a non-inverting input terminal of the differential amplifier U1D, a first end of the resistor R42 is grounded, an output terminal of the differential amplifier U1D is connected to a second end of the resistor R31, a first end of the capacitor C22, a second end of the resistor R36, and the high-frequency pulse signal extraction circuit 124, a first end of the resistor R36 is connected to the automatic gain amplifying circuit 1232, a second end of the capacitor C22 is connected to a second end of the resistor R37, a first end of the resistor R44 and the processor 11, and a first end of the resistor R37 is connected to the power conversion circuit 10 to the ground, and a second end of the resistor R3.3V 3.44 is connected to the ground.
The automatic gain amplifying circuit 1232 includes a resistor R28, a resistor R23, a resistor R29, a non-inverting amplifier U1A, a resistor R43, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R38, a resistor R39, a resistor R40, a resistor R45, a resistor R46, a resistor R47, a transistor Q1, a transistor Q2, and a transistor Q3, a first end of the resistor R28 is grounded, a second end of the resistor R28 and a first end of the resistor R23 are connected to an inverting input terminal of the non-inverting amplifier U1A, a first end of the resistor R29 is connected to a non-inverting input terminal of the non-inverting amplifier U1A, an output terminal of the non-inverting amplifier U1A is connected to a second end of the resistor R23 and a first end of the resistor R43, and a second end of the resistor R43 is connected to the current positive square wave generating circuit 1233 and the current negative square wave generating circuit 1234. The second end of the resistor R29 is connected to the first end of the resistor R36, the first end of the resistor R32, the first end of the resistor R33, the first end of the resistor R34, and the first end of the resistor R35, the second end of the resistor R33 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the second end of the resistor R38 and the first end of the resistor R45, the first end of the resistor R38, the first end of the resistor R39, and the first end of the resistor R40 are all connected to the processor 11, the collector of the transistor Q2 is connected to the second end of the resistor R34, the base of the transistor Q2 is connected to the second end of the resistor R39 and the first end of the resistor R46, the collector of the transistor Q3 is connected to the first end of the resistor R35, the base of the resistor R40 and the first end of the resistor R47, the second end of the resistor R32, the emitter of the transistor Q1, the emitter of the transistor Q2, the emitter of the transistor Q3, the second end of the resistor R45, the second end of the resistor R46, and the second end of the resistor R47 are all grounded. The processor 11 controls whether the transistor Q1, the transistor Q2 and the transistor Q3 are conducted or not by controlling the level applied to the resistor R38, the resistor R39 and the resistor R40, thereby controlling the number of resistors put into the circuit and the connection structure among the plurality of resistors to change the attenuation intensity of the input signal of the non-inverting amplifier U1A, and thus realizing 8-step attenuation control.
The current forward square wave generating circuit 1233 includes a capacitor C25, a resistor R48, a resistor R59, a forward square wave generator U2B, a resistor R55, and a resistor R56, where a first end of the capacitor C25 and a forward input end of the forward square wave generator U2B are both connected to the automatic gain amplifying circuit 1232, that is, to a second end of the resistor R43, so as to receive the amplified current sine wave signal, a second end of the resistor R48 is connected to the power conversion circuit 10 so as to receive a-5.5V power voltage, a first end of the resistor R48 is connected to a first end of the resistor R59 and an inverted input end of the forward square wave generator U2B, an output end of the forward square wave generator U2B is connected to a first end of the resistor R55, a first end of the resistor R56, and a first current shaping circuit 1236, a second end of the resistor R59, a second end of the capacitor C25, and a second end of the resistor R55 are all grounded, and a second end of the resistor R56 is connected to the flat-shoulder pulse generating circuit 1235. The fault arc current positive square wave signal generated by the current positive square wave generating circuit 1233 is shown in fig. 6.
The current negative square wave generating circuit 1234 includes a resistor R49, a resistor R60, a negative square wave generator U2C, a capacitor C23, a capacitor C27, and a resistor R58, where an inverting input terminal of the negative square wave generator U2C is connected to the automatic gain amplifying circuit 1232, that is, connected to the second terminal of the resistor R43, a positive input terminal is connected to the first terminal of the resistor R49 and the first terminal of the resistor R60, the second terminal of the resistor R49, the first terminal of the capacitor C23, the No. 4 pin of the negative square wave generator U2C, and the first terminal of the capacitor C27 are all connected to the power converting circuit 10 to access a +5.5V power voltage, the No. 11 pin of the negative square wave generator U2C and the first terminal of the capacitor C27 are connected to the power converting circuit 10 to access a-5.5V power voltage, an output terminal of the negative square wave generator U2C is connected to the first terminal of the resistor R58 and the first current shaping circuit 1236, and the second terminal of the resistor R58, the second terminal of the capacitor C23, the second terminal of the capacitor C27, and the second terminal of the resistor R60 are all grounded. The fault arc current negative square wave signal generated by the current negative square wave generation circuit 1234 is shown in fig. 7.
The shoulder-flat pulse generating circuit 1235 includes a resistor R53, a capacitor C24, a capacitor C26, a nand gate U3D, and a resistor R50, where a first end of the resistor R53 is connected to an output end of the negative square wave generator U2C, a second end of the resistor R53 is connected to a first end of the capacitor C24 and a first input end of the nand gate U3D, a second input end of the nand gate U3D is connected to a first end of the capacitor C26 and an output end of the current positive square wave generating circuit (i.e., a second end of the resistor R56), an output end of the nand gate U3D is connected to the processor 11 and a second end of the resistor R50, the first end of the resistor R50 is connected to the power conversion circuit 10 to receive the 3.3V power voltage, and the second ends of the capacitor C24 and the capacitor C26 are grounded. As shown in fig. 8 and 9, the positive square wave signal of the fault arc current and the negative square wave signal of the fault arc current are superimposed by the nand gate U3D, and the reverse waveform of the shoulder pulse, that is, the current shoulder pulse signal, is extracted. Fig. 8 is a schematic diagram of the nand gate U3D superimposing the fault arc current positive square wave signal and the fault arc current negative square wave signal, and fig. 9 is a schematic diagram of a waveform of the flat shoulder pulse inversion signal synthesized by the nand gate U3D.
The first current shaping circuit 1236 includes a resistor R24, a capacitor C21, an nand gate U3B, and a resistor R21, wherein a first end of the resistor R24 is connected to an output end of the forward direction wave generator U2B, a second end of the resistor R24 is connected to a first end of the capacitor C21 and an input end of the nand gate U3B, a second end of the capacitor C21 is grounded, an output end of the nand gate U3B is connected to the processor 11 and a second end of the resistor R21, and a first end of the resistor R21 is connected to the power conversion circuit 10 to access a 3.3V power supply voltage. The current forward square wave signal of 5.5V is converted into a current forward square wave signal of 3.3V by the nand gate U3B, and then output to the processor 11, so that the processor 11 performs identification processing. It is understood that the current square wave signal output by the first current shaping circuit 1236 is a current positive square wave signal, i.e., a half wave signal.
The high-frequency pulse signal extraction circuit 124 includes a high-pass filter circuit 1241, a low-pass filter circuit 1242 and a second current shaping circuit 1243, the high-pass filter circuit 1241 is connected to the current differential amplification circuit 1231, the low-pass filter circuit 1242 is connected to the high-pass filter circuit 1241 and the second current shaping circuit 1243, the high-pass filter circuit 1241 is configured to filter a low-frequency interference signal in the amplified current sine wave signal, the low-pass filter circuit 1242 is configured to filter a high-frequency interference signal in the current sine wave signal, only a current sine wave signal of an intermediate frequency may enter the second current shaping circuit 1243 after being subjected to two-pass filtering, and the second current shaping circuit 1243 is configured to shape the current sine wave signal into a current square wave signal of 3.3V and output the current square wave signal to the processor 11. It is understood that the current square-wave signal output by the second current shaping circuit 1243 is a complete square-wave signal. In a preferred embodiment of the present invention, the high-pass filter circuit 1241 allows passage of a critical signal frequency of 700kHz, i.e. only signals exceeding 700kHz, while the low-pass filter circuit 1242 allows passage of a critical signal frequency of 900kHz, i.e. only signals smaller than 900kHz, while the current sine wave signal is around 800 kHz.
Specifically, the high-pass filter circuit 1241 includes a capacitor C29, a resistor R77, a capacitor C30, a resistor R64, an operational amplifier U2A, a resistor R79, and a resistor R68, where a first end of the capacitor C29 is connected to an output end of the current differential amplifier circuit 1231, that is, to an output end of the differential amplifier U1D, a second end of the capacitor C29 is connected to a first end of the capacitor C30 and a first end of the resistor R77, a second end of the capacitor C30 is connected to a first end of the resistor R79 and a non-inverting input end of the operational amplifier U2A, a second end of the resistor R79 and a first end of the resistor R64 are grounded, an inverting input end of the operational amplifier U2A is connected to a second end of the resistor R64 and a first end of the resistor R68, and an output end of the operational amplifier U2A is connected to a second end of the resistor R68, a second end of the resistor R77 and the low-pass filter circuit 1242.
The low-pass filter circuit 1242 includes a resistor R71, a capacitor C33, a resistor R72, a capacitor C31, an operational amplifier U2B, a resistor R63, and a resistor R65, a first end of the resistor R71 is connected to an output end of the high-pass filter circuit 1241, that is, to an output end of the operational amplifier U2A, a second end of the resistor R71 is connected to a first end of the capacitor C33 and a first end of the resistor R72, a second end of the resistor R72 is connected to a first end of the capacitor C31 and a non-inverting input end of the operational amplifier U2B, an inverting input end of the operational amplifier U2B is connected to a second end of the resistor R63 and a first end of the resistor R65, a first end of the resistor R63 and a second end of the capacitor C31 are grounded, and an output end of the operational amplifier U2B is connected to a second end of the capacitor C33, a second end of the resistor R65, and the second current shaping circuit 1243.
The second current shaping circuit 1243 comprises a resistor R69, a capacitor C32, a nand gate U3C, and a resistor R66, wherein a first end of the resistor R69 is connected to an output end of the low-pass filter circuit 1242, that is, to an output end of the operational amplifier U2B, a second end of the resistor R69 is connected to a first end of the capacitor C32 and an input end of the nand gate U3C, respectively, a second end of the capacitor C32 is grounded, an output end of the nand gate U3C is connected to a second end of the resistor R66 and the processor 11, respectively, and a first end of the resistor R66 is connected to the power conversion circuit 10 to receive a 3.3V power supply voltage. The current sine wave signal after the secondary band-pass filtering is shaped into a complete current square wave signal of 3.3V through the nand gate U3C, so that the processor 11 can perform identification processing conveniently. In addition, the circuit pin diagram of the processor 11 is shown in fig. 10, and has 48-bit pins in total.
It can be understood that, as shown in fig. 3 and fig. 11, the single-phase fault arc detector further preferably includes an audible alarm circuit 16 connected to the processor 11 and configured to issue an audible alarm prompt, and when the processor 11 determines that a single-phase fault arc exists in the power line, the audible alarm circuit 16 is controlled to issue an alarm prompt. Specifically, the sound alarm circuit 16 includes a buzzer BE1, a diode D2, a capacitor C28, a resistor R73, a resistor R76, and a transistor Q5, wherein a first end of the resistor R73 is connected to the processor 11 to receive a control signal, a second end of the resistor R73 is connected to a first end of the resistor R76 and a base of the transistor Q5, a second end of the resistor R76 and an emitter of the transistor Q5 are grounded, a collector of the transistor Q5 is connected to a positive end of the buzzer BE1, a positive end of the diode D2, and a second end of the capacitor C28, and the buzzer BE1, a negative end of the diode D2, and a first end of the capacitor C28 are connected to the power conversion circuit 10 to receive a +12V power voltage. The whole circuit structure is simpler, and the use is comparatively common electronic components in the market moreover, and manufacturing cost is lower.
It will be appreciated that preferably, as shown in fig. 3 and 12, the single-phase fault arc detector further comprises a crystal debugging interface circuit 14 connected to the processor 11. Specifically, the crystal oscillator debugging interface circuit 14 includes an interface PZ1, a resistor R2, a capacitor C6, a capacitor C11, and a crystal oscillator Y1, where the interface PZ1, a first end of the resistor R2, a first end of the capacitor C6, two ends of the crystal oscillator Y1, and a second end of the capacitor C11 are all connected to the processor 11, and a second end of the resistor R2, a second end of the capacitor C6, and a first end of the capacitor C11 are all grounded. The PZ1 is connected with external crystal oscillator debugging equipment, so that the working parameters of the crystal oscillator Y1 can be debugged.
It will be appreciated that the single-phase fault arc detector also preferably includes a communications networking circuit 15 connected to the processor 11, as shown in figures 3 and 13. Specifically, the communication networking circuit 15 includes a Wifi interface module and an RS485 communication circuit, which are respectively connected to the processor 11, where the Wifi interface module is used for communication of Wifi signals, and the RS485 communication circuit is used for communication of 485 signals. RS485 communication circuit includes resistance R61, resistance R54, resistance R62, RS485 communication module U4, resistance R61, resistance R54, resistance R62's first end all is connected with power conversion circuit 10 in order to insert 5V's mains voltage, resistance R61's second end, resistance R54's second end, resistance R62's second end, RS485 communication module U4's output all is connected with treater 11, RS485 communication module U4's input passes through the interface and is connected with external communication equipment.
It can be understood that, as shown in fig. 3 and fig. 14, the single-phase fault arc detector further includes a key indication circuit 17 connected to the processor 11, and specifically, the key indication circuit 17 includes a resistor R67, a resistor R70, a resistor R74, a resistor R75, a resistor R78, a key switch S1, a key switch S2, an led D3, an led D4, and an led D5, a first end of the resistor R67 and a first end of the resistor R70 are both connected to the power conversion circuit 10 to receive a 3.3V power voltage, a second end of the resistor R67 is connected to the processor 11 and a first end of the key switch S1, a second end of the resistor R70 is connected to the processor 11 and a first end of the key switch S2, a first end of the resistor R74, a first end of the resistor R75, and a first end of the resistor R78 are both connected to the processor 11, a second end of the resistor R74 is connected to the first end of the led D3, a second end of the resistor R75 is connected to the first end of the led D3, a second end of the key switch R4 is connected to the second end of the led D4, and a second end of the resistor R78 is connected to the led D5, a second end of the led D5 and a second end of the led S5, a second end of the led S5 is connected to the led D5, a second end of the switch S5, a second end of the led D5, a ground.
It will be appreciated that, as shown in fig. 3 and 15, the single-phase fault arc detector further preferably includes an alarm trip circuit 18 connected to the processor 11 for controlling the safety switch in the power line to open under the control of the processor 11 for safety protection. Specifically, the alarm trip circuit 18 includes a resistor R57, a resistor R51, a resistor R52, a transistor Q4, a diode D1, and a relay K1, a first end of the resistor R57 is connected to the processor 11, a second end of the resistor R57 is connected to the power conversion circuit 10 to access a 3.3V power supply voltage, a second end of the resistor R51 is connected to the processor 11, a first end of the resistor R51 and a first end of the resistor R52 are both connected to the base of the transistor Q4, a second end of the resistor R52 and an emitter of the transistor Q4 are both grounded, a collector of the transistor Q4 is respectively connected to a positive terminal of the diode D1 and the relay K1, negative terminals of the relay K1 and the diode D1 are both connected to the power conversion circuit 10 to access a +5V power supply voltage, and a normally closed contact of the relay K1 is connected to a safety switch in the power line. The processor 11 sends out a control signal to control the triode Q4 to be conducted, so that the relay K1 is controlled to be electrified, and the relay K1 acts, so that the safety switch is controlled to be disconnected.
It can be understood that, as shown in fig. 3 and 16, the single-phase fault arc detector further includes a communication interface circuit 19 connected to the communication networking circuit 15, the communication interface circuit 19 includes a resistor R10, a resistor R15, and a resistor R11, a first end of the resistor R10 is connected to ground, a second end of the resistor R10 and a first end of the resistor R11 are connected to the communication networking circuit 15, both a second end of the resistor R11 and a first end of the resistor R15 are connected to the communication networking circuit 15, and a second end of the resistor R15 is connected to the power conversion circuit 10 to receive a supply voltage of 5V.
As shown in fig. 17, the current signal input circuit 13 includes a resistor R25, a resistor R26, a resistor R27, and a filter inductor T2, wherein both ends of the resistor R25, both ends of the resistor R26, both ends of the resistor R27, and both input ends of the filter inductor T2 are respectively connected to both ends of the transformer, and both output ends of the filter inductor T2 are connected to the fault arc signal processing circuit 12, specifically, to the first end of the resistor R30 and the first end of the resistor R41 in the current differential amplifier circuit 1231. The common-mode filtering function can be achieved by arranging the filter inductor T2.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A fault arc signal processing circuit, comprising:
the voltage signal processing circuit (121) is used for converting the voltage sampling signals into voltage sine wave signals and voltage square wave signals respectively and outputting the voltage sine wave signals and the voltage square wave signals to the processor (11);
the current signal processing circuit (122) is used for converting the current sampling signal into a current sine wave signal, a current square wave signal, a current flat shoulder pulse signal and a current high-frequency pulse signal respectively and outputting the signals to the processor (11);
the voltage signal processing circuit (121) comprises a voltage differential amplifying circuit (1211) and a voltage shaping circuit (1212), the voltage differential amplifying circuit (1211) is used for carrying out primary amplification processing on a voltage sampling signal and then outputting the voltage sampling signal, and the voltage shaping circuit (1212) is used for sequentially carrying out secondary amplification processing and shaping processing on a voltage sine wave signal after the primary amplification processing, converting the voltage sine wave signal into a 3.3V voltage square wave signal and then outputting the voltage square wave signal;
the current signal processing circuit (122) comprises a flat shoulder pulse signal extraction circuit (123) and a high-frequency pulse signal extraction circuit (124), the flat shoulder pulse signal extraction circuit (123) is used for converting current sampling signals into current sine wave signals, current square wave signals and current flat shoulder pulse signals respectively and then outputting the current sine wave signals, the current square wave signals and the current flat shoulder pulse signals to the processor (11), and the high-frequency pulse signal extraction circuit (124) is used for converting the current sine wave signals output by the flat shoulder pulse signal extraction circuit (123) into current high-frequency pulse signals and then outputting the current high-frequency pulse signals to the processor (11).
2. The fault arc signal processing circuit according to claim 1, wherein the voltage differential amplifying circuit (1211) includes a resistor R14, a resistor R16, a resistor R13, a capacitor C20, a resistor R22, a differential amplifier U1D, a resistor R19, a resistor R20, and a capacitor C19, first ends of the resistor R14 and the resistor R16 are used for receiving a voltage sampling signal, a first end of the capacitor C20 is used for receiving a supply voltage of 5V, second ends of the resistor R14 are respectively connected to a first end of the resistor R13 and an inverting input end of the differential amplifier U1D, a second end of the capacitor C20 is connected to a first end of the resistor R22, a second end of the resistor R16 is respectively connected to a second end of the resistor R22 and a non-inverting input end of the differential amplifier U1D, an output end of the differential amplifier U1D is respectively connected to a second end of the resistor R13, a first end of the capacitor C19, a voltage shaping circuit (1212), and a second end of the capacitor C19 is respectively connected to a second end of the resistor R19, a first end of the resistor R20, a second end of the resistor R11, a second end of the resistor R19, a power supply voltage receiving a voltage, a power supply voltage, a 3.3.3.
3. The circuit of claim 1, wherein the voltage shaping circuit (1212) comprises a resistor R18, a differential amplifier U1C, a resistor R17, a capacitor C18, a nand gate U3A, and a resistor R12, wherein a first end of the resistor R18 is connected to an output end of the voltage differential amplifying circuit (1211), a second end of the resistor R18 is connected to a non-inverting input end of the differential amplifier U1C, an inverting input end of the differential amplifier U1C is grounded, an output end is connected to a first end of the resistor R17, a second end of the resistor R17 is connected to a first end of the capacitor C18 and two input ends of the nand gate U3A, respectively, a second end of the capacitor C18 is grounded, an output end of the nand gate U3A is connected to a first end of the resistor R12 and the processor (11), a second end of the resistor R12 is used for accessing a supply voltage of 3.3V, the voltage sine wave signal after the primary amplification is amplified by the differential amplifier U1C, and then the voltage sine wave signal is shaped by the nand gate U3A to be a square wave signal (3.3V) for identification.
4. The fault arc signal processing circuit according to claim 1, wherein the flat-shoulder pulse signal extracting circuit (123) includes a current differential amplifying circuit (1231), an automatic gain amplifying circuit (1232), a current positive square wave generating circuit (1233), a current negative square wave generating circuit (1234), a flat-shoulder pulse generating circuit (1235), and a first current shaping circuit (1236), the current differential amplifying circuit (1231) is configured to amplify a current sample signal for the first time and output the amplified current sine wave signal to the processor (11) and the automatic gain amplifying circuit (1232), the automatic gain amplifying circuit (1232) is configured to amplify the current sine wave signal for the second time under the control of the processor (11) and output the amplified current sine wave signal, the current positive square wave generating circuit (1233) is configured to convert the current sine wave signal for the second time into a current positive square wave signal of 5.5V, the current generating circuit (1234) is configured to convert the current signal for the second time into a current positive square wave signal of 5.5V, the current negative square wave generating circuit (1233) is configured to output the current negative square wave signal after the current square wave signal is amplified for the positive square wave signal (1233) and output, and the negative square wave signal is configured to output the first current signal (1233) and output the negative square wave signal for the negative square wave signal (1233) and output the negative square wave signal for the positive square wave signal (1233) and output, and the negative square wave signal of the current negative square wave signal (1233) is configured to output, and the current negative square wave signal of the current V5.5.5V 6, and the current generating circuit (1233) is configured to output the current V6 and output the current V output the current negative square wave signal after the current V6) is configured to output the current generation circuit (1233 and output the current generation circuit (6) is configured to output the square wave signal after the current generation circuit (6) is configured to output the current generation circuit (6) ).
5. The arc fault signal processing circuit according to claim 4, wherein the current forward square wave generating circuit (1233) comprises a capacitor C25, a resistor R48, a resistor R59, a forward square wave generator U2B, a resistor R55, and a resistor R56, wherein a first end of the capacitor C25 and a non-inverting input end of the forward square wave generator U2B are connected to the automatic gain amplifying circuit (1232), a second end of the resistor R48 is used for receiving a 5.5V power voltage, a first end of the resistor R48 is connected to a first end of the resistor R59 and an inverting input end of the forward square wave generator U2B, an output end of the forward square wave generator U2B is connected to a first end of the resistor R55, a first end of the resistor R56 and the first current shaping circuit (1236), a second end of the resistor R59, a second end of the capacitor C25 and a second end of the resistor R55 are grounded, and a second end of the resistor R56 is connected to the shoulder pulse generating circuit (1235).
6. The fault arc signal processing circuit according to claim 4, wherein the current negative square wave generator circuit (1234) comprises a resistor R49, a resistor R60, a negative square wave generator U2C, a capacitor C23, a capacitor C27, and a resistor R58, wherein an inverting input of the negative square wave generator U2C is connected to the automatic gain amplifier circuit (1232), a positive input is connected to the first end of the resistor R49 and the first end of the resistor R60, respectively, a second end of the resistor R49, the first end of the capacitor C23, and a pin No. 4 of the negative square wave generator U2C are connected to a +5.5V power supply voltage, a pin No. 11 of the negative square wave generator U2C and the first end of the capacitor C27 are connected to a-5.5V power supply voltage, an output of the negative square wave generator U2C is connected to the first end of the resistor R58 and the first current shaping circuit (1236), and a second end of the resistor R58, a second end of the capacitor C23, a second end of the capacitor C27, and a second end of the resistor R60 are connected to ground.
7. The arc fault signal processing circuit according to claim 4, wherein the flat-shoulder pulse generating circuit (1235) includes a resistor R53, a capacitor C24, a nand gate U3D, a capacitor C26, and a resistor R50, a first end of the resistor R53 is connected to the output end of the current negative square wave generating circuit (1234), a second end of the resistor R53 is connected to the first end of the capacitor C24 and the first input end of the nand gate U3D, respectively, a second input end of the nand gate U3D is connected to the output end of the current positive square wave generating circuit (1233) and the first end of the capacitor C26, respectively, an output end of the nand gate U3D is connected to the processor (11) and the second end of the resistor R50, respectively, the first end of the resistor R50 is used for receiving a 3.3V power voltage, and the second ends of the capacitor C24 and the capacitor C26 are both grounded.
8. A single-phase fault arc detector is characterized in that a fault arc signal processing circuit as claimed in any one of claims 1 to 7 is adopted.
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