CN113955131A - Data intelligent monitoring processing platform for health state of manned aircraft - Google Patents
Data intelligent monitoring processing platform for health state of manned aircraft Download PDFInfo
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- 230000036541 health Effects 0.000 title claims abstract description 43
- 238000012544 monitoring process Methods 0.000 title claims abstract description 31
- 238000012545 processing Methods 0.000 title claims abstract description 30
- 238000013473 artificial intelligence Methods 0.000 claims abstract description 26
- 230000003862 health status Effects 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims description 98
- 238000004891 communication Methods 0.000 claims description 39
- 239000011324 bead Substances 0.000 claims description 38
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- 238000004458 analytical method Methods 0.000 description 9
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- 230000002159 abnormal effect Effects 0.000 description 5
- 238000007726 management method Methods 0.000 description 5
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- 238000013135 deep learning Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000013528 artificial neural network Methods 0.000 description 2
- 230000005548 health behavior Effects 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B64—AIRCRAFT; AVIATION; COSMONAUTICS
- B64D—EQUIPMENT FOR FITTING IN OR TO AIRCRAFT; FLIGHT SUITS; PARACHUTES; ARRANGEMENT OR MOUNTING OF POWER PLANTS OR PROPULSION TRANSMISSIONS IN AIRCRAFT
- B64D45/00—Aircraft indicators or protectors not otherwise provided for
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B64—AIRCRAFT; AVIATION; COSMONAUTICS
- B64D—EQUIPMENT FOR FITTING IN OR TO AIRCRAFT; FLIGHT SUITS; PARACHUTES; ARRANGEMENT OR MOUNTING OF POWER PLANTS OR PROPULSION TRANSMISSIONS IN AIRCRAFT
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Abstract
The application discloses manned vehicle health status's data intelligent monitoring processing platform, including high performance AI system, video acquisition system, flight environment acquisition system and each part operating condition acquisition system of manned vehicle, high performance AI system connection video acquisition system, flight environment acquisition system and each part operating condition acquisition system of manned vehicle. Has the following advantages: all data represented by the health state of the manned vehicle and relevant parameters of the flight environment of the manned vehicle are collected and collected in real time, the collected flight parameter data are analyzed and processed in an artificial intelligence mode in real time based on a high-performance AI processor/model/algorithm, health state judgment of the manned vehicle is output, relevant information is fed back to a flight control system, and deep unmanned driving of the manned vehicle is achieved.
Description
Technical Field
The invention relates to an intelligent data monitoring and processing platform for the health state of a manned aircraft, in particular to a data acquisition, processing, storage and other monitoring platform for the state monitoring of the manned aircraft.
Background
As a current emerging technical product, the manned aircraft has reliability and safety which are core factors for wide application of the product due to personnel safety.
At present, various types of manned aircrafts have been developed by multiple units/organizations, but a highly reliable and standardized health state monitoring scheme of the manned aircrafts is not provided for a while.
The invention patent of patent number "202010015332.2", IPC classification number "G06F", patent name "an aircraft health management method and system" discloses an aircraft health management system, including: the state monitoring module is used for establishing an abnormity monitoring library, setting a monitoring parameter range and judging whether abnormity occurs or not by acquiring flight parameters of the aircraft; the health evaluation module is used for establishing a health behavior model and a health evaluation algorithm, and comparing real-time output parameters of the flight control system with results output by the health behavior model based on the health evaluation algorithm to obtain a health state evaluation result of the current flight control system; the fault prediction module is used for acquiring aircraft equipment information, and obtaining the probability and time of predicting the occurrence of a fault according to the aircraft equipment information for aircraft damage judgment, degradation state identification and residual service life prediction; and the maintenance management module is used for establishing a database for storing and managing aircraft historical data and state information, analyzing and researching the corresponding aircraft based on the output results of the three modules and generating a maintenance scheme.
The invention patent of patent number "201510191978.5", IPC classification number "G06F", patent name "an unmanned aerial vehicle system health status evaluation device" discloses an unmanned aerial vehicle system health status evaluation device, is applied to evaluating the health status of K unmanned aerial vehicles; the method comprises the following steps: the system comprises an information acquisition module, an information processing module, an evaluation processing module, a health state score display module and a health state information database; the information acquisition module is used for acquiring flight data of the unmanned aerial vehicle in the flight process; the information processing module is used for processing the flight data to obtain a standard flight data block; the evaluation processing module processes the standard flight data by using an entropy weight G1 weighting method according to the set health state evaluation index system, obtains the weight of each evaluation index and the health state score of the unmanned aerial vehicle system, and sends the weight and the health state score to the health state score display module for displaying.
In the prior art, the health state monitoring of the manned aircraft mostly records flight parameters of the aircraft, data processing such as data playback and analysis is carried out after the flight is finished, and the data processing has the timeliness problem and cannot judge the health state of the aircraft in real time in the flight process of the aircraft; some traditional manned aircraft health condition monitoring carry out real-time monitoring state judgement through the abnormal parameter of monitoring and fault mode contrast, but these fault modes are aircraft hardware fault codes, mainly fix a position some hardware in the aircraft and break down, can't gather external environment parameter and carry out data fusion analysis processing in the internal hardware parameter, do not synthesize a plurality of parameters and carry out big data artificial intelligence processing analysis, can't effective early warning to some potential flight safety problems.
Disclosure of Invention
The invention aims to solve the technical problems that based on the current increasingly mature artificial intelligence technology and big data intelligent analysis technology, the invention provides a data intelligent monitoring and processing platform for the health state of the manned vehicle, which collects and summarizes all data represented by the health state of the manned vehicle and relevant parameters of the flight environment of the manned vehicle in real time, carries out artificial intelligent analysis and processing on the collected flight parameter data in real time based on a high-performance AI processor/model/algorithm, outputs the health state judgment of the manned vehicle, and feeds back the related information to the flight control system to realize the deep unmanned piloting of the manned aircraft, and simultaneously displays the health state information of the manned aircraft on a central control platform of the aircraft in real time, the method has the advantages that the abnormal condition is early warned in real time, so that the pilot/passenger can conveniently make emergency operation, and the safe and reliable flight of the manned aircraft is effectively guaranteed.
In order to solve the technical problems, the invention adopts the following technical scheme:
a data intelligent monitoring and processing platform for the health state of a manned aircraft comprises a high-performance AI system, a video acquisition system, a flight environment acquisition system and a working state acquisition system for each component of the manned aircraft, wherein the high-performance AI system is connected with the video acquisition system, the flight environment acquisition system and the working state acquisition system for each component of the manned aircraft;
the high-performance AI system comprises an artificial intelligence chip, a local large-capacity memory, an LVDS video display interface, an MIPI image data input interface, an internal bus communication interface and an external wireless communication interface, wherein the artificial intelligence chip is connected with the local large-capacity memory, the LVDS video display interface, the MIPI image data input interface, the internal bus communication interface and the external wireless communication interface;
the artificial intelligence chip integrates a CPU + GPU + NN unit and provides a control management function and an AI mode/algorithm acceleration operation function; the local large-capacity storage comprises DDR3, FLASH and EEPROM, and is used for storing an AI model, an AI library, and a program memory and a data memory required by the running of a CPU; the LVDS video display interface is connected with the LCD display screen and used for outputting and displaying information; the MIPI image data input interface is used for connecting the video acquisition system and receiving image data; the internal bus communication interface comprises an Ethernet, a USB, a CAN, an RS422/485 bus interface and is used for connecting the flight environment acquisition system and the working state acquisition system of each part of the manned aircraft and receiving all the acquired data; the external wireless communication interface comprises Beidou communication and 4G/5G public network communication, is used for communicating with a ground command/service station and is used as a communication interface for early warning information downloading and emergency command instruction interaction.
Furthermore, the model of the artificial intelligence chip is YuLong810A, and the artificial intelligence chip comprises a chip U1A, a chip U1B, a chip U1D and a chip U1E;
an AG9 pin of the chip U1D is connected with one end of a resistor R88, the other end of the resistor R88 is grounded, an AG8 pin of the chip U1D is connected with one end of a resistor R89, the other end of the resistor R89 is grounded, an AE9 pin of the chip U1D is connected with one end of a resistor R91, the other end of the resistor R91 is grounded, an AF9 pin of the chip U1D is connected with one end of a resistor R92, the other end of the resistor R92 is grounded, an AG6 pin of the chip U1D is connected with one end of a resistor R95, the other end of the resistor R95 is grounded, an AF6 pin of the chip U1D is connected with one end of a resistor R99, the other end of the resistor R99 is grounded, an AG4 pin of the chip U1D is connected with one end of a resistor R100, and the other end of the resistor R100 is grounded; an AC14 pin and an AB15 pin of a chip U1E are connected with one end of a capacitor C180, one end of a capacitor C181 and one end of a magnetic bead inductor FB8, the other end of the capacitor C180 and the other end of the capacitor C181 are grounded, the other end of the magnetic bead inductor FB8 is connected with a VDD _ SOC power supply, an AD14 pin and an AD15 pin of the chip U1E are connected with one end of a capacitor C182, one end of a capacitor C183 and one end of a magnetic bead inductor FB9, the other end of the capacitor C182 and the other end of the capacitor C183 are grounded, and the other end of the magnetic bead inductor FB9 is connected with the VDD _ SOC power supply.
Further, the local mass storage comprises a chip U2, a chip U3, a chip U5, a chip U6 and a chip U7, the models of the chip U2, the chip U3, the chip U5, the chip U6 and the chip U7 are MT41K256M16TW-107AAT, and the chip U2, the chip U3, the chip U5, the chip U6 and the chip U7 are all connected with a chip U1A; the chip U1B is connected to each of the chip U5, the chip U6, and the chip U7.
Further, the local mass storage device further comprises a chip U4, the model of the chip U4 is TPS51200QDRCRQ 4, pin 1 of the chip U4 is connected with one end of a capacitor C4, one end of a resistor R4 and one end of a resistor R4, the other end of the capacitor C4 and the other end of the resistor R4 are grounded, the other end of the resistor R4 is connected with pin 2 of the chip U4, one end of the capacitor C4 and one end of the capacitor C4 are connected to VDDIO _ DDR power, the other end of the capacitor C4 and the other end of the capacitor C4 are grounded, pin 3 and pin 5 of the chip U4 are connected with one end of the capacitor C4 and are connected to DDR _ VTT power, the other end of the capacitor C4 and the other end of the capacitor C4 are grounded, pin 6 of the chip U4 is connected with one end of the resistor R4 and one end of the capacitor C4, the other end of the capacitor C4 is connected to ground, the other end of the resistor R4 is connected to DDR _ VREF _ 4, the other end of the capacitor C4 and the other end of the capacitor C4 are connected to DVDD 4, the other end of the capacitor C44 is grounded, a pin 6 of the chip U4 is connected with one end of a capacitor C47 and one end of a resistor R13, the other end of the capacitor C47 is grounded, and the other end of the resistor R13 is connected with a DDR3_ VREF power supply.
Further, the internal bus communication interface comprises a U10, the model number of a chip U10 is 88E1116R, the 64 pin of the chip U10 is connected with one end of a resistor R94, the other end of the resistor R94 is connected with a PHY _ POWER POWER supply, the 4 pin of the chip U10 is connected with one end of a resistor R93 and one end of a resistor R101, the other end of the resistor R93 is connected with the PHY _ POWER supply, the 57 pin of the chip U10 is connected with one end of a resistor R102 and the other end of the resistor R101, the other end of the resistor R102 is grounded, the 52 pin, the 56 pin, the 46 pin and the 7 pin of the chip U10 are connected with one end of an inductor magnetic bead FB5, the other end of the FB5 is connected with the PHY _ POWER supply, the 33 pin of the chip U10 is connected with one end of a resistor R86, the other end of the resistor R86 is grounded, the 38 pin of the chip U10 is connected with one end of a resistor R81, one end of a crystal oscillator X2 and one end of a capacitor C163, the 39 pin of the chip U10 is connected with the other end of the resistor R81, the other end of the capacitor C163 and the capacitor C10 are connected with the other end of the capacitor C103, and the other end of the capacitor C103 and the capacitor C9, and the other end of the capacitor C9 are connected with the other end of the resistor R81, One end of a capacitor C165, one end of a resistor R104 and one end of a diode D3, the other end of a resistor R103 and the other end of a diode D3 are connected with a PHY _ POWER POWER supply, and the other end of the capacitor C165 is grounded.
Furthermore, a pin 6 of the chip U10 is connected with one end of a resistor R108, the other end of the resistor R108 is connected with a base of a triode Q4, a collector of the triode Q4 is connected with one end of a diode D4, the other end of the diode D4 is connected with one end of a resistor R105, the other end of the resistor R105 is connected with a DVDD _3V3 power supply, a pin 8 of the chip U10 is connected with one end of a resistor R83, one end of a resistor R83 is connected with a base of a triode Q2, a collector of the triode Q2 is connected with one end of a diode D1, the other end of the diode D1 is connected with one end of a resistor R82, the other end of the resistor R82 is connected with a DVDD _3V3 power supply, a pin 9 of the chip U10 is connected with one end of a resistor R87, the other end of the resistor R87 is connected with a base of a triode Q3, a collector of a triode Q3 is connected with one end of a diode D2, the other end of a resistor D2 is connected with one end of a DVDD _3V 2 power supply;
the 3 feet of the chip U10 are connected with one end of a resistor R106, one end of a resistor R107, one end of a resistor R109 and one end of a resistor R110, the other end of the resistor R106 is connected with one end of a resistor R94, the other end of the resistor R94 is connected with 64 feet of the chip U10, the other end of the resistor R107 is grounded, the other end of the resistor R109 is connected with 6 feet of the chip U10, the other end of the resistor R110 is connected with 8 feet of the chip U10, the 2 feet of the chip U10 is connected with one end of a resistor R111, one end of a resistor R112 and one end of a resistor R113, the other end of the resistor R111 is connected with one end of a resistor R94, the other end of the resistor R94 is connected with 64 feet of the chip U10, the other end of the resistor R112 is grounded, and the other end of the resistor R113 is connected with 6 feet of the chip U10.
Furthermore, the 45 pin of the chip U10 is connected to the AF4 pin of the chip U1D, the 48 pin of the chip U10 is connected to the AE5 pin of the chip U1D, the 60 pin of the chip U10 is connected to the AG5 pin of the chip U1D, the 63 pin of the chip U10 is connected to the AE10 pin of the chip U1D, the 62 pin of the chip U10 is connected to the AE12 pin of the chip U1D, the 61 pin of the chip U10 is connected to the AF 10 pin of the chip U1 10, the 59 pin of the chip U10 is connected to the AF 10 pin of the chip U1 10, the 58 pin of the chip U10 is connected to the AG10 pin of the chip U1 10, the 53 pin of the chip U10 is connected to the AF 10 pin of the chip U1 10, the 49 pin of the chip U10 is connected to the AG10 pin of the chip U1 10, the AH pin of the chip U10 is connected to the AF 10, the AF 10 pin of the chip U10 is connected to the AF 10, and the AF 10 of the AF 10 is connected to the AF 10 pin of the chip U1U 10.
Further, the internal bus communication interface further comprises a chip U11 and a chip U12, the models of the chip U11 and the chip U12 are IP4292CZ10-TBR, the 10 pin of the chip U11 is connected with the 31 pin of the chip U10, the 9 pin of the chip U11 is connected with the 30 pin of the chip U10, the 7 pin of the chip U11 is connected with the 26 pin of the chip U10, the 6 pin of the chip U11 is connected with the 25 pin of the chip U10, the 1 pin of the chip U11 is connected with the 1 pin of the network interface J11, the 2 pin of the chip U11 is connected with the 2 pin of the network interface J11, the 4 pin of the chip U11 is connected with the 3 pin of the network interface J11, and the 5 pin of the chip U11 is connected with the 6 pin of the network interface J11;
the 10 pin of the chip U12 is connected with the 24 pin of the chip U10, the 9 pin of the chip U12 is connected with the 23 pin of the chip U10, the 7 pin of the chip U12 is connected with the 20 pin of the chip U10, the 6 pin of the chip U12 is connected with the 19 pin of the chip U10, the 1 pin of the chip U12 is connected with the 4 pin of the network interface J11, the 2 pin of the chip U12 is connected with the 5 pin of the network interface J11, the 4 pin of the chip U12 is connected with the 7 pin of the network interface J11, and the 5 pin of the chip U12 is connected with the 8 pin of the network interface J11.
Further, the LVDS video display interface includes an interface J12, the MIPI image data input interface includes an interface J13, an 8 pin of the interface J13 and a 10 pin of the interface J12 are connected to a chip U13, the model of the chip U13 is TXS0108E, a 4 pin of the chip U13 is connected to the 8 pin of the interface J13 and a 10 pin of the interface J12, a 5 pin of the chip U13 is connected to a 6 pin of the interface J13 and a 12 pin of the interface J12, a 6 pin of the chip U13 is connected to one end of a resistor R122, the other end of the resistor R122 is connected to a 12 pin of the interface J13, a 16 pin of the interface J12 and one end of a resistor R131, the other end of the resistor R131 is connected to a3 pin of a crystal oscillator X3, a 4 pin of the crystal oscillator X3 is connected to one end of a capacitor C186 connected to a DVDD _1V8 power supply, the other end of the capacitor C186 is grounded, a 10 pin of the chip U13 is connected to one end of a resistor R121, and the other end of the resistor V8 is connected to another power supply.
Furthermore, a pin 3 of the interface J13 is connected to one end of a resistor R119, the other end of the resistor R119 is connected to one end of a resistor R120, the other end of the resistor R120 is connected to a pin 5 of the interface J12, a pin 5 of the interface J13 is connected to one end of a resistor R123, the other end of the resistor R123 is connected to one end of a resistor R124, the other end of the resistor R124 is connected to a pin 7 of the interface J12, a pin 4 of the interface J13 is connected to one end of a magnetic bead inductor FB10, the other end of the magnetic bead inductor FB10 is connected to an AVDD28 power supply, a pin 10 of the interface J13 is connected to one end of a magnetic bead inductor FB 3, the other end of the magnetic bead inductor FB11 is connected to a DVDD12 power supply, a pin 11 of the interface J13 is connected to one end of a magnetic bead inductor FB12, and the other end of the magnetic bead inductor FB12 is connected to a DVDD _1V8 power supply;
a pin 14 of the interface J13 is connected with a pin AJ13 of the chip U1E, a pin 15 of the interface J13 is connected with a pin AK13 of the chip U1E, a pin 16 of the interface J13 is connected with a pin AJ12 of the chip U1E, a pin 17 of the interface J13 is connected with a pin AK12 of the chip U1E, a pin 18 of the interface J13 is connected with a pin AJ10 of the chip U1E, a pin 19 of the interface J13 is connected with a pin AK10 of the chip U1E, a pin 20 of the interface J13 is connected with a pin AJ9 of the chip U1E, a pin 21 of the interface J13 is connected with a pin AK9 of the chip U1E, a pin 23 of the interface J13 is connected with a pin AJ11 of the chip U1E, and a pin 24 of the interface J13 is connected with a pin AK11 of the chip U1E;
the pin 11 of the interface J12 is connected with one end of a resistor R125, the other end of the resistor R125 is connected with an AK11 pin of a chip U1E, the pin 13 of the interface J12 is connected with one end of a resistor R126, the other end of the resistor R126 is connected with an AJ11 pin of the chip U1E, the pin 15 of the interface J12 is connected with one end of a resistor R127, the other end of the resistor R127 is connected with an AK9 pin of the chip U1E, the pin 17 of the interface J12 is connected with one end of a resistor R128, the other end of the resistor R128 is connected with an AJ9 pin of the chip U1E, the pin 19 of the interface J12 is connected with one end of a resistor R129, the other end of the resistor R129 is connected with an AK10 pin of the chip U1E, the pin 21 of the interface J12 is connected with one end of a resistor R130, the other end of the resistor R130 is connected with an AJ10 pin of the chip U1E, the pin 24 of the interface J12 is connected with one end of a magnetic bead inductor FB13, and the other end of the magnetic bead FB13 is grounded.
By adopting the technical scheme, compared with the prior art, the invention has the following technical effects:
aiming at the relevance of flight environment parameters, flight coordinate positions and postures of the manned aircraft and working state parameters of flight components, a monitoring device consisting of a high-performance AI system, a video acquisition system, a flight environment acquisition system and a working state acquisition system of each component of the manned aircraft is built based on the current artificial intelligence technology developed at a high speed, all data represented by the health state of the manned aircraft and relevant parameters of the flight environment are acquired and collected in real time, finally, the AI system calls a relevant AI model and an AI algorithm to carry out artificial intelligence analysis on the data, the health state judgment of the manned aircraft is output, relevant information is fed back to the flight control system, the deep unmanned driving of the manned aircraft is realized, the health state information of the manned aircraft is displayed on a central control platform of the aircraft in real time, and the abnormal condition is early warned in real time, the emergency operation of pilots/passengers is facilitated, and therefore powerful guarantee is provided for safe and reliable flight of the manned aircraft.
Drawings
In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
FIG. 1 is a system block diagram of an intelligent data monitoring and processing platform for the health status of a manned aircraft according to an embodiment of the invention;
fig. 2 is a system block diagram of a high-performance AI system according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a circuit of a portion of an artificial intelligence chip according to an embodiment of the invention;
FIG. 4 is a schematic circuit diagram of a local mass storage portion according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a circuit of a portion of an artificial intelligence chip according to an embodiment of the invention;
FIG. 6 is a schematic circuit diagram of a local mass storage portion according to an embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of a local mass storage portion according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a circuit of a portion of an artificial intelligence chip according to an embodiment of the invention;
FIG. 9 is a schematic diagram of the internal bus communication interface according to an embodiment of the present invention;
FIG. 10 is a schematic circuit diagram of a portion of an internal bus communication interface according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a LVDS video display interface and a MIPI image data input interface circuit according to an embodiment of the present invention.
Detailed Description
As shown in fig. 2, the high-performance AI system 1 includes an artificial intelligence chip 106, a local mass storage 105, an LVDS video display interface 101, an MIPI image data input interface 104, an internal bus communication interface 103, and an external wireless communication interface 102, where the artificial intelligence chip 106 connects the local mass storage 105, the LVDS video display interface 101, the MIPI image data input interface 104, the internal bus communication interface 103, and the external wireless communication interface 102.
The artificial intelligence chip 106 integrates a CPU + GPU + NN unit and provides a control management function and an AI mode/algorithm acceleration operation function; the local mass storage 105 comprises DDR3, FLASH, EEPROM and the like, and is mainly used for storing an AI model, an AI library, and a program memory and a data memory required by the running of a CPU; the LVDS video display interface 101 is connected with an LCD display screen and used for outputting and displaying information; the MIPI image data input interface 104 is used for connecting the video acquisition system and receiving image data; the internal bus communication interface 103 comprises bus interfaces such as Ethernet, USB, CAN, RS422/485 and the like, and is used for connecting a flight environment acquisition system and a manned aircraft each component working state acquisition system and receiving all acquired data; the external wireless communication interface 102 comprises Beidou communication and 4G/5G public network communication, is used for communicating with a ground command/service station, and is used as a communication interface for early warning information downloading and emergency command instruction interaction.
The artificial intelligence chip 106 is a domestic intelligent chip YuLong810A or a similar product.
As shown in FIG. 3, the artificial intelligence chip 106 includes a chip U1A.
As shown in FIG. 4, the local mass storage 105 comprises a chip U and a chip U, the model of the chip U and the model of the chip U are MT41K256M 16-107 AAT, the N pins of the chip U and the chip U are both connected with the W pin of the chip U1, the P pins of the chip U and the chip U are both connected with the N pin of the chip U1, the P pins of the chip U and the chip U are both connected with the W pin of the chip U1, the N pins of the chip U and the chip U are both connected with the N pin of the chip U1, the P pins of the chip U and the chip U are both connected with the W pin of the chip U1, the P pins of the chip U and the chip U are both connected with the M pin of the chip U1, the R pins of the chip U and the chip U are both connected with the Y pin of the chip U1, the R pins of the chip U and the chip U are both connected with the L pin of the chip U1, the Y pin of the chip U and the chip U are both connected with the V pin of the chip U1, the R pins of the chip U and the chip U are connected with the Y pin of the chip U1, the N pins of the chip U and the chip U are connected with the R pin of the chip U1, the T pins of the chip U and the chip U are connected with the M pin of the chip U1, the T pins of the chip U and the chip U are connected with the V pin of the chip U1, the M pins of the chip U and the chip U are connected with the P pin of the chip U1, the M pins of the chip U and the chip U are connected with the W pin of the chip U1, the N pins of the chip U and the chip U are connected with the N pin of the chip U1, the M pins of the chip U and the chip U are connected with the V pin of the chip U1, the L pins of the chip U and the chip U are connected with the V pin of the chip U1, the K pins of the chip U and the chip U are connected with the N pin of the chip U1, the J pins of the chip U and the chip U are connected with the T pin of the chip U1, the pins K9 of the chips U2 and U3 are connected with the pin U25 of the chip U1A, and the pins T2 of the chips U2 and U3 are connected with the pin L27 of the chip U1A.
The J7 pins of the chip U2 are all connected with the U28 pin of the chip U1A, the K7 pins of the chip U2 are all connected with the U27 pin of the chip U1A, the F3 pins of the chip U2 are all connected with the F27 pin of the chip U1A, the G3 pins of the chip U2 are all connected with the F28 pin of the chip U1A, the C7 pins of the chip U2 are all connected with the B30 pin of the chip U1A, the B7 pins of the chip U2 are all connected with the F28 pin of the chip U1A, the E7 pins of the chip U2 are all connected with the E28 pin of the chip U1A, and the D3 pins of the chip U2 are all connected with the D30 pin of the chip U1A.
The J7 pins of the chip U3 are all connected with the T28 pin of the chip U1A, the K7 pins of the chip U3 are all connected with the T27 pin of the chip U1A, the F3 pins of the chip U3 are all connected with the J28 pin of the chip U1A, the G3 pins of the chip U3 are all connected with the J27 pin of the chip U1A, the C7 pins of the chip U3 are all connected with the J30 pin of the chip U1A, the B7 pins of the chip U3 are all connected with the H30 pin of the chip U1A, the E7 pins of the chip U3 are all connected with the J26 pin of the chip U1A, and the D3 pins of the chip U3 are all connected with the L30 pin of the chip U1A.
The pins E of the chip U are all connected with the pins G of the chip U1, the pins F of the chip U are all connected with the pins E of the chip U1, the pins F of the chip U are all connected with the pins G of the chip U1, the pins H of the chip U are all connected with the pins F of the chip U1, the pins G of the chip U are all connected with the pins G of the chip U1, the pins H of the chip U are all connected with the pins D of the chip U1, the pins D of the chip U are all connected with the pins C of the chip U1, the pins C of the chip U are all connected with the pins A of the chip U1, the pins A of the chip U are all connected with the pins E of the chip U1, and the pins D of the chip U are all connected with the pins B of the chip U1, the pins A3 of the chip U2 are connected with the pins D29 of the chip U1A.
The pins E of the chip U are all connected with the pins K of the chip U1, the pins F of the chip U are all connected with the pins H of the chip U1, the pins F of the chip U are all connected with the pins K of the chip U1, the pins F of the chip U are all connected with the pins H of the chip U1, the pins H of the chip U are all connected with the pins K of the chip U1, the pins G of the chip U are all connected with the pins K of the chip U1, the pins H of the chip U are all connected with the pins J of the chip U1, the pins D of the chip U are all connected with the pins J of the chip U1, the pins C of the chip U are all connected with the pins K of the chip U1, the pins C of the chip U are all connected with the pins F of the chip U1, the pins C of the chip U are all connected with the pins M of the chip U1, the pins A of the chip U are all connected with the pins G of the chip U1, the A3 pins of the chip U3 are all connected with the K29 pins of the chip U1A.
The local mass storage 105 further comprises a chip U4, the model of the chip U4 is TPS51200QDRCRQ 4, a pin 1 of the chip U4 is connected with one end of a capacitor C4, one end of a resistor R4 and one end of a resistor R4, the other end of the capacitor C4 and the other end of the resistor R4 are grounded, the other end of the resistor R4 is connected with a pin 2 of the chip U4, one end of the capacitor C4 and one end of the capacitor C4 are grounded and connected with a VDDIO _ DDR power supply, the other end of the capacitor C4 and the other end of the capacitor C4 are grounded, a pin 3 and a pin 5 of the chip U4 are connected with one end of the capacitor C4 and connected with a DDR 4 _ VTT power supply, the other end of the capacitor C4 and the other end of the capacitor C4 are grounded, the other end of the capacitor C4 is connected with a pin 6 of the resistor R4 and one end of the capacitor C4, the other end of the capacitor C4 is connected with a DDR3 and connected with a DDR3_ DD and connected with a capacitor C4 and connected with a capacitor D4 and connected with a DDR 3V 4. The other end of the capacitor C44 is grounded, a pin 6 of the chip U4 is connected with one end of a capacitor C47 and one end of a resistor R13, the other end of the capacitor C47 is grounded, and the other end of the resistor R13 is connected with a DDR3_ VREF power supply.
As shown in FIG. 5, the artificial intelligence chip 106 also includes a chip U1B.
As shown in FIGS. 6 and 7, the local mass storage 105 further comprises a chip U, a chip U and a chip U, the model of the chip U and the model of the chip U are MT41K256M 16-107 AAT, the N pins of the chip U, the chip U and the chip U are all connected with the W pin of the chip U1, the P pins of the chip U, the chip U and the chip U are all connected with the N pin of the chip U1, the P pins of the chip U, the chip U and the chip U are all connected with the W pin of the chip U1, the N pins of the chip U, the chip U and the chip U are all connected with the N pin of the chip U1, the P pins of the chip U, the chip U and the chip U are all connected with the W pin of the chip U1, the P pins of the chip U, the chip U and the chip U are all connected with the M pin of the chip U1, the R pins of the chip U, the chip U and the chip U are all connected with the L pin of the chip U1, and the chip U, The T feet of the chip U and the chip U are connected with the Y foot of the chip U1, the R feet of the chip U, the chip U and the chip U are connected with the M foot of the chip U1, the L feet of the chip U, the chip U and the chip U are connected with the V foot of the chip U1, the R feet of the chip U, the chip U and the chip U are connected with the Y foot of the chip U1, the N feet of the chip U, the chip U and the chip U are connected with the R foot of the chip U1, the T feet of the chip U, the chip U and the chip U are connected with the M foot of the chip U1, the T feet of the chip U, the chip U and the chip U are connected with the V foot of the chip U1, the M feet of the chip U, the chip U and the chip U are connected with the P foot of the chip U1, the M feet of the chip U, the chip U and the chip U are connected with the W foot of the chip U1, the N feet of the chip U, the M feet of the chip U and the chip U are connected with the V foot of the chip U1, the L3 pins of the chips U5, U6 and U7 are all connected with the V28 pin of the chip U1A, the K3 pins of the chips U5, U6 and U7 are all connected with the N27 pin of the chip U1A, the J3 pins of the chips U5, U6 and U7 are all connected with the T3 pin of the chip U13, the L3 pins of the chips U3, U3 and U3 are all connected with the R3 pin of the chip U13, the K3 pins of the chips U3, U3 and U3 are all connected with the T3 pin of the chip U13, the U3 and the T3 pins of the chips U3 are all connected with the L3 pin of the chip U1 3.
The J7 pins of the chip U5 are all connected with the R28 pin of the chip U1A, the K7 pins of the chip U5 are all connected with the R27 pin of the chip U1A, the F3 pins of the chip U5 are all connected with the AB27 pin of the chip U1B, the G3 pins of the chip U5 are all connected with the AB28 pin of the chip U1B, the C7 pins of the chip U5 are all connected with the R30 pin of the chip U1B, the B7 pins of the chip U5 are all connected with the R29 pin of the chip U1B, the E7 pins of the chip U5 are all connected with the AB26 pin of the chip U1B, and the D3 pin of the chip U5 is all connected with the T30 pin of the chip U1B.
The J7 pins of the chip U6 are all connected with the P28 pin of the chip U1A, the K7 pins of the chip U6 are all connected with the P27 pin of the chip U1A, the F3 pins of the chip U6 are all connected with the AF28 pin of the chip U1B, the G3 pins of the chip U6 are all connected with the AF27 pin of the chip U1B, the C7 pins of the chip U6 are all connected with the AB29 pin of the chip U1B, the B7 pins of the chip U6 are all connected with the AB30 pin of the chip U1B, the E7 pins of the chip U6 are all connected with the AE27 pin of the chip U1B, and the D3 pins of the chip U6 are all connected with the AC30 pin of the chip U1B.
The pins E of the chip U are all connected with the pins AC of the chip U1, the pins F of the chip U are all connected with the pins AA of the chip U1, the pins F of the chip U are all connected with the pins AC of the chip U1, the pins H of the chip U are all connected with the pins AB of the chip U1, the pins G of the chip U are all connected with the pins AD of the chip U1, the pins H of the chip U are all connected with the pins AA of the chip U1, the pins D of the chip U are all connected with the pins T of the chip U1, the pins C of the chip U are all connected with the pins N of the chip U1, the pins C of the chip U are all connected with the pins W of the chip U1, the pins A of the chip U are all connected with the pins P of the chip U1, the pins A of the chip U are all connected with the pins V of the chip U1, the pins A3 of the chip U5 are connected with the pins V29 of the chip U1B.
The pins E of the chip U are all connected with the pins AG of the chip U1, the pins F of the chip U are all connected with the pins AE of the chip U1, the pins F of the chip U are all connected with the pins AG of the chip U1, the pins F of the chip U are all connected with the pins AD of the chip U1, the pins H of the chip U are all connected with the pins AH of the chip U1, the pins G of the chip U are all connected with the pins AH of the chip U1, the pins H of the chip U are all connected with the pins AD of the chip U1, the pins D of the chip U are all connected with the pins W of the chip U1, the pins C of the chip U are all connected with the pins AD of the chip U1, the pins C of the chip U are all connected with the pins Y of the chip U1, the pins C of the chip U are all connected with the pins AE of the chip U1, the pins A of the chip U are all connected with the pins AA of the chip U1, and the pins D of the chip U are all connected with the pins AA of the chip U1, the A3 pins of the chip U6 are connected with the AD29 pins of the chip U1B.
The pins J7 of the chip U7 are connected with the pin P28 of the chip U1A, the pins K7 of the chip U7 are connected with the pin P27 of the chip U1A, the pins F3 of the chip U7 are connected with the pins AJ30 of the chip U1B, the pins G3 of the chip U7 are connected with the pins AJ29 of the chip U1B, and the pins E7 of the chip U7 are connected with the pins AH29 of the chip U1B.
As shown in fig. 8, the artificial intelligence chip 106 further includes a chip U1D and a chip U1E, a pin AG9 of the chip U1D is connected to one end of a resistor R88, the other end of the resistor R88 is grounded, a pin AG8 of the chip U1D is connected to one end of a resistor R89, the other end of the resistor R89 is grounded, a pin AE9 of the chip U1D is connected to one end of a resistor R91, the other end of the resistor R91 is grounded, a pin AF9 of the chip U1D is connected to one end of a resistor R92, the other end of the resistor R92 is grounded, a pin AG6 of the chip U1D is connected to one end of a resistor R95, the other end of the resistor R95 is grounded, a pin AF6 of the chip U1D is connected to one end of a resistor R99, the other end of the resistor R99 is grounded, a pin AG4 of the chip U1D is connected to one end of a resistor R100, and the other end of the resistor R100 is grounded; an AC14 pin and an AB15 pin of a chip U1E are connected with one end of a capacitor C180, one end of a capacitor C181 and one end of a magnetic bead inductor FB8, the other end of the capacitor C180 and the other end of the capacitor C181 are grounded, the other end of the magnetic bead inductor FB8 is connected with a VDD _ SOC power supply, an AD14 pin and an AD15 pin of the chip U1E are connected with one end of a capacitor C182, one end of a capacitor C183 and one end of a magnetic bead inductor FB9, the other end of the capacitor C182 and the other end of the capacitor C183 are grounded, and the other end of the magnetic bead inductor FB9 is connected with the VDD _ SOC power supply.
As shown in fig. 10, the internal bus communication interface 103 includes a U10, a chip U10 is 88E1116R, a resistor R94 is connected to a pin 64 of the chip U10, the other end of the resistor R94 is connected to the PHY _ POWER supply, a resistor R93 and a resistor R101 are connected to a pin 4 of the chip U10, the other end of the resistor R93 is connected to the PHY _ POWER supply, a resistor R102 and a resistor R101 are connected to a pin 57 of the chip U10, the other end of the resistor R102 is grounded, a ball inductor FB5 is connected to pins 52, 56, 46 and 7 of the chip U10, the other end of FB5 is connected to the PHY _ POWER supply, a resistor R86 is connected to a pin 33 of the chip U10, the other end of the resistor R86 is grounded, a pin 38 of the chip U10 is connected to a resistor R81, a crystal X2 and a capacitor C163, a pin 39 of the chip U10 is connected to the other end of the crystal R81, the other end of the crystal X2 and the other end of the capacitor C163 and the capacitor C163, the pin 10 of the chip U10 is connected with one end of a resistor R103, one end of a capacitor C165, one end of a resistor R104 and one end of a diode D3, the other end of the resistor R103 and the other end of the diode D3 are connected with a PHY _ POWER POWER supply, and the other end of the capacitor C165 is grounded.
The 6 feet of the chip U10 are connected with one end of a resistor R108, the other end of the resistor R108 is connected with a base of a triode Q4, a collector of the triode Q4 is connected with one end of a diode D4, the other end of the diode D4 is connected with one end of a resistor R105, the other end of the resistor R105 is connected with a DVDD _3V3 power supply, the 8 feet of the chip U10 is connected with one end of a resistor R83, one end of a resistor R83 is connected with a base of a triode Q2, the collector of the triode Q2 is connected with one end of a diode D1, the other end of the diode D1 is connected with one end of a resistor R82, the other end of the resistor R82 is connected with a DVDD _3V3 power supply, the 9 feet of the chip U10 is connected with one end of a resistor R87, the other end of the resistor R87 is connected with a base of a triode Q3, the collector of the triode Q3 is connected with one end of a diode D2, the other end of the diode D2 is connected with one end of a resistor R85, and the other end of the resistor R85 is connected with a DD _3V3 power supply.
The 3 feet of the chip U10 are connected with one end of a resistor R106, one end of a resistor R107, one end of a resistor R109 and one end of a resistor R110, the other end of the resistor R106 is connected with one end of a resistor R94, the other end of the resistor R94 is connected with 64 feet of the chip U10, the other end of the resistor R107 is grounded, the other end of the resistor R109 is connected with 6 feet of the chip U10, the other end of the resistor R110 is connected with 8 feet of the chip U10, the 2 feet of the chip U10 is connected with one end of a resistor R111, one end of a resistor R112 and one end of a resistor R113, the other end of the resistor R111 is connected with one end of a resistor R94, the other end of the resistor R94 is connected with 64 feet of the chip U10, the other end of the resistor R112 is grounded, and the other end of the resistor R113 is connected with 6 feet of the chip U10.
The 45 pin of the chip U10 is connected with the AF4 pin of the chip U1D, the 48 pin of the chip U10 is connected with the AE5 pin of the chip U1D, the 60 pin of the chip U10 is connected with the AG5 pin of the chip U1D, the 63 pin of the chip U10 is connected with the AE10 pin of the chip U1D, the 62 pin of the chip U10 is connected with the AE12 pin of the chip U1D, the 61 pin of the chip U10 is connected with the AF 10 pin of the chip U1 10, the 59 pin of the chip U10 is connected with the AF 10 pin of the chip U1 10, the 58 pin of the chip U10 is connected with the AG10 pin of the chip U1 10, the 53 pin of the chip U10 is connected with the AF 10 pin of the chip U1 10, the 49 pin of the chip U10 is connected with the AF 10 pin of the chip U1 10, the pin of the chip U72 is connected with the AF 10 pin of the AF 10, the AE10 pin of the chip U10 is connected with the AE10 of the chip U1, the chip AH 72, and the AE10 of the chip U10 is connected with the chip U72.
As shown in fig. 9, the internal bus communication interface 103 further includes a chip U11 and a chip U12, the models of the chip U11 and the chip U12 are IP4292CZ10-TBR, the 10 pin of the chip U11 is connected to the 31 pin of the chip U10, the 9 pin of the chip U11 is connected to the 30 pin of the chip U10, the 7 pin of the chip U11 is connected to the 26 pin of the chip U10, the 6 pin of the chip U11 is connected to the 25 pin of the chip U10, the 1 pin of the chip U11 is connected to the 1 pin of the network interface J11, the 2 pin of the chip U11 is connected to the 2 pin of the network interface J11, the 4 pin of the chip U11 is connected to the 3 pin of the network interface J11, and the 5 pin of the chip U11 is connected to the 6 pin of the network interface J11.
The 10 pin of the chip U12 is connected with the 24 pin of the chip U10, the 9 pin of the chip U12 is connected with the 23 pin of the chip U10, the 7 pin of the chip U12 is connected with the 20 pin of the chip U10, the 6 pin of the chip U12 is connected with the 19 pin of the chip U10, the 1 pin of the chip U12 is connected with the 4 pin of the network interface J11, the 2 pin of the chip U12 is connected with the 5 pin of the network interface J11, the 4 pin of the chip U12 is connected with the 7 pin of the network interface J11, and the 5 pin of the chip U12 is connected with the 8 pin of the network interface J11.
As shown in fig. 11, the LVDS video display interface 101 includes an interface J12, the MIPI image data input interface 104 includes an interface J13, an 8 pin of the interface J13 and a 10 pin of the interface J12 are connected to a chip U13, the model of the chip U13 is TXS0108E, a 4 pin of the chip U13 is connected to an 8 pin of the interface J13 and a 10 pin of the interface J12, a 5 pin of the chip U13 is connected to a 6 pin of the interface J13 and a 12 pin of the interface J12, a 6 pin of the chip U13 is connected to one end of a resistor R122, the other end of the resistor R122 is connected to a 12 pin of the interface J13, a 16 pin of the interface J12 and one end of a resistor R131, the other end of the resistor R131 is connected to a3 pin of the crystal oscillator X3, a 4 pin of the crystal oscillator X3 is connected to one end of a capacitor C186 and connected to a DVDD _1V8 power supply, the other end of the capacitor C186 is connected to ground, a 10 pin of the chip U13 is connected to one end of a resistor R121 and a resistor V8.
The 3 feet of the interface J13 are connected with one end of a resistor R119, the other end of the resistor R119 is connected with one end of a resistor R120, the other end of the resistor R120 is connected with the 5 feet of the interface J12, the 5 feet of the interface J13 are connected with one end of a resistor R123, the other end of the resistor R123 is connected with one end of a resistor R124, the other end of the resistor R124 is connected with the 7 feet of the interface J12, the 4 feet of the interface J13 are connected with one end of a magnetic bead inductor FB10, the other end of the magnetic bead inductor FB10 is connected with an AVDD28 power supply, the 10 feet of the interface J13 are connected with one end of a magnetic bead inductor FB11, the other end of the magnetic bead inductor FB11 is connected with a DVDD12 power supply, the 11 foot of the interface J13 is connected with one end of a magnetic bead inductor FB12, and the other end of the magnetic bead inductor FB12 is connected with a DVDD _1V8 power supply.
The 14 pin of the interface J13 is connected with the AJ13 pin of the chip U1E, the 15 pin of the interface J13 is connected with the AK13 pin of the chip U1E, the 16 pin of the interface J13 is connected with the AJ12 pin of the chip U1E, the 17 pin of the interface J13 is connected with the AK12 pin of the chip U1E, the 18 pin of the interface J13 is connected with the AJ10 pin of the chip U1E, the 19 pin of the interface J13 is connected with the AK10 pin of the chip U1E, the 20 pin of the interface J13 is connected with the AJ9 pin of the chip U1E, the 21 pin of the interface J13 is connected with the AK9 pin of the chip U1E, the 23 pin of the interface J13 is connected with the AJ11 pin of the chip U1E, and the 24 pin of the interface J13 is connected with the AK11 pin of the chip U1E.
The pin 11 of the interface J12 is connected with one end of a resistor R125, the other end of the resistor R125 is connected with an AK11 pin of a chip U1E, the pin 13 of the interface J12 is connected with one end of a resistor R126, the other end of the resistor R126 is connected with an AJ11 pin of the chip U1E, the pin 15 of the interface J12 is connected with one end of a resistor R127, the other end of the resistor R127 is connected with an AK9 pin of the chip U1E, the pin 17 of the interface J12 is connected with one end of a resistor R128, the other end of the resistor R128 is connected with an AJ9 pin of the chip U1E, the pin 19 of the interface J12 is connected with one end of a resistor R129, the other end of the resistor R129 is connected with an AK10 pin of the chip U1E, the pin 21 of the interface J12 is connected with one end of a resistor R130, the other end of the resistor R130 is connected with an AJ10 pin of the chip U1E, the pin 24 of the interface J12 is connected with one end of a magnetic bead inductor FB13, and the other end of the magnetic bead FB13 is grounded.
The high-performance AI system 1 provides a high-performance processor and an AI accelerator, has platform acceleration capacity of deep learning and neural network algorithm, integrates an image data interface, high-speed interfaces such as Ethernet and USB, low-speed interfaces such as CAN, RS422/485 and the like, is used for connecting a video acquisition system, a flight environment acquisition system and each component working state acquisition systems of the manned aircraft, realizes the control of other acquisition systems through an external interface and collects all data represented by the health state of the manned aircraft and relevant parameters of the flight environment of the manned aircraft, finally calls a relevant AI model and an AI algorithm by the AI system, carries out artificial intelligent analysis on the data, outputs the health state judgment of the manned aircraft, feeds relevant information back to the flight control system, realizes the deep unmanned driving of the manned aircraft, and simultaneously displays the health state information of the manned aircraft on a central control platform of the aircraft in real time, and the abnormal condition is early warned in real time, so that the pilot/passenger can conveniently make emergency operation.
The intelligent data monitoring and processing platform for the health state of the manned aircraft integrates the Beidou communication function, and can download the health state information of the manned aircraft to the ground command/service platform in real time through Beidou satellite communication in any environment.
The data intelligent monitoring and processing platform for the health state of the manned aircraft has an intelligent self-learning (deep learning) function, automatically carries out intelligent analysis and identification on all data represented by the health state of the manned aircraft and relevant parameters of the flight environment of the manned aircraft in the flight process, and automatically takes the data as training samples of an AI model to carry out self-training and automatically reconstruct and optimize the AI model and algorithm.
The intelligent data monitoring and processing platform for the health state of the manned aircraft provides a remote online upgrading/reconstruction interface, comprises Beidou communication, 4G/5G public network communication and the like, and a user can annotate an AI model/algorithm of the platform at any time, reconstruct platform firmware and the like.
The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to practitioners skilled in this art. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (10)
1. The utility model provides a manned vehicle health status's data intelligent monitoring processing platform which characterized in that: the system comprises a high-performance AI system (1), a video acquisition system (2), a flight environment acquisition system (3) and a manned aircraft component working state acquisition system (4), wherein the high-performance AI system (1) is connected with the video acquisition system (2), the flight environment acquisition system (3) and the manned aircraft component working state acquisition system (4);
the high-performance AI system (1) comprises an artificial intelligence chip (106), a local large-capacity memory (105), an LVDS video display interface (101), an MIPI image data input interface (104), an internal bus communication interface (103) and an external wireless communication interface (102), wherein the artificial intelligence chip (106) is connected with the local large-capacity memory (105), the LVDS video display interface (101), the MIPI image data input interface (104), the internal bus communication interface (103) and the external wireless communication interface (102);
the artificial intelligence chip (106) integrates a CPU + GPU + NN unit and provides a control management function and an AI mode/algorithm acceleration operation function; the local large-capacity storage (105) comprises DDR3, FLASH and EEPROM and is used for storing an AI model, an AI library and a program memory and a data memory required by the running of the CPU; the LVDS video display interface (101) is connected with an LCD display screen and used for outputting and displaying information; the MIPI image data input interface (104) is used for connecting the video acquisition system and receiving image data; the internal bus communication interface (103) comprises an Ethernet, a USB, a CAN, and an RS422/485 bus interface, and is used for connecting the flight environment acquisition system and the working state acquisition system of each part of the manned aircraft and receiving all the acquired data; the external wireless communication interface (102) comprises Beidou communication and 4G/5G public network communication, is used for communicating with a ground command/service station and is used as a communication interface for early warning information downloading and emergency command instruction interaction.
2. The manned vehicle health status data intelligent monitoring processing platform of claim 1, wherein: the model of the artificial intelligence chip (106) is YuLong810A, and the artificial intelligence chip comprises a chip U1A, a chip U1B, a chip U1D and a chip U1E;
an AG9 pin of the chip U1D is connected with one end of a resistor R88, the other end of the resistor R88 is grounded, an AG8 pin of the chip U1D is connected with one end of a resistor R89, the other end of the resistor R89 is grounded, an AE9 pin of the chip U1D is connected with one end of a resistor R91, the other end of the resistor R91 is grounded, an AF9 pin of the chip U1D is connected with one end of a resistor R92, the other end of the resistor R92 is grounded, an AG6 pin of the chip U1D is connected with one end of a resistor R95, the other end of the resistor R95 is grounded, an AF6 pin of the chip U1D is connected with one end of a resistor R99, the other end of the resistor R99 is grounded, an AG4 pin of the chip U1D is connected with one end of a resistor R100, and the other end of the resistor R100 is grounded; an AC14 pin and an AB15 pin of a chip U1E are connected with one end of a capacitor C180, one end of a capacitor C181 and one end of a magnetic bead inductor FB8, the other end of the capacitor C180 and the other end of the capacitor C181 are grounded, the other end of the magnetic bead inductor FB8 is connected with a VDD _ SOC power supply, an AD14 pin and an AD15 pin of the chip U1E are connected with one end of a capacitor C182, one end of a capacitor C183 and one end of a magnetic bead inductor FB9, the other end of the capacitor C182 and the other end of the capacitor C183 are grounded, and the other end of the magnetic bead inductor FB9 is connected with the VDD _ SOC power supply.
3. The manned vehicle health status data intelligent monitoring processing platform of claim 2, wherein: the local mass storage (105) comprises a chip U2, a chip U3, a chip U5, a chip U6 and a chip U7, wherein the models of the chip U2, the chip U3, the chip U5, the chip U6 and the chip U7 are MT41K256M16TW-107AAT, and the chip U2, the chip U3, the chip U5, the chip U6 and the chip U7 are all connected with a chip U1A; the chip U1B is connected to each of the chip U5, the chip U6, and the chip U7.
4. The intelligent data monitoring and processing platform for the health state of the manned aircraft according to claim 3, wherein: the local mass storage (105) further comprises a chip U4, the model of the chip U4 is TPS51200QDRCRQ 4, a pin 1 of the chip U4 is connected with one end of a capacitor C4, one end of a resistor R4 and one end of a resistor R4, the other end of the capacitor C4 and the other end of the resistor R4 are grounded, the other end of the resistor R4 is connected with a pin 2 of the chip U4, one end of the capacitor C4 and one end of the capacitor C4 are grounded and connected with a VDDIO _ DDR power supply, the other end of the capacitor C4 and the other end of the capacitor C4 are grounded, a pin 3 and a pin 5 of the chip U4 are connected with one end of the capacitor C4 and connected with a DDR power supply, the other end of the capacitor C4 and the other end of the capacitor C4 are grounded, the pin 6 of the chip U4 is connected with one end of the resistor R4 and one end of the capacitor C4 and the other end of the capacitor DVDD 4 are connected with a DDR power supply, the resistor D4 and the other end of the chip 4 are connected with a DDR power supply, and connected with a resistor D9 of the chip 4 and a resistor D4 and connected with a resistor V3 of the chip 4, the other end of the capacitor C44 is grounded, a pin 6 of the chip U4 is connected with one end of a capacitor C47 and one end of a resistor R13, the other end of the capacitor C47 is grounded, and the other end of the resistor R13 is connected with a DDR3_ VREF power supply.
5. The manned vehicle health status data intelligent monitoring processing platform of claim 2, wherein: the internal bus communication interface (103) comprises a U10, the model number of a chip U10 is 88E1116R, the pin 64 of the chip U10 is connected with one end of a resistor R94, the other end of the resistor R94 is connected with a PHY _ POWER POWER supply, the pin 4 of the chip U10 is connected with one end of a resistor R93 and one end of a resistor R101, the other end of the resistor R93 is connected with the PHY _ POWER supply, the pin 57 of the chip U10 is connected with one end of a resistor R102 and the other end of the resistor R101, the other end of the resistor R102 is grounded, the pins 52, 56, 46 and 7 of the chip U10 are connected with one end of a magnetic bead FB5, the other end of the FB5 is connected with the PHY _ POWER supply, the pin 33 of the chip U10 is connected with one end of a resistor R86, the other end of the resistor R86 is grounded, the pin 38 of the chip U10 is connected with one end of a resistor R81, one end of a crystal oscillator X2 and one end of a capacitor C163, the pin 39 of the chip U10 is connected with the other end of a resistor R81, the other end of the capacitor C63164 and the other end of the capacitor C163 are connected with the other end of the capacitor C9, and the other end of the chip U81 are connected with the resistor R103 and the capacitor C9, One end of a capacitor C165, one end of a resistor R104 and one end of a diode D3, the other end of a resistor R103 and the other end of a diode D3 are connected with a PHY _ POWER POWER supply, and the other end of the capacitor C165 is grounded.
6. The intelligent data monitoring and processing platform for the health state of the manned aircraft according to claim 5, wherein: a pin 6 of the chip U10 is connected with one end of a resistor R108, the other end of the resistor R108 is connected with a base of a triode Q4, a collector of a triode Q4 is connected with one end of a diode D4, the other end of a diode D4 is connected with one end of a resistor R105, the other end of the resistor R105 is connected with a DVDD _3V3 power supply, a pin 8 of the chip U10 is connected with one end of a resistor R83, one end of a resistor R83 is connected with a base of a triode Q2, a collector of a triode Q2 is connected with one end of a diode D1, the other end of a diode D1 is connected with one end of a resistor R82, the other end of a resistor R82 is connected with a DVDD _3V3 power supply, a pin 9 of a chip U10 is connected with one end of a resistor R87, the other end of the resistor R87 is connected with a base of a triode Q3, a collector of a triode Q3 is connected with one end of a diode D2, the other end of a diode D2 is connected with one end of a resistor R85, and the other end of a resistor DVR 85 is connected with a DD _3V3 power supply;
the 3 feet of the chip U10 are connected with one end of a resistor R106, one end of a resistor R107, one end of a resistor R109 and one end of a resistor R110, the other end of the resistor R106 is connected with one end of a resistor R94, the other end of the resistor R94 is connected with 64 feet of the chip U10, the other end of the resistor R107 is grounded, the other end of the resistor R109 is connected with 6 feet of the chip U10, the other end of the resistor R110 is connected with 8 feet of the chip U10, the 2 feet of the chip U10 is connected with one end of a resistor R111, one end of a resistor R112 and one end of a resistor R113, the other end of the resistor R111 is connected with one end of a resistor R94, the other end of the resistor R94 is connected with 64 feet of the chip U10, the other end of the resistor R112 is grounded, and the other end of the resistor R113 is connected with 6 feet of the chip U10.
7. The intelligent data monitoring and processing platform for the health state of the manned aircraft according to claim 5, wherein: the 45 pin of the chip U10 is connected with the AF4 pin of the chip U1D, the 48 pin of the chip U10 is connected with the AE5 pin of the chip U1D, the 60 pin of the chip U10 is connected with the AG5 pin of the chip U1D, the 63 pin of the chip U10 is connected with the AE10 pin of the chip U1D, the 62 pin of the chip U10 is connected with the AE12 pin of the chip U1D, the 61 pin of the chip U10 is connected with the AF 10 pin of the chip U1 10, the 59 pin of the chip U10 is connected with the AF 10 pin of the chip U1 10, the 58 pin of the chip U10 is connected with the AG10 pin of the chip U1 10, the 53 pin of the chip U10 is connected with the AF 10 pin of the chip U1 10, the 49 pin of the chip U10 is connected with the AF 10 pin of the chip U1 10, the pin of the chip U72 is connected with the AF 10 pin of the AF 10, the AE10 pin of the chip U10 is connected with the AE10 of the chip U1, the chip AH 72, and the AE10 of the chip U10 is connected with the chip U72.
8. The intelligent data monitoring and processing platform for the health state of the manned aircraft according to claim 5, wherein: the internal bus communication interface (103) further comprises a chip U11 and a chip U12, the models of the chip U11 and the chip U12 are IP4292CZ10-TBR, the 10 pin of the chip U11 is connected with the 31 pin of the chip U10, the 9 pin of the chip U11 is connected with the 30 pin of the chip U10, the 7 pin of the chip U11 is connected with the 26 pin of the chip U10, the 6 pin of the chip U11 is connected with the 25 pin of the chip U10, the 1 pin of the chip U11 is connected with the 1 pin of a network interface J11, the 2 pin of the chip U11 is connected with the 2 pin of the network interface J11, the 4 pin of the chip U11 is connected with the 3 pin of the network interface J11, and the 5 pin of the chip U11 is connected with the 6 pin of the network interface J11;
the 10 pin of the chip U12 is connected with the 24 pin of the chip U10, the 9 pin of the chip U12 is connected with the 23 pin of the chip U10, the 7 pin of the chip U12 is connected with the 20 pin of the chip U10, the 6 pin of the chip U12 is connected with the 19 pin of the chip U10, the 1 pin of the chip U12 is connected with the 4 pin of the network interface J11, the 2 pin of the chip U12 is connected with the 5 pin of the network interface J11, the 4 pin of the chip U12 is connected with the 7 pin of the network interface J11, and the 5 pin of the chip U12 is connected with the 8 pin of the network interface J11.
9. The manned vehicle health status data intelligent monitoring processing platform of claim 2, wherein: the LVDS video display interface (101) comprises an interface J12, the MIPI image data input interface (104) comprises an interface J13, an 8 pin of the interface J13 and a 10 pin of the interface J12 are connected with a chip U13, the model of the chip U13 is TXS0108E, a 4 pin of the chip U13 is connected with an 8 pin of the interface J13 and a 10 pin of the interface J12, a 5 pin of the chip U13 is connected with a 6 pin of the interface J13 and a 12 pin of the interface J12, a 6 pin of the chip U13 is connected with one end of a resistor R122, the other end of the resistor R122 is connected with a 12 pin of the interface J13, a 16 pin of the interface J12 and one end of a resistor R131, the other end of the resistor R131 is connected with a3 pin of a crystal oscillator X3, a 4 pin of the crystal oscillator X3 is connected with one end of a capacitor C186 and connected with a DVDD _1V8 power supply, the other end of the capacitor C186 is grounded, a 10 pin of the chip U13 is connected with one end of a resistor R121 and the other resistor V8 is connected with a DVDD 8.
10. The manned vehicle health status data intelligent monitoring processing platform of claim 9, wherein: a pin 3 of the interface J13 is connected with one end of a resistor R119, the other end of the resistor R119 is connected with one end of a resistor R120, the other end of the resistor R120 is connected with a pin 5 of an interface J12, a pin 5 of an interface J13 is connected with one end of a resistor R123, the other end of the resistor R123 is connected with one end of a resistor R124, the other end of the resistor R124 is connected with a pin 7 of an interface J12, a pin 4 of the interface J13 is connected with one end of a magnetic bead inductor FB10, the other end of the magnetic bead inductor FB10 is connected with an AVDD28 power supply, a pin 10 of the interface J13 is connected with one end of a magnetic bead inductor FB11, the other end of the magnetic bead inductor FB11 is connected with a DVDD12 power supply, a pin 11 of the interface J13 is connected with one end of a magnetic bead inductor FB12, and the other end of the magnetic bead inductor FB12 is connected with a DVDD _1V8 power supply;
a pin 14 of the interface J13 is connected with a pin AJ13 of the chip U1E, a pin 15 of the interface J13 is connected with a pin AK13 of the chip U1E, a pin 16 of the interface J13 is connected with a pin AJ12 of the chip U1E, a pin 17 of the interface J13 is connected with a pin AK12 of the chip U1E, a pin 18 of the interface J13 is connected with a pin AJ10 of the chip U1E, a pin 19 of the interface J13 is connected with a pin AK10 of the chip U1E, a pin 20 of the interface J13 is connected with a pin AJ9 of the chip U1E, a pin 21 of the interface J13 is connected with a pin AK9 of the chip U1E, a pin 23 of the interface J13 is connected with a pin AJ11 of the chip U1E, and a pin 24 of the interface J13 is connected with a pin AK11 of the chip U1E;
the pin 11 of the interface J12 is connected with one end of a resistor R125, the other end of the resistor R125 is connected with an AK11 pin of a chip U1E, the pin 13 of the interface J12 is connected with one end of a resistor R126, the other end of the resistor R126 is connected with an AJ11 pin of the chip U1E, the pin 15 of the interface J12 is connected with one end of a resistor R127, the other end of the resistor R127 is connected with an AK9 pin of the chip U1E, the pin 17 of the interface J12 is connected with one end of a resistor R128, the other end of the resistor R128 is connected with an AJ9 pin of the chip U1E, the pin 19 of the interface J12 is connected with one end of a resistor R129, the other end of the resistor R129 is connected with an AK10 pin of the chip U1E, the pin 21 of the interface J12 is connected with one end of a resistor R130, the other end of the resistor R130 is connected with an AJ10 pin of the chip U1E, the pin 24 of the interface J12 is connected with one end of a magnetic bead inductor FB13, and the other end of the magnetic bead FB13 is grounded.
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